CN104952871A - Hybrid crystal orientation based junctionless CMOS (complementary metal oxide semiconductor) structure - Google Patents
Hybrid crystal orientation based junctionless CMOS (complementary metal oxide semiconductor) structure Download PDFInfo
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- CN104952871A CN104952871A CN201510276547.9A CN201510276547A CN104952871A CN 104952871 A CN104952871 A CN 104952871A CN 201510276547 A CN201510276547 A CN 201510276547A CN 104952871 A CN104952871 A CN 104952871A
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Abstract
The invention discloses a hybrid crystal orientation based junctionless CMOS (complementary metal oxide semiconductor) structure. The junctionnless CMOS structure comprises a junctionless NMOS (N-channel metal oxide semiconductor) structure, a junctionless PMOS (P-channel metal oxide semiconductor) structure and a silicon chip. Top silicon made of (100) crystal-face monocrystalline silicon is arranged on a silicon substrate made of (110) crystal-face monocrystalline silicon through a buried oxide layer to form the silicon chip. The junctionless NMOS structure is arranged on the (100) crystal-face top silicon, and the junctionless PMOS structure is arranged on the (110) crystal-face silicon substrate. The junctionless NMOS structure corresponds to the (100) crystal-face top silicon highest in electron mobility, and the junctionless PMOS structure corresponds to the (110) crystal-face silicon substrate highest in hole mobility, so that electron mobility of the junctionless NMOS structure and hole mobility of the junctionless PMOS structure can be improved.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing equipment field, relate to a kind of crystallographic orientation without knot CMOS structure.
Background technology
From first transistor invention to the extensive use of very lagre scale integrated circuit (VLSIC), Moore's Law instructs the development speed of microelectronics industry.But be constantly contracted to 65nm even below 22nm along with device critical dimensions, further reduction of device critical size becomes more and more difficult to improve performance, and this brings great challenge to integrated circuit fabrication process.New device is not also had to replace silicon CMOS when the existing main flow silicon technology of compatibility at present.In addition, existing cmos circuit is also subject to the unmatched restriction of mobility.In silicon materials, hole mobility only has about 1/3 of electron mobility, in order to make the drive current of NMOS with PMOS consistent, must increase the breadth length ratio of PMOS device, and this can make the speed of circuit and integrated level all be affected, and reduces circuit performance.In order to address this problem, an effective way improves the conductivity of channel material, improves the mobility of hole and electronics, strengthens drive current, improves circuit performance.
Crystallographic orientation technology (hybrid crystal orientation technology, HOT) technique is proposed by IBM IEDM2003 at first, it adopts different crystal face Si substrate for n-MOSFET and p-MOSFET, effectively can increase hole mobility, thus improve CMOS performance.At present, the research based on crystallographic orientation technological development cmos circuit has some to report.Specifically, 2003, the people such as the Yang of IBM creatively proposed the crystallographic orientation technology based on SOI, were promoted the mobility of charge carrier by the surface orientation optimizing substrate and raceway groove, thus can boost device performance.The crystallographic orientation technology that the people such as M.Yang propose is a kind of technology based on SOI, on the same wafer, can prepare n-MOSFET respectively prepare p-MOSFET with (110) crystal face region in (100) crystal face region.In the art, related process is adopted to transfer on (100) monocrystalline silicon piece by (110) monocrystalline silicon layer, or (100) monocrystalline silicon layer is transferred on (110) monocrystalline silicon piece, prepare the globalize crystallographic orientation SOI substrate that top layer silicon is different from Substrate orientation.(100) on crystal face, the electron mobility of nMOSFET is higher, and the hole mobility on (110) crystal face is higher.
The article " Nanowire transistors without junctions " that the structure of Juctionless MOSFET is published on Nature Nanotechnology by people such as J.-P.Colinge first for 2010 reported.In the past all MOSFET are against the knot work that formed of foreign atom introduced.When critical size drops to about 10nm, in order to suppress short-channel effect, very high doping content gradient variable obtains very necessary.Due to the restriction of the physical law in Impurity Diffusion process, technique produces so high doping content gradient very difficult.This device without knot does not need to make the very large PN junction of concentration gradient, does not use expensive rapid thermal annealing, so this structure substantially reduces complexity and the cost of manufacture technics.The device of this structure has the repertoire of CMOS, and subthreshold swing is close to ideal value, has low-down leakage current, and mobil-ity degradation is much less than common MOSFET when grid voltage and temperature raise.The details of Junctionless MOSFET operation principle can be published in the article " Nanowire transistors without junctions " on Nature Nanotechnology for 2010 referring to people such as J.-P.Coling.In brief, the principle of its conduction is the modulation utilizing grid voltage to channel carrier concentration, exhausts the electronics in grid lower body silicon when closing device.Its electric current passes through in the inside of body silicon, avoids the surperficial inversion mode of conventional MOS FET On current, avoids the mobil-ity degradation that interface scattering causes.The key of Junctionless MOSFET manufacturing process is to produce very little device widths and thickness so that grid voltage can charge carrier in depleted body silicon when OFF state.
Junctionless MOSFET is faced with the too small predicament of carrier mobility: according to the report of document " Nanowire transistors without junctions ", the electron mobility of N-type Junctionless MOSFET is 100cm2V-1S-1, the hole mobility of P type Junctionless MOSFET is 40cm2V-1S-1, and the impurity concentration now in silicon is 1e19 to 1e20/cm3.This for common long ditch MOSFET be quite little.Certainly, this less mobility also common manifestation at short ditch as in the MOSFET of 40nm technology node.
In sum, those skilled in the art need badly provides a kind of crystallographic orientation without knot CMOS structure, crystallographic orientation technology is applied to without knot CMOS structure, to solve without the little problem in the hole and electron mobility of tying CMOS structure, improves the integrated level of the chip without knot CMOS structure, speed and performance.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of crystallographic orientation without knot CMOS structure, crystallographic orientation technology is applied to without knot CMOS structure, to solve without the little problem in the hole and electron mobility of tying CMOS structure, improve the integrated level of the chip without knot CMOS structure, speed and performance.
In order to solve the problems of the technologies described above, the invention provides a kind of crystallographic orientation without knot CMOS structure, described nothing knot CMOS structure comprises without knot NMOS structure and without knot PMOS structure, also comprise top layer silicon to be arranged on a silicon substrate by oxygen buried layer and the silicon chip formed, described top layer silicon material is (100) crystal face monocrystalline silicon, described silicon substrate material is (110) crystal face monocrystalline silicon, described nothing knot NMOS structure is located in the top layer silicon of (100) crystal face, and described nothing knot PMOS structure is located on the silicon substrate of (110) crystal face.
Preferably, described without knot NMOS structure with without tying PMOS structure by shallow trench isolation from separating.
Preferably, described silicon substrate is P-type silicon substrate.
Preferably, described silicon substrate is N-type doping.
Preferably, described silicon chip is the crystallographic orientation silicon chip utilizing hybrid crystal orientation substrate technology to prepare.
Compared with existing scheme, crystallographic orientation provided by the invention is without knot CMOS structure, by being located in the top layer silicon of (100) crystal face without knot NMOS structure, be located on the silicon substrate of (110) crystal face without knot PMOS structure, make the top layer silicon without the highest (100) crystal face of the corresponding electron mobility of knot NMOS structure, without the silicon substrate tying the highest (110) crystal face of the corresponding hole mobility of PMOS structure, thus improve without the electron mobility of knot NMOS structure and the hole mobility without knot PMOS structure, and then improve the integrated level of the chip without knot CMOS structure, speed and performance.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of crystallographic orientation of the present invention without knot CMOS structure.
Number in the figure is described as follows:
10, without knot CMOS structure; 20, without knot NMOS structure; 30, top layer silicon; 40, oxygen buried layer; 50, silicon substrate; 60, shallow trench isolation from.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.Those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
In the present invention, other example of exemplary embodiment can have different values.It should be noted that: represent similar terms in similar label and letter accompanying drawing below, therefore, once be defined in an a certain Xiang Yi accompanying drawing, then do not need to be further discussed it in accompanying drawing subsequently.As known in the art, { 100} family of crystal planes comprises (100) crystal face, (010) crystal face, (001) crystal face, and { 110} family of crystal planes comprises (110) crystal face, (101) crystal face, (011) crystal face, (1-10) crystal face, (10-1) crystal face, (01-1) crystal face; { 111} family of crystal planes then comprises (111) crystal face, (-111) crystal face, (1-11) crystal face, (11-1) crystal face.
Above-mentioned and other technical characteristic and beneficial effect, will in conjunction with the embodiments and accompanying drawing 1 crystallographic orientation of the present invention is described in detail without knot CMOS structure.
As shown in Figure 1, the invention provides a kind of crystallographic orientation without knot CMOS structure, comprise without knot NMOS structure 10 and without knot PMOS structure 20 without knot CMOS structure, the present invention is also comprised top layer silicon 30 and is arranged on the silicon chip that silicon substrate 50 is formed by oxygen buried layer 40, top layer silicon 30 material is (100) crystal face monocrystalline silicon, silicon substrate 50 material is (110) crystal face monocrystalline silicon, be located in the top layer silicon 30 of (100) crystal face without knot NMOS structure 10, be located on the silicon substrate 50 of (110) crystal face without knot PMOS structure 20.
Concrete, in the present embodiment, separated from 60 by shallow trench isolation without knot NMOS structure 10 with without knot PMOS structure 20.
Meanwhile, silicon substrate 50 is P-type silicon substrate, and silicon substrate 50 is N-type doping; Described silicon chip is the crystallographic orientation silicon chip utilizing hybrid crystal orientation substrate technology to prepare.
Because the hole mobility of (110) crystal face on <110> crystal orientation is than high 2 to 3 times on <110> crystal orientation of (100) crystal face, effectively can improve the performance of MOS device, and crystallographic orientation technology (HOT, Hybrid Crystal Orientation Technology) be exactly the substrate adopting different crystal face for NMOS and PMOS, to increase carrier mobility, thus improve CMOS performance.
The high-quality globalize crystallographic orientation (SOI utilizing hybrid crystal orientation substrate (Simbond) technology to prepare, Silicon-On-Insulator) silicon chip, the silicon substrate of (110) crystal face under having the top layer silicon of (100) crystal face be arranged on and being arranged on is formed, oxygen buried layer isolation top layer silicon and silicon substrate.
Owing at same crystal orientation material being PMOS structure and the NMOS structure of substrate, about the hole mobility of PMOS structure only has the half of the electron mobility of NMOS structure, so in CMOS integrated circuit, in order to improve circuit working speed, both the effect of high frequency, often needs to increase CMOS channel width, the especially width of PMOS, but the integration density of circuit, the parasitic capacitance of increased device will be reduced to design raising speed for target, and the hole mobility of (110) crystal face on <110> crystal orientation is than high 2 to 3 times on <110> crystal orientation of (100) crystal face, effectively can improve the performance of MOS device, and the present invention utilizes this characteristic exactly, make the top layer silicon without the highest (100) crystal face of the corresponding electron mobility of knot NMOS structure, without the silicon substrate tying the highest (110) crystal face of the corresponding hole mobility of PMOS structure, to increase hole mobility, thus make PMOS structure reach relative balance with the carrier mobility in NMOS structure, to improve CMOS performance.
In sum, crystallographic orientation provided by the invention is without knot CMOS structure, by being located in the top layer silicon 30 of (100) crystal face without knot NMOS structure 10, be located on the silicon substrate 50 of (110) crystal face without knot PMOS structure 20, make the top layer silicon 30 without the highest (100) crystal face of the corresponding electron mobility of knot NMOS structure 10, without the silicon substrate 50 tying the highest (110) crystal face of the corresponding hole mobility of PMOS structure 20, thus improve without the electron mobility of knot NMOS structure and the hole mobility without knot PMOS structure, and then improve the integrated level of the chip without knot CMOS structure, speed and performance.
Above-mentioned explanation illustrate and describes some preferred embodiments of the present invention, but as previously mentioned, be to be understood that the present invention is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in invention contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from the spirit and scope of the present invention, then all should in the protection range of claims of the present invention.
Claims (5)
1. a crystallographic orientation is without knot CMOS structure, described nothing knot CMOS structure comprises without knot NMOS structure and without knot PMOS structure, it is characterized in that, also comprise top layer silicon to be arranged on a silicon substrate by oxygen buried layer and the silicon chip formed, described top layer silicon material is (100) crystal face monocrystalline silicon, described silicon substrate material is (110) crystal face monocrystalline silicon, described nothing knot NMOS structure is located in the top layer silicon of (100) crystal face, and described nothing knot PMOS structure is located on the silicon substrate of (110) crystal face.
2. crystallographic orientation according to claim 1 is without knot CMOS structure, it is characterized in that, described without knot NMOS structure with without tying PMOS structure by shallow trench isolation from separating.
3. crystallographic orientation according to claim 1 is without knot CMOS structure, and it is characterized in that, described silicon substrate is P-type silicon substrate.
4. crystallographic orientation according to claim 3 is without knot CMOS structure, it is characterized in that, described silicon substrate is N-type doping.
5. according to the arbitrary described crystallographic orientation of Claims 1 to 4 without knot CMOS structure, it is characterized in that, described silicon chip is the crystallographic orientation silicon chip utilizing hybrid crystal orientation substrate technology to prepare.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105448845A (en) * | 2015-12-17 | 2016-03-30 | 中航（重庆）微电子有限公司 | Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof |
| CN105529305A (en) * | 2015-12-17 | 2016-04-27 | 中航（重庆）微电子有限公司 | Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof |
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| CN103700631A (en) * | 2013-11-29 | 2014-04-02 | 上海华力微电子有限公司 | Preparation method for non-junction MOS FET (metal oxide semiconductor field effect transistor) device |
| US20150102469A1 (en) * | 2013-10-16 | 2015-04-16 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor structure including laterally disposed layers having different crystal orientations and method of fabricating the same |
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| US20060113605A1 (en) * | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid fin field-effect transistor structures and related methods |
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| US20150102469A1 (en) * | 2013-10-16 | 2015-04-16 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor structure including laterally disposed layers having different crystal orientations and method of fabricating the same |
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Cited By (3)
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| CN105448845A (en) * | 2015-12-17 | 2016-03-30 | 中航（重庆）微电子有限公司 | Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof |
| CN105529305A (en) * | 2015-12-17 | 2016-04-27 | 中航（重庆）微电子有限公司 | Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof |
| CN105448845B (en) * | 2015-12-17 | 2019-02-05 | 华润微电子（重庆）有限公司 | Three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof |
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