CN105448845A - Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof - Google Patents
Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof Download PDFInfo
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- 239000013078 crystal Substances 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000012212 insulator Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 100
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 99
- 239000010703 silicon Substances 0.000 claims abstract description 99
- 230000000873 masking effect Effects 0.000 claims abstract description 72
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 53
- 238000005516 engineering process Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000008569 process Effects 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 297
- 239000000463 material Substances 0.000 claims description 50
- 238000002360 preparation method Methods 0.000 claims description 22
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 16
- 239000000126 substance Substances 0.000 claims description 13
- 238000003701 mechanical milling Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 239000002210 silicon-based material Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000012995 silicone-based technology Methods 0.000 abstract description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052732 germanium Inorganic materials 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 6
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- 230000010354 integration Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
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- 238000006479 redox reaction Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Abstract
The invention provides a three-layer hybrid crystal orientation on-insulator semiconductor structure and a fabrication method thereof. The semiconductor structure comprises a substrate, a first masking layer, a first groove, a GaN layer, a second groove, a first side wall structure, a single-crystal silicon layer, a third groove, a second side wall structure and a GeSi layer, wherein the upper surfaces of the GeSi layer, the GaN layer and the single-crystal silicon layer are flush on the same plane, the surface of the GaN layer is used for subsequent fabrication of a high-frequency (ultra) high-voltage GaN device, (100) the surface of a crystal-surface GeSi layer is used for subsequent fabrication of high-frequency (ultra) low-voltage GeSi device so that the hole carrier mobility is favorably and fully improved; (100) the surface of the crystal-surface single-crystal silicon layer is used for subsequent fabrication of an ordinary silicon-based device so that a silicon-on-insulator (SOI) technology, a GeSi technology, GaN technology and an ordinary silicon-based technology are fully utilized to make high-frequency, (ultra) high-voltage, (ultra) high-voltage, high-reliability and ordinary silicon-based nanoscale devices integrated and designed in a planer semiconductor integrated circuit, and an advanced structure and process technology is provided.
Description
Technical field
The invention belongs to field of manufacturing semiconductor devices, particularly relate to a kind of three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof.
Background technology
At present, under normal circumstances, crystallographic orientation SOI refers to the different soi structure of the crystal face of substrate silicon and top layer silicon, its objective is NMOSFET and PMOSFET be prepared in respectively (100) crystal face and (110) crystal face silica-based on, thus under the mobility keeping electronic carrier in NMOSFET, fully increase the mobility of holoe carrier in PMOSFET, fully balance to make NMOSFET and PMOSFET operating current, increase cmos circuit function, simplify cmos circuit design.
Based on above-mentioned conventional crystallographic orientation soi structure, the papers " localization mixed crystal orientation strain silicon CMOS structure and preparation method thereof " be published on " semiconductor technology " 2012Vol.37No.8 phase such as Huang Xiao big shield propose a kind of localization mixed crystal orientation strain silicon CMOS structure and preparation method thereof, the operations such as logical hard mask deposit, photoetching, dry etching, extension, CMP, wet etching, (110) silicon face and (100) silicon face is made to realize complanation, then NMOSFET and PMOSFET is prepared respectively at grade, as shown in Figure 1.
Meanwhile, the investigation and application of germanium silicon material and germanium material is just becoming the focus of semiconducter research at present, main because germanium tool has the following advantages: 1) hole mobility is maximum, is four times of silicon; Electron mobility is the twice of silicon.2) energy gap is smaller, is conducive to developing voltage devices.3) activationary temperature of alms giver/acceptor is far below silicon, is conducive to saving heat budget.4) little bohr exciton radii, contributes to the field emission characteristic improving it.5) little energy gap, contributes to combining dielectric material, reduces leakage current.But the shortcoming of germanium also clearly, and germanium belongs to comparatively active material, easily there is redox reaction with the interface of dielectric material in it, generates GeO, produce more defect, and then affect the performance of material.But along with the development of semiconductor technology, the shortcoming of germanium silicon material and germanium material is overcome just gradually, and advantage can be utilized very well, at present, industry makes great progress using germanium silicon or germanium material in exploitation in the ultralow pressure high-frequency element of backing material.
In addition, the research and apply of GaN material is forward position and the focus of the research of current global semiconductor, it is the novel semiconductor material of development microelectronic component, opto-electronic device, and together with the semi-conducting material such as SIC, diamond, being described as is third generation semi-conducting material after first generation Ge, Si semi-conducting material, second generation GaAs, InP compound semiconductor materials.It has character and the strong Radiation hardness such as wide direct band gap, strong atomic bond, high thermal conductivity, chemical stability good (hardly by any acid corrosion), has wide prospect in photoelectron, high temperature high power device and high-frequency microwave device application aspect.Usually, because lattice structure is close, the general GaN material stable by the silicon crystal lattice surface extension generation lattice structure at (111) crystal face.
Due to the difference of backing material, how to have made full use of SOI technology, germanium silicon technology, GaN technology by the nanoscale devices Integration Design of high frequency, (surpassing) high pressure, (surpassing) low pressure, high reliability in a planar-type semiconductor integrated circuit, industry does not still have correlative study.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure, think that high frequency, (surpassing) high pressure, (surpassing) low pressure, high reliability and conventional silicon-based nano level device integration are designed into the structure &processes technology providing a kind of advanced person in a planar-type semiconductor integrated circuit by SOI technology, germanium silicon technology, GaN technology, conventional silicon-based technologies.
For achieving the above object and other relevant objects, the invention provides a kind of manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure, comprise step: a) provide a substrate, described substrate comprises the silicon top layer in the silicon bottom in the first crystal orientation stacked gradually, the first insulating barrier, the silicon intermediate layer in the second crystal orientation, the second insulating barrier and the 3rd crystal orientation; B) above described silicon top layer, form the first masking layer, formed until the first groove of described silicon top layer in the position for preparation the first device area, in described first groove, form GaN layer; C) formed until the second groove of silicon bottom in the position for preparation the second device area, in described second groove, form the first sidewall structure, in described second groove, then form the monocrystalline silicon layer with the first crystal orientation; D) formed until the 3rd groove in silicon intermediate layer in the position for preparation the 3rd device area, the second sidewall structure is formed in described 3rd groove, then in described 3rd groove, GeSi material is formed, and adopt oxidation concentration technology Ge is concentrated and diffuses into silicon intermediate layer downwards, make all to form GeSi layer in silicon interlayer region and the 3rd groove.
As a kind of preferred version of the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, in described manufacture method, step execution sequence a), b), c), d) is: a), b), c), d) or a), b), d), c) or a), c), b), d) or a), c), d), b) or a), d), b), c) or a), d), c), b).
As a kind of preferred version of the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, the growth thickness of described GaN layer, monocrystalline silicon layer and GeSi layer is at least make the upper surface of described GaN layer, monocrystalline silicon layer and GeSi layer maintain an equal level at grade.
As a kind of preferred version of the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, step b) in, the upper surface of the described GaN layer of formation is made to exceed described first masking layer, draw together afterwards and adopt chemical mechanical milling tech to remove unnecessary GaN material, the upper surface of GaN layer and described first masking layer upper surface are maintained an equal level; Step c) in, described second groove is formed by forming second masking layer with etching window, and make the upper surface of the described monocrystalline silicon layer of formation exceed described second masking layer, adopt chemical mechanical milling tech to remove unnecessary single crystal silicon material afterwards, the upper surface of monocrystalline silicon layer and described second masking layer upper surface are maintained an equal level; Steps d) in, described second groove is formed by forming the 3rd masking layer with etching window, and make the upper surface of the described GeSi layer of formation exceed described 3rd masking layer, adopt chemical mechanical milling tech to remove unnecessary GeSi material afterwards, the upper surface of GeSi layer and described 3rd masking layer upper surface are maintained an equal level.
As a kind of preferred version of the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, the material of described first masking layer, the second masking layer and the 3rd masking layer comprises Si
3n
4and SiO
2in one or its combination, the material of described first sidewall structure and the second sidewall structure comprises Si
3n
4and SiO
2in one or its combination.
As a kind of preferred version of the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, also comprise step: what produce in employing chemical mechanical milling tech removal technical process is positioned at GaN layer, and/or monocrystalline silicon layer, and/or the unnecessary masking layer above GeSi layer, and described GaN layer, monocrystalline silicon layer and GeSi layer surface is maintained an equal level; Or what first produce in employing wet etching removal technical process is positioned at GaN layer, and/or monocrystalline silicon layer, and/or the unnecessary masking layer above GeSi layer, then adopt chemical mechanical milling tech that described GaN layer, monocrystalline silicon layer and GeSi layer surface is maintained an equal level.
As a kind of preferred version of the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, steps d) in what adopt is globalize wafer surface dry-oxygen oxidation technique with oxidation concentration technology.
As a kind of preferred version of the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, described 3rd crystal orientation is (111) crystal orientation.
As a kind of preferred version of the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, described first crystal orientation is (100), and the second crystal orientation is (110); Or described first crystal orientation is (110), the second crystal orientation is (100).
The present invention also provides a kind of three layers of crystallographic orientation semiconductor-on-insulator structure, comprise: substrate, described substrate comprises the silicon top layer in the silicon bottom in the first crystal orientation stacked gradually, the first insulating barrier, the silicon intermediate layer in the second crystal orientation, the second insulating barrier and the 3rd crystal orientation; First masking layer, is formed at described silicon topsheet surface; First groove, is formed in described first masking layer, and exposes and have silicon topsheet surface; GaN layer, is formed in described first groove; Second groove, extends in described substrate from described structure upper surface, and contacts silicon bottom surface bottom it; ; First sidewall structure, is formed at described second recess sidewall; The monocrystalline silicon layer in the first crystal orientation, is formed in described second groove; 3rd groove, extends in described substrate from described structure upper surface, and contacts silicon intermediate layer bottom it; Second sidewall structure, is formed at described 3rd recess sidewall; GeSi layer, the silicon interlayer region being formed in described 3rd groove and connecting with described 3rd groove.
As a kind of preferred version of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, the upper surface of described GaN layer, monocrystalline silicon layer and GeSi layer maintains an equal level at grade.
As a kind of preferred version of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, described 3rd crystal orientation is (111) crystal orientation.
As a kind of preferred version of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, described first crystal orientation is (100), and the second crystal orientation is (110); Or described first crystal orientation is (110), the second crystal orientation is (100).
As a kind of preferred version of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention, the material of described first masking layer comprises Si
3n
4and SiO
2in one or its combination, the material of described first sidewall structure and the second sidewall structure comprises Si
3n
4and SiO
2in one or its combination.
As mentioned above, three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention and preparation method thereof, there is following beneficial effect: the invention provides a kind of three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof, high frequency (surpassing) high voltage gan device is prepared for follow-up in GaN layer surface, (110) crystal face germanium silicon surface prepares high frequency (surpassing) low pressure SiGe device for follow-up, be beneficial to fully increase hole carrier mobility, (100) crystal face monocrystalline surface is used for the conventional silicon-based devices of follow-up preparation, thus make full use of SOI technology, germanium silicon technology, GaN technology, conventional silicon-based technologies is by high frequency, (surpassing) high pressure, (surpassing) low pressure, high reliability and conventional silicon-based nano level device integration are designed into the structure providing a kind of advanced person in a planar-type semiconductor integrated circuit, technology.Simply, Be very effective, is with a wide range of applications in field of semiconductor manufacture for structure of the present invention and method.
Accompanying drawing explanation
Fig. 1 is shown as the schematic diagram of a kind of mixed crystal orientation strain silicon CMOS structure that localizes of the prior art.
Fig. 2 is shown as the manufacture method steps flow chart schematic diagram of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention.
The structural representation that each step of manufacture method that Fig. 3 ~ Figure 13 is shown as three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention presents.Wherein, Figure 13 is shown as the final structure schematic diagram of three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention.
Element numbers explanation
101 silicon bottoms
102 first insulating barriers
103 silicon intermediate layers
104 second insulating barriers
105 silicon top layers
106 first masking layers
107GaN layer
108 second masking layers
109 first sidewall structures
110 monocrystalline silicon layers
111 the 3rd masking layers
112 second sidewall structures
113GeSi layer
114SiO
2layer
S11 ~ S14 step 1) ~ step 4)
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 2 ~ Figure 13.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in diagram but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment 1
As shown in Fig. 2 ~ Figure 13, the present embodiment provides a kind of manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure, comprises step:
As shown in Figures 2 and 3, first carry out step 1) S11, there is provided a substrate, described substrate comprises silicon intermediate layer 103, second insulating barrier 104 in silicon bottom 101, first insulating barrier 102, second crystal orientation and the silicon top layer 105 in the 3rd crystal orientation in the first crystal orientation stacked gradually.
In the present embodiment, described first crystal orientation is (100), second crystal orientation is (110), 3rd crystal orientation is (111), particularly, described substrate comprises silicon bottom 101, first silicon dioxide layer in (100) crystal orientation stacked gradually, silicon intermediate layer 103, second silicon dioxide layer in (110) crystal orientation and the silicon top layer 105 in (111) crystal orientation.
As shown in Fig. 2 and Fig. 4 ~ Fig. 5, then carry out step 2) S12, above described silicon top layer 101, form the first masking layer 106, and formed until the first groove of described silicon top layer 105 in the position for preparation the first device area, in described first groove, form GaN layer 107.
Exemplarily, described first masking layer 106 is hard mask, and its material can be SiO
2or Si
3n
4.In the present embodiment, the material of described first masking layer 106 is Si
3n
4.
Particularly, comprise the following steps:
Step 2-1), in described silicon top layer 105 surface deposition Si
3n
4layer;
Step 2-2), in described Si
3n
4the surperficial spin coating photoresist of layer, and adopt photoetching process to open window in the position for preparation the first device area, form litho pattern;
Step 2-3), based on described litho pattern, adopt dry etch process to etch described Si
3n
4layer, to exposing described silicon top layer 105, forms the first groove;
Step 2-4), adopt epitaxy technique, with (111) the silicon top layer 105 in the first groove for inculating crystal layer, growing GaN layer 107, its growing height need exceed the upper surface of described first masking layer; Stablize and the higher GaN material of quality because lattice structure can obtain lattice structure close to the silicon crystal lattice surface epitaxial growth at (111) crystal face;
Step 2-5), adopt CMP (cmp) technique to remove unnecessary GaN, the upper surface of GaN upper surface and the first masking layer is maintained an equal level.
As shown in Fig. 2 and Fig. 6 ~ Fig. 9, then carry out step 3) S13, make the second masking layer 108, and formed until the second groove of silicon bottom 101 in the position for preparation the second device area, in described second groove, form the first sidewall structure 109, in described second groove, then form the monocrystalline silicon layer 110 with the first crystal orientation.
Exemplarily, described second masking layer 108 is selected as hard mask, and its material can be SiO
2or Si
3n
4.In the present embodiment, the material of described second masking layer 108108 is Si
3n
4.
Particularly, comprise the following steps:
Step 3-1), in described GaN layer 107 and the first masking layer 106 surface deposition Si
3n
4layer;
Step 3-2), in described Si
3n
4the surperficial spin coating photoresist of layer, and adopt photoetching process to open window in the position for preparation the second device area, form litho pattern;
Step 3-3), based on described litho pattern, adopt dry etch process to etch described Si
3n
4layer and described substrate, to exposing described silicon bottom 101, form the second groove;
Step 3-4), in described second groove, prepare the first sidewall structure 109 by the technique such as deposit, etching, described first sidewall structure 109 material can be Si
3n
4or SiO
2or both combination or other spacer material, and (100) the silicon bottom 101 in the second groove is exposed;
Step 3-5), adopt epitaxy technique, with (100) the silicon bottom 101 in the second groove for inculating crystal layer, growth (100) monocrystalline silicon layer 110, its growth thickness need more than the second masking layer upper surface;
Step 3-6), then adopt CMP (cmp) technique to remove unnecessary (100) monocrystalline silicon, the upper surface of (100) monocrystalline silicon and the upper surface of the second masking layer are maintained an equal level,
Step 3-7) remove unnecessary (100) monocrystalline silicon and the second masking layer 108, the upper surface of (100) monocrystalline silicon and the upper surface of described GaN layer 107 are maintained an equal level.
As shown in Fig. 2 and Figure 10 ~ Figure 13, finally carry out step 4) S14, make the 3rd masking layer 111, and formed until the 3rd groove in silicon intermediate layer 103 in the position for preparation the 3rd device area, the second sidewall structure 112 is formed in described 3rd groove, then in described 3rd groove and the 3rd masking layer 111 surface form GeSi material, and adopt oxidation concentration technology Ge is concentrated and diffuses into silicon intermediate layer 103 downwards, make all to form GeSi layer 113 in silicon interlayer region and the 3rd groove.
Exemplarily, described 3rd masking layer 111 is selected as hard mask, and its material can be SiO
2or Si
3n
4.In the present embodiment, the material of described 3rd masking layer 111 is Si
3n
4.Described 3rd device substrate material is the monocrystalline silicon in (110) crystal orientation.
Particularly, comprise the following steps:
Step 4-1), in described GaN layer 107, first masking layer 106 and (100) monocrystalline silicon surface deposition Si
3n
4layer;
Step 4-2), in described Si
3n
4the surperficial spin coating photoresist of layer, and adopt photoetching process to open window in the position for preparation the 3rd device area, form litho pattern;
Step 4-3), based on described litho pattern, adopt dry etch process to etch described Si
3n
4layer and described substrate, to exposing described silicon intermediate layer 103, form the 3rd groove;
Step 4-4), in described 3rd groove, prepare the second sidewall structure 112 by the technique such as deposit, etching, described second sidewall structure 112 material can be Si
3n
4or SiO
2or both combination or other spacer material, and (110) the silicon intermediate layer 103 in the 3rd groove is exposed;
Step 4-5), adopt epitaxy technique, with (110) the silicon bottom 101 in the 3rd groove for inculating crystal layer, growth GeSi material, its growth thickness need more than the 3rd masking layer upper surface, and, there is segment thickness to be covered in described 3rd masking layer upper surface;
Step 4-6), carry out globalize wafer surface dry-oxygen oxidation, at this moment, the top of GeSi material is the SiO that oxidation is formed
2layer, GeSi material is oxidized gradually to concentrate and Ge is concentrated downwards and diffuses into silicon intermediate layer 103, makes all to form GeSi layer 113 in silicon interlayer region and the 3rd groove;
Step 4-7), adopt wet etching or dry etching, and CMP (cmp) technique removes the SiO of globalize surface oxidation generation
2layer and hard mask, make the upper surface of GeSi layer 113 upper surface and the 3rd masking layer maintain an equal level;
Step 4-8), remove unnecessary GeSi material and the 3rd masking layer 111, the upper surface of the upper surface of the upper surface of GeSi layer 113 and described GaN layer 107 and (100) monocrystalline silicon is maintained an equal level at grade.
Certainly, above-mentioned steps 3-7) and step 4-8) can first not carry out, like this, after completing in steps, carry out step 5), what produce in employing chemical mechanical milling tech removal technical process is positioned at GaN layer 107, and/or monocrystalline silicon layer 110, and/or the unnecessary masking layer above GeSi layer 113, and the upper surface of the upper surface of described GeSi layer 113 and the upper surface of described GaN layer 107 and (100) monocrystalline silicon is maintained an equal level at grade; What also can first adopt wet etching to remove in technical process to produce is positioned at GaN layer 107, and/or monocrystalline silicon layer 110, and/or the unnecessary masking layer above GeSi layer 113, then adopt chemical mechanical milling tech that the upper surface of the upper surface of described GeSi layer 113 and the upper surface of described GaN layer 107 and (100) monocrystalline silicon is maintained an equal level at grade.Thus complete the substrate plane metallization processes method of three kinds of different materials substrate devices.
Finally, GaN base high frequency (surpassing) high voltage gan device can be made in described GaN layer 107, high frequency (surpassing) low pressure SiGe device is prepared on described (110) crystal face GeSi layer 113 surface, be beneficial to fully increase hole carrier mobility, the monocrystalline silicon in described (100) crystal orientation makes conventional silicon-based devices, thus make full use of SOI technology, germanium silicon technology, GaN technology, conventional silicon-based technologies is by high frequency, (surpassing) high pressure, (surpassing) low pressure, high reliability and conventional silicon-based nano level device integration are designed into the structure providing a kind of advanced person in a planar-type semiconductor integrated circuit, technology.
As shown in figure 13, the present embodiment also provides a kind of three layers of crystallographic orientation semiconductor-on-insulator structure, comprise: substrate, described substrate comprises silicon intermediate layer 103, second insulating barrier 104 in silicon bottom 101, first insulating barrier 102, second crystal orientation and the silicon top layer 105 in the 3rd crystal orientation in the first crystal orientation stacked gradually; Monocrystalline silicon layer 110, the 3rd groove, the second sidewall structure 112, the GeSi layer 113 in the first masking layer 106, first groove, GaN layer 107, second groove, the first sidewall structure 109, first crystal orientation, the silicon interlayer region being formed in described 3rd groove and connecting with described 3rd groove, wherein, the upper surface of the monocrystalline silicon in the upper surface of described GeSi layer 113, the upper surface of GaN layer 107 and the first crystal orientation maintains an equal level at grade.
Described substrate comprises silicon intermediate layer 103, second insulating barrier 104 in silicon bottom 101, first insulating barrier 102, second crystal orientation and the silicon top layer 105 in the 3rd crystal orientation in the first crystal orientation stacked gradually.In the present embodiment, described first crystal orientation is (100), second crystal orientation is (110), 3rd crystal orientation is (111), particularly, described substrate comprises silicon bottom 101, first silicon dioxide layer in (100) crystal orientation stacked gradually, silicon intermediate layer 103, second silicon dioxide layer in (110) crystal orientation and the silicon top layer 105 in (111) crystal orientation.
Described first masking layer 106 be formed at described silicon top layer 105 surface, described first groove type is formed in described first masking layer 106, and expose have silicon top layer 105 surface; Described GaN layer 107 is formed in described first groove.Exemplarily, the material of described first masking layer 106 comprises Si
3n
4and SiO
2in one or its combination, in the present embodiment, the material selection of described first masking layer 106 is Si
3n
4.
Described second groove extends in described substrate from described structure upper surface, and contacts bottom it at the bottom of silicon, 101 surfaces; Described first sidewall structure 109 is formed at described second recess sidewall; The monocrystalline silicon layer 110 in described first crystal orientation is formed in described second groove; Exemplarily, the material of described first sidewall structure 109 comprises Si
3n
4and SiO
2in one or its combination, in the present embodiment, the material of described first sidewall structure 109 is first with being Si
3n
4, described monocrystalline silicon layer 110 is the monocrystalline silicon in (100) crystal orientation.
Described 3rd groove extends in described substrate from described structure upper surface, and contacts silicon intermediate layer 103 bottom it; Described second sidewall structure 112 is formed at described 3rd recess sidewall; The silicon interlayer region that described GeSi layer 113 to be formed in described 3rd groove and to connect with described 3rd groove, namely GeSi material is formed with in described 3rd groove, and the silicon intermediate layer 103 to connect with described 3rd groove is converted to GeSi material, both form GeSi layer 113 together.Exemplarily, the material of described second sidewall structure 112 comprises Si
3n
4and SiO
2in one or its combination, in the present embodiment, the material of described second sidewall structure 112 is first with being Si
3n
4.
In addition, described GaN layer 107 can be used for make GaN base high frequency (surpassing) high voltage gan device, described (110) crystal face GeSi layer 113 surface can be used for making high frequency (surpassing) low pressure SiGe device, be beneficial to fully increase hole carrier mobility, the monocrystalline silicon in described (100) crystal orientation can be used for making conventional silicon-based devices, thus make full use of SOI technology, germanium silicon technology, GaN technology, conventional silicon-based technologies is by high frequency, (surpassing) high pressure, (surpassing) low pressure, high reliability and conventional silicon-based nano level device integration are designed into the structure providing a kind of advanced person in a planar-type semiconductor integrated circuit, technology.
Embodiment 2
The present embodiment provides a kind of manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure, its basic step is as embodiment 1, wherein, the execution sequence of each step in embodiment 1 is for first carry out step 1), after carry out step 2), then carry out step 4), finally carry out step 3 again), i.e. step 3) with step 4) execution sequence exchange.
Embodiment 3
The present embodiment provides a kind of manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure, its basic step is as embodiment 1, wherein, the execution sequence of each step in embodiment 1 is for first carry out step 1), after carry out step 3), then carry out step 2), finally carry out step 4 again).What deserves to be explained is, the manufacture method of this order needs the growth thickness being ensured described GeSi layer 113, GaN layer 107 and monocrystalline silicon layer 110 by the thickness controlling described first masking layer 106, second masking layer 108 and the 3rd masking layer 111, can maintain an equal level at grade to make the upper surface of described GeSi layer 113, GaN layer 107 and monocrystalline silicon layer 110.
In addition, described in the present embodiment 3, the execution sequence of each step in embodiment 1 also can be advanced row step 1), after carry out step 3), then carry out step 4), finally carry out step 2);
Or first carry out step 1), after carry out step 4), then carry out step 2), finally carry out step 3);
Or first carry out step 1), after carry out step 4), then carry out step 3), finally carry out step 2).
The example of several manufacture method above, only need the growth thickness being ensured described GeSi layer 113, GaN layer 107 and monocrystalline silicon layer 110 by the thickness controlling described first masking layer 106, second masking layer 108 and the 3rd masking layer 111, just make the upper surface of described GeSi layer 113, GaN layer 107 and monocrystalline silicon layer 110 to maintain an equal level at grade.
As mentioned above, three layers of crystallographic orientation semiconductor-on-insulator structure of the present invention and preparation method thereof, there is following beneficial effect: the invention provides a kind of three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof, high frequency (surpassing) high voltage gan device is prepared for follow-up in GaN layer 107 surface, (110) crystal face germanium silicon surface prepares high frequency (surpassing) low pressure SiGe device for follow-up, be beneficial to fully increase hole carrier mobility, (100) crystal face monocrystalline silicon layer 110 surface is used for the conventional silicon-based devices of follow-up preparation, thus make full use of SOI technology, germanium silicon technology, GaN technology, conventional silicon-based technologies is by high frequency, (surpassing) high pressure, (surpassing) low pressure, high reliability and conventional silicon-based nano level device integration are designed into the structure providing a kind of advanced person in a planar-type semiconductor integrated circuit, technology.Simply, Be very effective, is with a wide range of applications in field of semiconductor manufacture for structure of the present invention and method.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (14)
1. a manufacture method for three layers of crystallographic orientation semiconductor-on-insulator structure, is characterized in that, comprises step:
A) provide a substrate, described substrate comprises the silicon top layer in the silicon bottom in the first crystal orientation stacked gradually, the first insulating barrier, the silicon intermediate layer in the second crystal orientation, the second insulating barrier and the 3rd crystal orientation;
B) above described silicon top layer, form the first masking layer formed until the first groove of described silicon top layer in the position for preparation the first device area, in described first groove, form GaN layer;
C) formed until the second groove of silicon bottom in the position for preparation the second device area, in described second groove, form the first sidewall structure, in described second groove, then form the monocrystalline silicon layer with the first crystal orientation;
D) formed until the 3rd groove in silicon intermediate layer in the position for preparation the 3rd device area, the second sidewall structure is formed in described 3rd groove, then in described 3rd groove, GeSi material is formed, and adopt oxidation concentration technology Ge is concentrated and diffuses into silicon intermediate layer downwards, make all to form GeSi layer in silicon interlayer region and the 3rd groove.
2. the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, it is characterized in that: in described manufacture method, step execution sequence a), b), c), d) is: a), b), c), d) or a), b), d), c) or a), c), b), d) or a), c), d), b) or a), d), b), c) or a), d), c), b).
3. the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, is characterized in that: the growth thickness of described GaN layer, monocrystalline silicon layer and GeSi layer is at least make the upper surface of described GaN layer, monocrystalline silicon layer and GeSi layer maintain an equal level at grade.
4. the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, is characterized in that:
Step b) in, make the upper surface of the described GaN layer of formation exceed described first masking layer, draw together afterwards and adopt chemical mechanical milling tech to remove unnecessary GaN material, the upper surface of GaN layer and described first masking layer upper surface are maintained an equal level;
Step c) in, described second groove is formed by forming second masking layer with etching window, and make the upper surface of the described monocrystalline silicon layer of formation exceed described second masking layer, adopt chemical mechanical milling tech to remove unnecessary single crystal silicon material afterwards, the upper surface of monocrystalline silicon layer and described second masking layer upper surface are maintained an equal level;
Steps d) in, described second groove is formed by forming the 3rd masking layer with etching window, and make the upper surface of the described GeSi layer of formation exceed described 3rd masking layer, adopt chemical mechanical milling tech to remove unnecessary GeSi material afterwards, the upper surface of GeSi layer and described 3rd masking layer upper surface are maintained an equal level.
5. the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 4, is characterized in that: the material of described first masking layer, the second masking layer and the 3rd masking layer comprises Si
3n
4and SiO
2in one or its combination, the material of described first sidewall structure and the second sidewall structure comprises Si
3n
4and SiO
2in one or its combination.
6. the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, it is characterized in that: also comprise step: what produce in employing chemical mechanical milling tech removal technical process is positioned at GaN layer, and/or monocrystalline silicon layer, and/or the unnecessary masking layer above GeSi layer, and make the step that described GaN layer, monocrystalline silicon layer and GeSi layer surface maintains an equal level; Or what first produce in employing wet etching removal technical process is positioned at GaN layer, and/or monocrystalline silicon layer, and/or the unnecessary masking layer above GeSi layer, then adopt chemical mechanical milling tech that described GaN layer, monocrystalline silicon layer and GeSi layer surface is maintained an equal level.
7. the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, is characterized in that: steps d) in adopt be globalize wafer surface dry-oxygen oxidation technique with oxidation concentration technology.
8. the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, is characterized in that: described 3rd crystal orientation is (111) crystal orientation.
9. the manufacture method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, is characterized in that: described first crystal orientation is (100), and the second crystal orientation is (110); Or described first crystal orientation is (110), the second crystal orientation is (100).
10. three layers of crystallographic orientation semiconductor-on-insulator structure, is characterized in that, comprising:
Substrate, described substrate comprises the silicon top layer in the silicon bottom in the first crystal orientation stacked gradually, the first insulating barrier, the silicon intermediate layer in the second crystal orientation, the second insulating barrier and the 3rd crystal orientation;
First masking layer, is formed at described silicon topsheet surface;
First groove, is formed in described first masking layer, and exposes and have silicon topsheet surface;
GaN layer, is formed in described first groove;
Second groove, extends in described substrate from described structure upper surface, and contacts silicon bottom surface bottom it;
First sidewall structure, is formed at described second recess sidewall;
The monocrystalline silicon layer in the first crystal orientation, is formed in described second groove;
3rd groove, extends in described substrate from described structure upper surface, and contacts silicon intermediate layer bottom it;
Second sidewall structure, is formed at described 3rd recess sidewall;
GeSi layer, the silicon interlayer region being formed in described 3rd groove and connecting with described 3rd groove.
11. three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 10, is characterized in that: the upper surface of described GaN layer, monocrystalline silicon layer and GeSi layer maintains an equal level at grade.
12. three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 10, is characterized in that: described 3rd crystal orientation is (111) crystal orientation.
13. three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 10, is characterized in that: described first crystal orientation is (100), and the second crystal orientation is (110); Or described first crystal orientation is (110), the second crystal orientation is (100).
14. three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 10, is characterized in that: the material of described first masking layer comprises Si
3n
4and SiO
2in one or its combination, the material of described first sidewall structure and the second sidewall structure comprises Si
3n
4and SiO
2in one or its combination.
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