CN112736025A - SOI HYB edge silicon epitaxial manufacturing method and terminal equipment - Google Patents
SOI HYB edge silicon epitaxial manufacturing method and terminal equipment Download PDFInfo
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- CN112736025A CN112736025A CN202011562993.3A CN202011562993A CN112736025A CN 112736025 A CN112736025 A CN 112736025A CN 202011562993 A CN202011562993 A CN 202011562993A CN 112736025 A CN112736025 A CN 112736025A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 93
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 93
- 239000010703 silicon Substances 0.000 title claims abstract description 93
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000000407 epitaxy Methods 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000000227 grinding Methods 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 i.e. Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Abstract
The invention discloses a manufacturing method of SOI HYB edge silicon epitaxy, which comprises the following steps: providing an SOI substrate; setting a hard mask layer to etch and remove part of a BOX layer, an SOI SI layer and an OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate; performing a grinding process to enable the upper surface of the silicon epitaxy to be flush with the upper surface of the hard mask layer; etching the silicon epitaxy to enable the upper surface of the silicon epitaxy to be located between the upper surface and the lower surface of the SOI SI layer; removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy layer; and performing STI trench etching and subsequent processes. The invention can provide a flat plane for the subsequent STI trench etching process, thoroughly eliminate the height difference, improve the STI shallow trench etching load effect, enlarge the BARC etching window and reduce the risk of etching residual defects, thereby improving the yield of products.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing SOI HYB edge silicon epitaxy. The invention also relates to a terminal device for carrying out the SOI HYB edge silicon epitaxial manufacturing method.
Background
SOI is known as Silicon-On-Insulator, i.e., Silicon On an insulating substrate, and this technique introduces a buried oxide layer between the top Silicon and the back substrate. The principle of SOI is that an insulator substance is added between Silicon transistors, so that the parasitic capacitance between the Silicon transistors is twice as small as that of the original one. The material is formed by a semiconductor film on an insulator, and the SOI material has the advantages which cannot be compared with the bulk silicon: the dielectric isolation of components in the integrated circuit can be realized, and the parasitic latch-up effect in a bulk silicon CMOS circuit is thoroughly eliminated; the integrated circuit made of the material also has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, particular application to low-voltage and low-power consumption circuits and the like, so that the SOI can possibly become the mainstream technology of deep submicron low-voltage and low-power consumption integrated circuits. In addition, SOI materials have also been used to fabricate MEMS optical switches, such as with bulk micromachining techniques.
As shown in fig. 1, the left side is an SOI region, and the right side is a HYB non-SOI region, when an epitaxial silicon layer grows, the silicon growth speed at the edge boundary is higher due to the presence of the left side SOI, and a protrusion is formed at the boundary. Subsequent processes will etch away STI trenches to separate the SOI/HYB bulk regions. The influence of the silicon bump is conducted during the STI etch to the final trench loading effect, as shown in fig. 2. In addition, double-boundary bulges exist in a small-size HYB area, so that the relative thickness of the middle BARC is thicker, the pattern is broken due to insufficient coverage of an etching window, and the product yield is insufficient.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The technical problem to be solved by the invention is to provide an SOI HYB edge silicon epitaxy manufacturing method and terminal equipment for implementing the SOI HYB edge silicon epitaxy manufacturing method, wherein the STI etching load caused by SOI HYB edge silicon epitaxy protrusion can be avoided, a BARC etching window is expanded, and the etching residual defect is reduced.
In order to solve the technical problem, the method for manufacturing the SOI HYB edge silicon epitaxy provided by the invention comprises the following steps:
s1, providing an SOI substrate;
s2, setting a hard mask layer to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate;
s3, performing a grinding process to enable the upper surface of the silicon epitaxy to be flush with the upper surface of the hard mask layer;
s4, etching the silicon epitaxy to make the upper surface of the silicon epitaxy between the upper surface and the lower surface of the SOI SI layer;
s5, removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy layer;
s6, performing STI trench etching and subsequent processes.
Optionally, the method for manufacturing an SOI HYB edge silicon epitaxy is further improved, and when step S3 is performed, the SIN layer is used as a hard mask layer.
Optionally, the method for manufacturing the SOI HYB edge silicon epitaxy is further improved, and when step S3 is performed, the silicon epitaxy is made flush with the SIN layer by CMP process
Optionally, the method for manufacturing the SOI HYB edge silicon epitaxy is further improved, and when the step S4 is implemented, the silicon epitaxy upper surface is located between the upper surface and the lower surface of the SOI SI layer through the poly/SIN high selectivity dry etching.
Optionally, the method for manufacturing the SOI HYB edge silicon epitaxy is further improved, and when the step S4 is implemented, the upper surface of the silicon epitaxy is located between the upper surface and the lower surface of the SOI SI layer by poly/SIN high selectivity wet etching.
Alternatively, the SOI HYB edge silicon epitaxial fabrication process is further improved, which can be used for FDSOI wafers.
Optionally, the SOI HYB edge silicon epitaxial manufacturing method is further improved, and can be used for processes with the grain size of 130nm or more, 90nm, 65nm, 55nm, 45nm, 40nm, 32nm, 28nm, 22nm, 20nm and 16nm or less.
Optionally, the SOI HYB edge silicon epitaxial manufacturing method is further improved, and can be used for manufacturing processes of semiconductor logic devices, semiconductor memory devices and semiconductor radio frequency devices.
The present invention provides a terminal device for carrying out the SOI HYB edge silicon epitaxial manufacturing method of any one of the above.
In order to solve the problem that the influence of the silicon epitaxial bulge is conducted to the final formed groove load effect in the STI etching process, the invention adds a CMP grinding process after the silicon epitaxial growth, takes a silicon nitride mask layer as a CMP grinding barrier layer and a grinding end point detection layer, and the grinding end point is stopped at a silicon nitride layer. And then adjusting the height of the epitaxially grown silicon to be close to the height of the SOI silicon layer by using poly/SIN high-selectivity dry etching or wet etching. Finally, after the silicon nitride mask layer is pulled out, the junction of the SOI edge and the HYB edge becomes more flat, a flat plane is provided for the subsequent STI trench etching process, the height difference is thoroughly eliminated, the STI shallow trench etching load effect can be improved, the BARC etching window is enlarged, the risk of etching residual defects is reduced, and the yield of products is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a schematic flow diagram of the present invention.
FIG. 2 is a first schematic diagram of the present invention.
FIG. 3 is a second schematic diagram of the present invention.
FIG. 4 is a third schematic diagram of the present invention.
FIG. 5 is a fourth schematic diagram of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
Like reference numerals refer to like elements throughout the drawings. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention.
A first embodiment;
as shown in fig. 1, the present invention provides a method for manufacturing SOI HYB edge silicon epitaxy, comprising the steps of:
s1, providing an SOI substrate;
s2, setting a hard mask layer to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate;
s3, performing a grinding process to enable the upper surface of the silicon epitaxy to be flush with the upper surface of the hard mask layer;
s4, etching the silicon epitaxy to make the upper surface of the silicon epitaxy between the upper surface and the lower surface of the SOI SI layer;
s5, removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy layer;
s6, performing STI trench etching and subsequent processes.
A second embodiment;
with continued reference to fig. 1, the present invention provides a method for SOI HYB edge silicon epitaxial fabrication comprising the steps of:
s1, providing an SOI substrate;
s2, setting a hard mask layer to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate;
s3, performing a CMP grinding process by taking the SIN layer as a hard mask layer to enable the upper surface of the silicon epitaxy to be flush with the upper surface of the SIN layer;
and S4, etching the silicon epitaxy, and enabling the upper surface of the silicon epitaxy to be positioned between the upper surface and the lower surface of the SOI SI layer through poly/SIN high-selectivity dry etching.
S5, removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy layer;
s6, performing STI trench etching and subsequent processes.
A third embodiment;
with continued reference to fig. 1, the present invention provides a method for SOI HYB edge silicon epitaxial fabrication comprising the steps of:
s1, providing an SOI substrate;
s2, as shown in FIG. 2, a hard mask layer is arranged to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and a silicon epitaxy is formed on the exposed silicon substrate;
s3, as shown in fig. 3, performing a CMP polishing process using the SIN layer as a hard mask layer to make the upper surface of the silicon epitaxy flush with the upper surface of the SIN layer;
s4, as shown in FIG. 4, etching the silicon epitaxy, and making the upper surface of the silicon epitaxy between the upper surface and the lower surface of the SOI SI layer by poly/SIN dry etching;
s5, as shown in FIG. 5, removing the hard mask layer, the OX layer and the SIN layer to make the upper surface of the SOI SI layer flush with the upper surface of the silicon epitaxy layer;
s6, performing STI trench etching and subsequent processes.
The SOI HYB edge silicon epitaxial manufacturing method according to any one of the first to fourth embodiments described above can be used for FDSOI wafers.
A fourth embodiment;
the present invention provides a terminal device, such as a semiconductor manufacturing machine, for performing the SOI HYB edge silicon epitaxial manufacturing method according to any one of the first to third embodiments.
The method for manufacturing SOI HYB edge silicon epitaxy according to any one of the first to fourth embodiments described above, which can be used in processes of 130nm or more, 90nm, 65nm, 55nm, 45nm, 40nm, 32nm, 28nm, 22nm, 20nm, and 16nm or less.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (9)
1. An SOI HYB edge silicon epitaxial manufacturing method is characterized by comprising the following steps:
s1, providing an SOI substrate;
s2, setting a hard mask layer to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate;
s3, performing a grinding process to enable the upper surface of the silicon epitaxy to be flush with the upper surface of the hard mask layer;
s4, etching the silicon epitaxy to make the upper surface of the silicon epitaxy between the upper surface and the lower surface of the SOI SI layer;
s5, removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy layer;
s6, performing STI trench etching and subsequent processes.
2. The SOI HYB edge silicon epitaxial fabrication process of claim 1 wherein: in step S3, the SIN layer is used as a hard mask layer.
3. An SOI HYB edge silicon epitaxial fabrication process as defined in claim 2 wherein: step S3 is performed by making the silicon epitaxy level with the SIN layer by a CMP process.
4. The SOI HYB edge silicon epitaxial fabrication process of claim 1 wherein: step S4 is performed by dry etching with a high selectivity ratio of poly/SIN so that the upper surface of the silicon epitaxy is located between the upper and lower surfaces of the soi isi layer.
5. The SOI HYB edge silicon epitaxial fabrication process of claim 1 wherein: step S4 is performed by wet etching with a high selectivity poly/SIN so that the upper surface of the silicon epitaxy is between the upper and lower surfaces of the soi isi layer.
6. The SOI HYB edge silicon epitaxial fabrication process according to any one of claims 1 to 5, characterized in that: which can be used for FDSOI wafers.
7. The SOI HYB edge silicon epitaxial fabrication process according to any one of claims 1 to 5, characterized in that: it can be used for the processes of 130nm or more, 90nm, 65nm, 55nm, 45nm, 40nm, 32nm, 28nm, 22nm, 20nm and 16nm or less.
8. The SOI HYB edge silicon epitaxial fabrication process according to any one of claims 1 to 5, characterized in that: it can be used in the manufacturing processes of semiconductor logic devices, semiconductor memory devices, and semiconductor radio frequency devices.
9. A terminal device characterized by: for carrying out the SOI HYB edge silicon epitaxial fabrication method of any one of claims 1 to 5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011562993.3A CN112736025B (en) | 2020-12-25 | SOI HYB edge silicon epitaxial manufacturing method and terminal equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011562993.3A CN112736025B (en) | 2020-12-25 | SOI HYB edge silicon epitaxial manufacturing method and terminal equipment |
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| CN112736025A true CN112736025A (en) | 2021-04-30 |
| CN112736025B CN112736025B (en) | 2024-04-30 |
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1041381A (en) * | 1996-07-22 | 1998-02-13 | Sharp Corp | Manufacture of semiconductor device |
| JP2000306994A (en) * | 1999-04-26 | 2000-11-02 | Oki Electric Ind Co Ltd | Semiconductor device of soi structure and fabrication thereof |
| KR20010003210A (en) * | 1999-06-22 | 2001-01-15 | 김영환 | Method of manufacturing SOI wafer |
| US20050202600A1 (en) * | 2004-03-12 | 2005-09-15 | Tenko Yamashita | Silicon-on insulator (soi) substrate having dual surface crystallographic orientations and method of forming same |
| CN102437129A (en) * | 2011-08-29 | 2012-05-02 | 上海华力微电子有限公司 | Localized SOI (Silicon-On-Insulator) and GOI (Germanium On Insulator) device structure and process integrating method thereof |
| CN103000519A (en) * | 2011-09-09 | 2013-03-27 | 上海华虹Nec电子有限公司 | Method for removing silicon ridge produced in epitaxial deposition of super-junction high-pressure device |
| CN103794542A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor substrate |
| CN105448845A (en) * | 2015-12-17 | 2016-03-30 | 中航（重庆）微电子有限公司 | Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof |
| US10062712B1 (en) * | 2017-07-26 | 2018-08-28 | Newport Fab, Llc | Method to fabricate both FD-SOI and PD-SOI devices within a single integrated circuit |
| DE102018125373A1 (en) * | 2017-11-22 | 2019-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming an SOI substrate |
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1041381A (en) * | 1996-07-22 | 1998-02-13 | Sharp Corp | Manufacture of semiconductor device |
| JP2000306994A (en) * | 1999-04-26 | 2000-11-02 | Oki Electric Ind Co Ltd | Semiconductor device of soi structure and fabrication thereof |
| KR20010003210A (en) * | 1999-06-22 | 2001-01-15 | 김영환 | Method of manufacturing SOI wafer |
| US20050202600A1 (en) * | 2004-03-12 | 2005-09-15 | Tenko Yamashita | Silicon-on insulator (soi) substrate having dual surface crystallographic orientations and method of forming same |
| CN102437129A (en) * | 2011-08-29 | 2012-05-02 | 上海华力微电子有限公司 | Localized SOI (Silicon-On-Insulator) and GOI (Germanium On Insulator) device structure and process integrating method thereof |
| CN103000519A (en) * | 2011-09-09 | 2013-03-27 | 上海华虹Nec电子有限公司 | Method for removing silicon ridge produced in epitaxial deposition of super-junction high-pressure device |
| CN103794542A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor substrate |
| CN105448845A (en) * | 2015-12-17 | 2016-03-30 | 中航（重庆）微电子有限公司 | Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof |
| US10062712B1 (en) * | 2017-07-26 | 2018-08-28 | Newport Fab, Llc | Method to fabricate both FD-SOI and PD-SOI devices within a single integrated circuit |
| DE102018125373A1 (en) * | 2017-11-22 | 2019-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming an SOI substrate |
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