CN112736025B - SOI HYB edge silicon epitaxial manufacturing method and terminal equipment - Google Patents
SOI HYB edge silicon epitaxial manufacturing method and terminal equipment Download PDFInfo
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- CN112736025B CN112736025B CN202011562993.3A CN202011562993A CN112736025B CN 112736025 B CN112736025 B CN 112736025B CN 202011562993 A CN202011562993 A CN 202011562993A CN 112736025 B CN112736025 B CN 112736025B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 95
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 95
- 239000010703 silicon Substances 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 51
- 238000000407 epitaxy Methods 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000227 grinding Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000000694 effects Effects 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 i.e. Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a SOI HYB edge silicon epitaxial manufacturing method, which comprises the following steps: providing an SOI substrate; setting a hard mask layer, etching to remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate; performing a grinding process to enable the upper surface of the silicon epitaxy to be flush with the upper surface of the hard mask layer; etching the silicon epitaxy so that the upper surface of the silicon epitaxy is positioned between the upper surface and the lower surface of the SOI SI layer; removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy; and executing STI TRENCH an etching process and subsequent processes. The invention can provide a flat plane for the subsequent STI TRENCH etching process, thoroughly eliminate the height difference, improve the STI shallow trench etching load effect, enlarge the BARC etching window and reduce the risk of etching residual defects, thereby improving the yield of products.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to an SOI HYB edge silicon epitaxial manufacturing method. The invention also relates to a terminal device for performing the SOI HYB edge silicon epitaxial manufacturing method.
Background
SOI is known as Silicon-On-Insulator, i.e., silicon On an insulating substrate, by introducing a buried oxide layer between the top Silicon layer and the bottom of the backing. SOI is the meaning of a Silicon transistor structure over an insulator, and the principle is that an insulator substance is added between Silicon transistors, so that parasitic capacitance between the Silicon transistor and the insulator substance is doubled less than that between the Silicon transistor and the insulator substance. Material by forming a semiconductor film on an insulator, SOI materials have advantages that are incomparable to bulk silicon: dielectric isolation of components in the integrated circuit can be realized, and parasitic latch-up effect in the bulk silicon CMOS circuit is thoroughly eliminated; the integrated circuit made of the material has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, and the like, and is particularly suitable for low-voltage and low-power consumption circuits, so that the SOI is likely to become a mainstream technology of deep submicron low-voltage and low-power consumption integrated circuits. In addition, SOI materials are also used to fabricate MEMS optical switches, such as with bulk micromachining techniques.
As shown in fig. 1, the left side is an SOI region and the right side is an HYB non-SOI region, and when the epitaxial silicon layer grows, the silicon at the boundary of the edge is generated at a higher speed due to the existence of the SOI at the left side, and a bump is formed at the boundary. Subsequent processing will etch there to form STI trench isolation SOI/HYB bulk regions. The influence of the silicon bump is conducted to the final trench loading effect during the STI etch process, as shown in fig. 2. Moreover, the existence of double boundary bulges in a small-size HYB region causes thicker intermediate BARC, insufficient coverage of an etching window causes pattern disconnection, and insufficient product yield is caused.
Disclosure of Invention
In the summary section, a series of simplified form concepts are introduced that are all prior art simplifications in the section, which are described in further detail in the detailed description section. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The technical problem to be solved by the invention is to provide the SOI HYB edge silicon epitaxial manufacturing method capable of avoiding STI etching load caused by the SOI HYB edge silicon epitaxial bulge, enlarging a BARC etching window and reducing etching residual defects, and terminal equipment for executing the SOI HYB edge silicon epitaxial manufacturing method.
In order to solve the technical problems, the method for manufacturing the SOI HYB edge silicon epitaxy comprises the following steps:
S1, providing an SOI substrate;
S2, setting a hard mask layer to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate;
S3, performing a grinding process to enable the upper surface of the silicon epitaxy to be flush with the upper surface of the hard mask layer;
s4, etching is carried out on the silicon epitaxy, so that the upper surface of the silicon epitaxy is positioned between the upper surface and the lower surface of the SOI SI layer;
s5, removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy;
S6, executing STI TRENCH etching process and subsequent processes.
Optionally, the method for manufacturing the SOI HYB edge silicon epitaxy is further improved, and when step S3 is implemented, the SIN layer is used as a hard mask layer.
Optionally, the method for manufacturing the SOI HYB edge silicon epitaxy is further improved, and when step S3 is implemented, the silicon epitaxy is flush with the SIN layer through a CMP process
Optionally, the method for manufacturing the SOI HYB edge silicon epitaxy is further improved, and in the step S4, the upper surface of the silicon epitaxy is located between the upper surface and the lower surface of the SOI SI layer by high selectivity dry etching of poly/SIN.
Optionally, the method for manufacturing the SOI HYB edge silicon epitaxy is further improved, and in the step S4, the upper surface of the silicon epitaxy is located between the upper surface and the lower surface of the SOI SI layer by high-selectivity wet etching of poly/SIN.
Alternatively, the SOI HYB edge silicon epitaxial fabrication method can be further improved, which can be used for FDSOI wafer.
Alternatively, the SOI HYB edge silicon epitaxial manufacturing method can be further improved and can be used for processes with the wavelength of 130nm, 90nm, 65nm, 55nm, 45nm, 40nm, 32nm, 28nm, 22nm, 20nm and 16nm or less.
Alternatively, the SOI HYB edge silicon epitaxial fabrication method can be further improved, which can be used in the fabrication process of semiconductor logic devices, semiconductor memory devices, and semiconductor radio frequency devices.
The invention provides a terminal device for executing the SOI HYB edge silicon epitaxial manufacturing method.
In order to solve the problem that the influence of the silicon epitaxial bulge on the final formation of a groove is conducted in the STI etching process, the invention adds a CMP grinding process after the silicon epitaxial growth, uses a silicon nitride mask layer as a CMP grinding blocking layer and a grinding end point detection layer, and the grinding end point is stopped at the silicon nitride layer. And then adjusting the height of the epitaxially grown silicon to be close to the height of the SOI silicon layer by dry etching or wet etching with high selectivity of poly/SIN. Finally, after the silicon nitride mask layer is removed, the boundary between the SOI and the HYB edge becomes smoother, a smooth plane is provided for the subsequent STI TRENCH etching process, the height difference is thoroughly eliminated, the STI shallow trench etching load effect can be improved, the BARC etching window is enlarged, the etching residual defect risk is reduced, and the yield of products is further improved.
Drawings
The accompanying drawings are intended to illustrate the general features of methods, structures and/or materials used in accordance with certain exemplary embodiments of the invention, and supplement the description in this specification. The drawings of the present invention, however, are schematic illustrations that are not to scale and, thus, may not be able to accurately reflect the precise structural or performance characteristics of any given embodiment, the present invention should not be construed as limiting or restricting the scope of the numerical values or attributes encompassed by the exemplary embodiments according to the present invention. The invention is described in further detail below with reference to the attached drawings and detailed description:
Fig. 1 is a schematic flow chart of the present invention.
Fig. 2 is a schematic diagram of an intermediate structure of the present invention.
FIG. 3 is a schematic diagram of an intermediate structure of the present invention.
Fig. 4 is a schematic diagram of an intermediate structure of the present invention.
Fig. 5 is a schematic diagram of an intermediate structure of the present invention.
Detailed Description
Other advantages and technical effects of the present invention will become more fully apparent to those skilled in the art from the following disclosure, which is a detailed description of the present invention given by way of specific examples. The invention may be practiced or carried out in different embodiments, and details in this description may be applied from different points of view, without departing from the general inventive concept. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It should be appreciated that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solution of these exemplary embodiments to those skilled in the art.
Like reference numerals refer to like elements throughout the several views. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Furthermore, it will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region, layer or section without departing from the teachings of the example embodiments of the present invention.
A first embodiment;
as shown in fig. 1, the invention provides a method for manufacturing SOI HYB edge silicon epitaxy, comprising the following steps:
S1, providing an SOI substrate;
S2, setting a hard mask layer to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate;
S3, performing a grinding process to enable the upper surface of the silicon epitaxy to be flush with the upper surface of the hard mask layer;
s4, etching is carried out on the silicon epitaxy, so that the upper surface of the silicon epitaxy is positioned between the upper surface and the lower surface of the SOI SI layer;
s5, removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy;
S6, executing STI TRENCH etching process and subsequent processes.
A second embodiment;
With continued reference to fig. 1, the present invention provides a method for manufacturing SOI HYB-edge silicon epitaxy, comprising the steps of:
S1, providing an SOI substrate;
S2, setting a hard mask layer to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate;
s3, performing a CMP (chemical mechanical polishing) process by taking the SIN layer as a hard mask layer, so that the upper surface of the silicon epitaxy is level with the upper surface of the SIN layer;
and S4, etching is carried out on the silicon epitaxy, and the upper surface of the silicon epitaxy is positioned between the upper surface and the lower surface of the SOI SI layer through high selectivity dry etching of poly/SIN.
S5, removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy;
S6, executing STI TRENCH etching process and subsequent processes.
A third embodiment;
With continued reference to fig. 1, the present invention provides a method for manufacturing SOI HYB-edge silicon epitaxy, comprising the steps of:
S1, providing an SOI substrate;
s2, as shown in FIG. 2, a hard mask layer is arranged to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and a silicon epitaxy is formed on the exposed silicon substrate;
S3, as shown in FIG. 3, performing a CMP (chemical mechanical polishing) process by taking the SIN layer as a hard mask layer, so that the upper surface of the silicon epitaxy is level with the upper surface of the SIN layer;
S4, as shown in FIG. 4, etching is carried out on the silicon epitaxy, and the upper surface of the silicon epitaxy is positioned between the upper surface and the lower surface of the SOI SI layer through high selectivity dry etching of poly/SIN;
S5, as shown in FIG. 5, removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy;
S6, executing STI TRENCH etching process and subsequent processes.
The method for manufacturing SOI HYB-edge silicon epitaxy as in any one of the first to fourth embodiments described above can be used for FDSOI wafer.
A fourth embodiment;
The present invention provides a terminal device, such as a semiconductor production machine, for performing the SOI HYB-edge silicon epitaxial manufacturing method described in any one of the above first to third embodiments.
The method for producing SOI HYB edge silicon epitaxy according to any one of the first to fourth embodiments, which can be used for 130nm, 90nm, 65nm, 55nm, 45nm, 40nm, 32nm, 28nm, 22nm, 20nm and 16nm or less processes.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail by way of specific embodiments and examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (9)
1. The SOI HYB edge silicon epitaxial manufacturing method is characterized by comprising the following steps of:
S1, providing an SOI substrate;
S2, setting a hard mask layer to etch and remove part of the BOX layer, the SOI SI layer and the OX layer of the SOI substrate to expose the silicon substrate, and forming a silicon epitaxy on the exposed silicon substrate;
S3, performing a grinding process to enable the upper surface of the silicon epitaxy to be flush with the upper surface of the hard mask layer;
s4, etching is carried out on the silicon epitaxy, so that the upper surface of the silicon epitaxy is positioned between the upper surface and the lower surface of the SOI SI layer;
s5, removing the hard mask layer, the OX layer and the SIN layer to enable the upper surface of the SOI SI layer to be flush with the upper surface of the silicon epitaxy;
S6, executing STI TRENCH etching process and subsequent processes.
2. The SOI HYB edge silicon epitaxial fabrication method of claim 1, wherein: in the implementation of step S3, the SIN layer is used as a hard mask layer.
3. The SOI HYB edge silicon epitaxial fabrication method of claim 2, wherein: in step S3, the silicon epitaxy is aligned with the SIN layer by a CMP process.
4. The SOI HYB edge silicon epitaxial fabrication method of claim 1, wherein: in step S4, the upper surface of the silicon epitaxy is located between the upper surface and the lower surface of the SOISI layer by a high selectivity dry etch of poly/SIN.
5. The SOI HYB edge silicon epitaxial fabrication method of claim 1, wherein: in step S4, the upper surface of the silicon epitaxy is located between the upper surface and the lower surface of the SOISI layer by a high selectivity wet etch of poly/SIN.
6. A method of SOI HYB edge silicon epitaxial fabrication as defined in any one of claims 1-5 wherein: it can be used for FDSOI wafer.
7. A method of SOI HYB edge silicon epitaxial fabrication as defined in any one of claims 1-5 wherein: it can be used for processes greater than or equal to 130nm, 90nm, 65nm, 55nm, 45nm, 40nm, 32nm, 28nm, 22nm, 20nm and less than or equal to 16 nm.
8. A method of SOI HYB edge silicon epitaxial fabrication as defined in any one of claims 1-5 wherein: it can be used in the manufacturing process of semiconductor logic devices, semiconductor memory devices and semiconductor radio frequency devices.
9. A terminal device, characterized by: for performing the SOI HYB edge silicon epitaxial fabrication method of any one of claims 1-5.
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| DE102018125373A1 (en) * | 2017-11-22 | 2019-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming an SOI substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6949420B1 (en) * | 2004-03-12 | 2005-09-27 | Sony Corporation | Silicon-on-insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same |
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2020
- 2020-12-25 CN CN202011562993.3A patent/CN112736025B/en active Active
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| JPH1041381A (en) * | 1996-07-22 | 1998-02-13 | Sharp Corp | Manufacture of semiconductor device |
| JP2000306994A (en) * | 1999-04-26 | 2000-11-02 | Oki Electric Ind Co Ltd | Semiconductor device of soi structure and fabrication thereof |
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