WO2007096581A2

WO2007096581A2 - Radio frequency integrated circuit manufacturing

Info

Publication number: WO2007096581A2
Application number: PCT/GB2007/000408
Authority: WO
Inventors: Neil Lloyd; Alec Reader
Original assignee: Polymer Vision Limited
Priority date: 2006-02-23
Filing date: 2007-02-06
Publication date: 2007-08-30
Also published as: GB2439357C; GB2439357B; GB2439357A; GB0603682D0; WO2007096581A3

Abstract

A method for manufacturing a radio frequency integrated circuit. The integrated circuit is fabricated in windows of a semiconductor material between regions of an insulating layer grown on a semiconductor substrate. An intermediate integrated circuit comprising a plurality of unconnected semiconductor components is also provided as a tool for manufacturing prototype radio frequency integrated circuits.

Description

Radio Frequency Integrated Circuit Manufacturing

BACKGROUND TO THE INVENTION

The invention relates to a method of manufacturing radio frequency integrated circuits (RPICs), and to RFICs manufactured by the method, more especially but not exclusively the invention relates to CMOS RFICs.

The development of an integrated CMOS circuit from the original circuit design to a working product requires a number of iterative manufacture steps during which prototype circuits are manufactured and tested. Failure of the prototype, followed by identification of the failure mode leads to an improved circuit design and the requirement for the manufacture of a further prototype.

The operation of an IC is heavily dependent on the precision with which each manufacturing step is completed. Thus, high precision equipment and lengthy manufacture times are required to manufacture reliable ICs. The cost of the equipment combined with the lengthy manufacturing time makes IC manufacture highly expensive.

In order to improve switching speeds and provide more functionality per unit area there has been a continued drive for smaller component sizes in digital IC manufacture. This fact, combined with the requirement for affordable ICs, has driven an increase in the 'packing density', which is the number of devices per unit area that can be fabricated. However, increasing the packing density also increases the likelihood of interference between components. Thus, the increase in packing density has required the use of increasingly more sophisticated technologies for isolating neighbouring components on an IC. Figures IA- 1C disclose the isolation technologies presently used during the manufacture of digital ICs.

Figure IA shows a cross-section through a silicon substrate 2 in which a first component 4, a second component 6 and a third component 8 are separated by regions of silicon dioxide 10 grown by the local oxidation of silicon (LOCOS) method. The

LOCOS procedure begins by masking areas of the semiconductor substrate 3 in which components will be fabricated to prevent oxidation of the silicon. The silicon substrate 2 is then oxidised. Following oxidation, the masked regions are etched to expose the silicon substrate 2. Semiconductor components 2, 4, 6 may then be manufactured in the regions of exposed silicon using standard techniques and are isolated by the regions of silicon dioxide 10.

Silicon dioxide has a greater volume than silicon, so that the regions of silicon dioxide 10 swell to produce a non-planar surface. The oxidation also occurs laterally, which produces "Bird's Beak" encroachments (areas of tapering oxide at the lateral edges of the oxidised region) that are characteristic of the LOCOS method. The lateral spread of the oxide in the Bird's Beak encroachments significantly reduces the attainable packing density. This limit in the achievable packing density of LOCOS has in recent years lead the industry to move over to an alternative method of shallow trench isolation (STI).

Figure IB shows a cross-section through a semiconductor substrate 3 in which a first component 4, a second component 6 and a third component 8 are separated by a region of an insulating material 12 manufactured by the chemical mechanical polishing - shallow trench isolation (CMP-STI) method. The trenches are initially filled with insulating material 12 through deposition of a conformant layer of insulating material 12 (not shown). Chemical vapour deposition or a similar technique that does not require oxidation of the semiconductor substrate 3 is used. This deposition results in insulating material extending above the plane of the surface of the semiconductor substrate 3. The excess insulating material is then removed by polishing to make it flush to the surface of the semiconductor substrate 3 as shown in idealised fashion in the figure.

With the CMP-STI method, Bird's Beak encroachments do not form. Moreover, etched features exhibit a well defined and controllable morphology so that the trenches may be foπned with a smaller feature size than is attainable with LOCOS. This merit, combined with the lack of Bird's Beaks, leads to an increase in the attainable packing density.

However, in practice, with the CMP-STI method, it is difficult to perform the polishing so that the insulating material 12 terminates in the plane of the surface of the semiconductor substrate 3.

Figure 1C shows a comparable cross-section to Figure IB illustrating this problem schematically to show how the idealised result of planar polishing shown in Figure IB is not always achieved in practice. As illustrated, the polishing can result in either over-fill 14 or under-fill 16 of the trenches. The lack of a planar surface may disrupt later optical or other lithography processes. Over-fill 14 can also reduce the achievable packing density due to the spreading of the over-fill 14 on the surface of the substrate 2.

CMP-STI is used primarily in the manufacture of digital electronics since it allows the highest packing densities and leaves a planar surface. However, CMP-STI requires accurate, lengthy and expensive polishing procedures in addition to the further process steps required by STI.

Whether by LOCOS or STI, standard approaches to CMOS IC manufacturing have thus evolved into highly complex processes involving large numbers of processing steps to manufacture an IC, largely driven by the requirements of high volume production of digital ICs, most notably computer processors and memories. -A-

Because of the way CMOS IC manufacturing processes have developed, prototyping in CMOS has become very expensive and time consuming. If a prototype design is given to a modern CMOS fabrication plant (which is often referred to as "taped-out"), it will typically take 4-8 months to fabricate. The long fabrication delay is an acute problem for prototyping, since the usual aim of a prototype is to test a design, and then to modify it following testing by making a further prototype and so forth. If the manufacturing time per prototype is too slow, an iterative design process becomes impossible in practice. In particular analogue designers of RFICs finds this situation problematic.

The aim of the invention is therefore to provide a modified IC fabrication process that allows more rapid production, thereby to reduce the manufacturing time for IC prototypes, in particular for RFIC prototypes.

SUMMARY OF THE INVENTION

According to a first aspect of the invention there is provided a method of manufacturing an IC, comprising: providing a semiconductor substrate; forming an insulating layer on the substrate; removing the insulating layer at a plurality of locations to form windows that expose areas of the semiconductor substrate; growing semiconductor material in the windows from the exposed areas of the semiconductor substrate to form some of the components of the IC; and depositing conductive material on the insulating layer to form the other components of the IC.

An effective isolation between semiconductor components is achieved by manufacturing semiconductor components, such as transistors and diodes, within windows in an insulating layer grown on a semiconductor substrate. Thus the manufacture of an IC is simplified relative to conventional manufacture, with a resultant reduction in cost and manufacture time. This is because many of the conventional manufacturing steps, which are performed only to provide narrow regions of isolation between components, become unnecessary. The manufacture of narrow regions of isolation between components is important for digital ICs, such as memories or processors, where high integration density is critical. However, for RFICs high integration density is in many cases irrelevant. In fact, for RFICs other problems exist, such as undesired levels of capacitive coupling between the gate, interconnects and LCR components on the one hand, and the source, channel and drain of the MOS transistors on the other hand. The process of the invention simultaneously solves this problem, since the source, channel and drain are physically and electrically separated from the gate, interconnects and LCR components by the insulating layer, since the latter can all be arranged on top of the insulating layer. Furthermore, preventing capacitive coupling with the semiconductor substrate can allow the use of lower-cost, low-resistivity substrates if desired, rather than the specialist high resistivity substrates used conventionally for RFICs.

In one embodiment, the semiconductor material grown on the exposed semiconductor regions is also doped. This doping may be performed by supply of dopants during the growth of the semiconductor material. Doping may also be performed after the growth of the semiconductor material, either before and/or after the depositing of the conductive material by introducing dopants by implantation or diffusion.

In one embodiment, the semiconductor material grown on the exposed regions of the semiconductor substrate is grown to be epitaxial with the semiconductor substrate.

The first aspect of the invention also relates to the products of the method. In particular the invention relates to an integrated circuit, comprising: a semiconductor substrate; an insulating layer arranged on the substrate; semiconductor components extending from the semiconductor substrate through windows in the insulating layer at a plurality of locations distributed over the insulating layer; and metallic components of conductive material arranged on the insulating layer which together with the semiconductor components form the integrated circuit.

A particular advantage of the first aspect of the invention is that until the final step of adding the metallic components, the steps can be kept quite generic to a large number of possible integrated circuit designs, in particular RFIC designs. This is highly advantageous in reducing further the time needed from receipt of a customer prototype order to delivery, since the prototype can be prepared starting from a semifinished wafer or chip that has been prepared already without knowledge of the customer's prototype circuit design. Consequently the first aspect of the invention also relates to the intermediate product prior to deposition of the metallic components. Namely, the invention further relates to a semi-finished integrated circuit, comprising: a semiconductor substrate; an insulating layer arranged on the substrate; and semiconductor components extending from the semiconductor substrate through windows in the insulating layer at a plurality of locations distributed over the insulating layer, such that metallic components of conductive material can later be deposited on the insulating layer to complete the integrated circuit.

According to a second aspect of the invention there is provided a method of manufacturing an IC, comprising: providing a semiconductor substrate; forming an oxidisation-inhibiting layer on the substrate; removing the oxidisation-inhibiting layer at a plurality of locations to select areas of the substrate for oxidisation; oxidising the selected areas of the substrate to form an insulating layer of oxide in the selected areas; removing the oxidisation-inhibiting layer to expose windows of the semiconductor substrate; forming semiconductor components in the windows of the semiconductor substrate; and depositing conductive material on the insulating layer to form metallic components for the IC which together with the semiconductor components form the IC.

The realisation that high packing density is not necessary for RFICs, allows the use of a modified LOCOS technique for fabricating RF circuits. An insulating layer is formed by oxidising the semiconductor substrate to provide an effective isolation between semiconductor components fabricated in the semiconductor substrate. Thus the manufacture of an IC is simplified relative to conventional STI manufacture, with a resultant reduction in cost and manufacture time, since many of the conventional manufacturing steps become unnecessary. The problems suffered by RFIC, such as undesired levels of capacitive coupling between the gate, interconnects and LCR components on the one hand, and the source, channel and drain of the MOS transistors on the other hand are also overcome in this embodiment of the invention, since the source, channel and drain are physically and electrically separated from the gate, interconnects and LCR components by the insulating layer. Furthermore, reduction in capacitive coupling with the semiconductor substrate can allow the use of lower-cost, low-resistivity substrates if desired, rather than the specialist high resistivity substrates required for conventional RFICs.

In one embodiment, the semiconductor material exposed in the windows is also doped. Doping may by introducing dopants by implantation or diffusion.

The second aspect of the invention also relates to the products of the method. In particular the invention relates to an integrated circuit, comprising: a semiconductor substrate; an oxidised insulating layer arranged on the substrate; semiconductor components extending from the semiconductor substrate through windows in the oxidised insulating layer at a plurality of locations distributed over the insulating layer; and metallic components of conductive material arranged on the insulating layer which together with the semiconductor components form the integrated circuit.

In the second aspect of the invention, the semi-finished product prior to the step of depositing the metallic components is significant and valuable in its own right as a generic platform for completion according to customer specifications. Accordingly, the second aspect of the invention also relates to a semi-finished integrated circuit, comprising: a semiconductor substrate; an oxidised insulating layer arranged on the substrate; and semiconductor components extending from the semiconductor substrate through windows in the oxidised insulating layer at a plurality of locations distributed over the insulating layer, such that metallic components of conductive material can later be deposited on the oxidised insulating layer to complete the integrated circuit.

Either aspect of the invention may further include the following.

The semiconductor substrate can be of any suitable material. This includes Group IV elemental substrates, most commonly Si, but also including Ge and C, or compound substrates, such as SiGe, SiC, SiGe(C) or Ge-on-SiGe or related binary or ternary compounds, wherein binary or ternary compounds are generally epitaxial layers on a Si wafer. For example, Ge may be of interest for fabricating the channels of transistors for RFICs in view of the higher carrier mobility, and hence current capacity, compared with Si. In this respect we use the term substrate to include layers deposited on the wafer material of different material type or composition.

In one embodiment, a product comprising a plurality of semiconductor components separated by an insulating layer is manufactured using the method of the invention.

The insulating layer for silicon substrates will most commonly be silicon dioxide. However, silicon nitride may be used instead. In general, any suitable dielectric material can be used. In other cases, a layer of other wide band-gap material may be used as the insulating layer, which may have a different composition than the underlying substrate material to allow composition-specific stop-etching to fabricate the windows as is well known in the art.

The plurality of semiconductor components provided on a semiconductor substrate and separated by an insulating layer to provide a useful prototyping tool, since such a product may be manufactured in advance and the semiconductor components only interconnected with circuit components when a prototype design is available.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention and to show how the same may be carried into effect reference is now made by way of example to the accompanying drawings.

Figures 1A-1C show cross-sections through a semiconductor substrate and an insulating layer manufactured by different prior art methods.

Figures 2A and 2B show a plan view and a side view of a window etched in an insulating layer covering the surface of a semiconductor substrate according to a first embodiment of the invention.

Figure 3 A to 3F show the stages in the manufacture of an n-channel FET by a first manufacturing method of the first embodiment.

Figure 4 shows a plan view of a transistor fabricated by the manufacturing method of the first embodiment.

Figure 5 A to 5D show the stages in the manufacture of an n-channel FET by a manufacturing method according to a second embodiment of the present invention.

Figure 6 shows a plan view of an intermediate IC with a plurality of transistors fabricated by the manufacturing method of the present invention.

Figure 7 shows an FET amplifier circuit for an oscillator manufactured using a manufacturing method of the present invention.

DETAILED DESCRIPTION

Figure 2A shows a plan view of a window 20 comprising a first section 22, a channel 24 and a third section 26 etched into an insulating layer 28 grown on a semiconductor substrate. The dumbbell shape of the window 20 is representative of only one of a plurality of possible shapes. A plurality of windows 20 of identical and/or different shape may be etched into the insulating layer 28. The insulating layer 28 may be grown on the semiconductor substrate using standard techniques such as oxide growth or deposition, or nitride deposition. Standard lithographic and etching techniques are used to define the window 20.

Figure 2B shows a side view of the window 20, which is etched through the insulating layer 28 to expose the surface of the semiconductor substrate 30.

Figures 3 A to 3F show the manufacture of a CMOS semiconductor component by the method of the present invention. The manufacture of an n-channel FET in the window 20 will be described.

Figure 3A shows a device 31 comprising a p-type semiconductor substrate 30 upon which an insulating layer 32 has been deposited. The insulating layer 32 may be formed as an oxide, a nitride or a alternative dielectric on the semiconductor substrate 30 by conventional methods.

Figure 3B shows the device 31 with a window 20 etched into the insulating layer 32.

Figure 3C shows the device 31 with a regrown semiconductor 34 filling the window 20. Various techniques are known in the art for depositing a regrown semiconductor 34. One technique particularly suited to the present invention, is that of selective epitaxial growth. Selective epitaxial growth allows epitaxial deposition of a semiconductor material on a semiconductor substrate 30 whilst inhibiting semiconductor deposition on the insulating layer 32. The regrown semiconductor 34 may be doped during deposition dependent on the semiconductor component that is fabricated.

Whereas prior art manufacture methods, such as that discussed above, fabricate semiconductor components in the semiconductor substrate 30, the method of the present invention fabricates semiconductor components in the regrown semiconductor

34 grown in the plurality of windows 20. The difficulties in achieving good isolation between semiconductor components with conventional high-density fabrication processes do not arise, since the plurality of re-grown semiconductor 34 regions are separated by the insulating layer 32. The insulating layer 32 may be as thick as required to provide sufficient isolation. The windows 20 in the insulating layer 32 may be widely separated laterally, for example, by distances of between 5 to 100 micrometres. This is desirable for many RP applications in order to provide sufficient area on top of the insulating layer to form the LCR components, i.e. inductors, capacitors and resistors, as well as the conducting interconnects.

Figure 3D shows the device 31 following growth of a layer of gate insulation 36 and a layer of conductive material 38. The conductive material 38 may be fabricated from polysilicon, titanium nitride or a metal, such as aluminium, copper or tungsten. The gate insulation 36 may be a layer of oxide, nitrided oxide or an alternative dielectric. The gate insulation 36 performs the function of separating the gate electrode from the channel between the source and drain of the FET. The conductive material 38 is used to form the gate electrode.

Figure 3E shows the device 31 following etching of the conductive material 38 and the gate insulation 36. The etched conductive material forms the gate electrode 39. The n-type doped source 40 and drain 42 are also shown in this Figure. The regions of regrown semiconductor corresponding to the source 40 and drain 42 are doped with phosphorus (or a similar dopant) so that these regions become n-type semiconductors. The doping may be by self-aligned implantation, during which the dopants are introduced to the surface of the device 31 and are selectively blocked by the gate electrode 39 and the insulating layer 32. Thus, the implantation of dopants is patterned by the existing structure of the device 31, and the length of the channel between the source 40 and drain 42 is controlled by the length of the gate electrode 39. The self-aligned implantation may also dope the gate electrode 39 to improve its conductivity, which is of importance if the gate electrode 39 is fabricated from a relatively low conductivity material such as polysilicon. Alternatively, the source 40 and drain 42 doping may be performed during growth of the regrown semiconductor 34 by the selective introduction of dopants into the constituent gas mixture. Other doping methods known in the prior art may also be used, such as diffusion. Spacers 44 may be fabricated either side of the gate insulation 36 and the conductive material 38 to increase the length of the channel, i.e. the distance between the source 40 and the drain 42, without having to increase the gate length, i.e. the extent of the gate electrode 39 in the direction between the source 40 and the drain 42.

In this respect, it is noted that gate length is used in the art to refer to what has become the short dimension of the gate electrode, contrary to normal English usage where one would refer to this dimension as the width, since the gate length is referring to the length transited by the charge carriers in the channel in the source-drain direction, not to the shape of the electrode itself.

The gate length provided by the gate electrode 39 can be selected in the range between the minimum possible as dictated by the lithography process, and the maximum allowed by the relevant lateral dimension of the regrown semiconductor material 34, which is dependent only on the earlier processing of the device 31. Gate lengths of approximately 30 nm can be obtained with current electron-beam lithography machines, or approximately 100 nm using current phase shift mask technology. Short gate lengths are desirable in RFICs since they allow access to higher RF frequencies. The width of the spacers 44 may also be varied. Thus, there is a high level of control over the gate length. FETs with different gate lengths may be fabricated on the same device 31. The gate width is determined only by the width of the window 20 etched into the insulating layer 32. Relative to digital ICs, it is desirable to fabricate FETs with wide gate widths, since in RFICs this allows more current to be drawn, and hence, more power from the semiconductor component. Figure 3F shows the finished n-channel FET following deposition of a drain electrode 46 and a source electrode 48 to contact the drain 42 and source 40 respectively. The drain electrode 46 and the source electrode 48 may be fabricated from a conductive material such as a metal, suicide, polycrystalline silicon or other semiconductor, or degenerately doped single crystal semiconductor, and may be deposited using a simple evaporation technique. If fabricated on a silicon semiconductor substrate 30, the conductive material 38, drain electrode 46 and source electrode 48 may be suicided to reduce the electrical contact and sheet resistance of these regions.

The fabrication of an n-channel FET is straightforwardly adaptable to fabricate p- channel FETs by starting with an oppositely doped regrown semiconductor and using a different dopant in the doping step. Thus CMOS devices are simple to manufacture. Indeed, CMOS devices may be fabricated by selectively etching a first plurality of windows 20 and regrowing n-type semiconductor material, then etching a second plurality of windows in which a p-type regrown semiconductor is grown. Furthermore, the fabrication of an n-channel FET described above is only an example of the semiconductor components that may be fabricated using the method of the present invention, many other semiconductor components can also be manufactured.

Figure 4 shows a plan view of a transistor 52, such as the n-channel FET described above, following deposition of gate contacts 50, source contact 51 and drain contact 53. The source contact 50, drain contact 53 and gate contacts 50 may lie predominantly on the insulating layer 32 to aid in reducing capacitive coupling with the semiconductor substrate 30. The source contact 50, drain contact 53 and gate contacts 50 may be relatively large without degradation in device operation, so that these contacts may be fabricated using relatively simple and inexpensive photolithography and deposition of a metal, such as aluminium or copper, by evaporation. In fact, large contact areas are preferred during prototyping of ICs as they are relatively easily connected to the probe stations used to test such ICs. It will be appreciated that the gate may be fabricated using electron beam lithography to provide a short gate length, for example 30-100 nm, but high-resolution optical lithography may be used, e.g. using phase masks. The gate contact pads as well as the source and drain contacts will typically be fabricated using optical lithography.

Figures 5A to 5D show the manufacture of a CMOS semiconductor device 70 by a second method of the present invention. The manufacture of an n-channel FET will be described to aid comparison with the prior art method discussed above.

Figure 5A shows the device 70 comprising a p-type silicon substrate 62 upon which a layer of an oxidisation-inhibiting material 60 has been deposited. The oxidisation- inhibiting material 60 may be silicon nitride or any other material that can serve to inhibit subsequent oxidation of the underlying silicon during an oxidisation step. Although not shown in the Figure, a layer of a buffer oxide may be deposited before the oxidisation-inhibiting material, as is known in the art, to prevent dislocations in the silicon substrate during growth of the silicon dioxide layer discussed below.

Figure 5B shows the device 70 following etching of the oxidisation-inhibiting material 60 to expose areas of the silicon substrate 62.

Figure 5C shows the device 70 with regions of silicon dioxide 64 formed during oxidation of the exposed areas of silicon. Oxidising the exposed silicon causes the formation of regions of silicon dioxide 64 that penetrate into, and also swell out of, the surface of the silicon substrate 62. These regions of silicon dioxide 64 form the insulation between components that are manufactured later in the method.

The masked regions of the silicon substrate, in which semiconductor components will be fabricated, may be separated by relatively large distances of at least 5 or 10 micrometres, typically by up to 50 or 100 micrometres. This large separation between the active semiconductor component regions is not merely tolerable, but is actually useful and necessary to provide sufficient areas of silicon dioxide upon which the RF components of the IC, e.g. inductors, capacitors and so forth, can be fabricated. Moreover, with this large separation of the masked regions, the lateral extent of the Bird's Beaks is not limiting.

Figure 5D shows the finished n-channel FET following stripping of the oxidisation- inhibiting material, doping of the source 74 and drain 76, and deposition of a gate insulation 73 and a drain electrode 66, a source electrode 68 and a gate electrode 72.

The excess oxidisation-inhibiting material 60 is stripped from the silicon substrate using a standard etching technique. The exposed regions of silicon may then be doped with phosphorus (or another n-type dopant) to produce n-type silicon regions that form the source 74 and the drain 76. A gate insulation 73 and a conductive layer are deposited on the substrate 62 and are selectively etched to leave a drain electrode 66, a source electrode 68 and a gate electrode 72. The conductive layer may be a layer of metal such as aluminium or copper, or may be a polysilicon layer. Conductive components such as capacitors and inductors may be formed during the same deposition and etch steps.

The fabrication of an n-channel FET is straightforwardly adaptable to fabricate p- channel FETs by starting with an n-type doped substrate and using a p-type dopant (such as boron) in the doping step. Alternatively, n-type wells may be formed in a p- type substrate and the p-channel FETs may then be manufactured in the n-type wells. Thus CMOS devices are simple to manufacture. Furthermore, the fabrication of an n- channel FET described above is only an example of the semiconductor components that may be fabricated using the described method, many other semiconductor components can also be manufactured.

Figure 6 shows an intermediate IC 60 with a plurality of transistors 52 fabricated by a method of the present invention and separated by an insulating layer 82. The plurality of transistors 52 may be fabricated in parallel, and are separated from neighbouring transistors 52 by relatively large distances of 5 or 10 micrometres or more, typically by up to 50 or 100 micrometres. The resulting intermediate IC 80 comprises a plurality of unconnected transistors 52 separated from neighbouring transistors 52 and surrounded by regions of an insulating layer 82. This allows further components such as interconnects, capacitors, resistors and inductors to be fabricated on the insulating layer 82 using conventional techniques so that the transistors 52 may be connected dependent on a desired circuit design. Thus, the intermediate IC 80 is a useful prototyping tool. After designing a prototype IC the developer merely needs to fabricate the further components onto the insulating layer 82 and connect the transistors 52 together as required by the IC design. In comparison to conventional prototyping, this method is significantly faster and incurs a significantly lower cost because the transistors 52 are supplied pre-fabricated and ready for connection. Furthermore, since the number of fabrication steps are significantly reduced over conventional prototyping, the ICs produced by this prototyping method are significantly more reproducible than prototype ICs fabricated by conventional means.

The intermediate IC 80 can also be used to test the electrical characteristics of transistors 52 dependent on different circuit designs.

Figure 7 shows an example FET amplifier circuit 110, which may be used as an oscillator, manufactured on the intermediate IC 60 by a method according to either the first or second embodiment of the invention. The FET amplifier circuit 110 is chosen as a simple example circuit and is not intended to limit the type of circuits that may be manufactured using a method of the present invention. The FET amplifier circuit 1 10 comprises nodes for the connection of the voltage in 90, voltage out 92, supply voltage 94, and ground 96. The RF components used in the FET amplifier circuit 110 are fabricated directly onto the insulating layer 82, and as such are capacitively decoupled from the semiconductor substrate. The RF components shown in the FET amplifier circuit 110 are resistors 98, an inductor 100, and a capacitor 102. One of the FET transistors 52 available on the intermediate IC 60 is connected to the RF components by conductive interconnects 104. The FET transistor 52 used in the FET amplifier circuit 110 is connected as follows, the gate is connected through a resistor to the voltage in 90, the drain is connected to the ground 96 and the source is connected through the inductor 100 to the supply voltage 94. The remaining FET transistors 52 on the intermediate IC 60 are not connected. Rather than starting from the intermediate IC 60, the FET amplifier circuit 110 may have been manufactured directly after manufacturing the FET transistors 52 and the insulating layer 82.

Manufacturing the FET amplifier circuit 110 using standard techniques may require 4-8 months of processing time. However, if the manufacturing process starts from the intermediate IC 60, then the only step required is the deposition of the RF components and the interconnects 104. This, may require only a single masking step followed by the evaporation of a metal to fabricate the components and interconnects 104. Thus, the required time for manufacturing a prototype circuit can be significantly reduced. It is clear from the above example that many simple circuits may be manufactured in parallel on the same substrate, allowing different prototype designs to be tested. Alternatively, more complex circuit designs that require two or more FETs may be manufactured.

Claims

1. A method of manufacturing a radio frequency integrated circuit, comprising: providing a semiconductor substrate; forming an insulating layer on the substrate; removing the insulating layer at a plurality of locations to form windows that expose areas of the semiconductor substrate; growing semiconductor material in the windows from the exposed areas of the semiconductor substrate to form semiconductor components for the radio frequency integrated circuit; and depositing conductive material on the insulating layer to form metallic components for the radio frequency integrated circuit which together with the semiconductor components form the radio frequency integrated circuit.

2. The method of claim 1 further comprising: doping the semiconductor material in the windows.

3. The method of claim 2, wherein the doping is carried out as part of said growing.

4. The method of claim 2, wherein the doping is carried out between said growing and said depositing by external introduction of dopants.

5. The method of claim 2, wherein the doping is carried out after said depositing by external introduction of dopants.

6. The method of any claims 4 or 5, wherein the external introduction of the dopants is by one of implantation and diffusion.

7. The method of any preceding claim, wherein the semiconductor material grown in the windows is epitaxial with the semiconductor substrate.

8. The method of any preceding claim, wherein the metallic components comprise inductors, capacitors and/or resistors.

9. The method of any preceding claim, wherein the metallic components comprise gates.

10. The method of any preceding claim, wherein the semiconductor components comprise sources, channels and drains.

11. The method of any preceding claim, wherein the semiconductor components are formed at least partially in one of silicon, germanium, silicon-carbon alloy, silicon-germanium alloy and silicon-germanium-carbon alloy.

12. The method of any preceding claim, wherein the windows are separated by a distance of at least 5 micrometres.

13. A radio frequency integrated circuit, comprising: a semiconductor substrate; an insulating layer arranged on the substrate; semiconductor components extending from the semiconductor substrate through windows in the insulating layer at a plurality of locations distributed over the insulating layer; and metallic components of conductive material arranged on the insulating layer which together with the semiconductor components form the radio frequency integrated circuit.

14. The circuit of claim 13, wherein the metallic components comprise inductors, capacitors and/or resistors.

15. The circuit of claim 13 or 14, wherein the metallic components comprise gates.

16. The circuit of claim 13, 14 or 15, wherein the semiconductor components comprise sources, channels and drains.

17. The circuit of any of claims 13 to 16, wherein the windows are separated by a distance of at least 5 micrometres.

18. A semi-finished radio frequency integrated circuit, comprising: a semiconductor substrate; an insulating layer arranged on the substrate; and semiconductor components extending from the semiconductor substrate through windows in the insulating layer at a plurality of locations distributed over the insulating layer, such that metallic components of conductive material can later be deposited on the insulating layer to complete the radio frequency integrated circuit.

19. The circuit of claim 18, wherein the semiconductor components comprise sources, channels and drains.

20. The circuit of claim 18 or 19, wherein the windows are separated by a distance of at least 5 micrometres.

21. A method of manufacturing a radio frequency integrated circuit, comprising: providing a semiconductor substrate; forming an oxidisation-inhibiting layer on the substrate; removing the oxidisation-inhibiting layer at a plurality of locations to select areas of the substrate for oxidisation; oxidising the selected areas of the substrate to form an insulating layer of oxide in the selected areas; removing the oxidisation-inhibiting layer to expose windows of the semiconductor substrate; forming semiconductor components in the windows of the semiconductor substrate; and depositing conductive material on the insulating layer to form metallic components for the radio frequency integrated circuit which together with the semiconductor components form the radio frequency integrated circuit.

22. The method of claim 21 further comprising: doping the semiconductor material in the windows.

23. The method of any claim 22, wherein the introduction of the dopants is by one of implantation and diffusion.

24. The method of any of claims 21 to 23, wherein the semiconductor components are formed at least partially in one of silicon, germanium, silicon-carbon alloy, silicon-germanium alloy and silicon-germanium-carbon alloy.

25. The method of any of claims 21 to 24, wherein the windows are separated by a distance of at least 5 micrometres.

26. A radio frequency integrated circuit, comprising: a semiconductor substrate; an oxidised insulating layer arranged on the substrate; semiconductor components extending from the semiconductor substrate through windows in the oxidised insulating layer at a plurality of locations distributed over the insulating layer; and metallic components of conductive material arranged on the insulating layer which together with the semiconductor components form the radio frequency integrated circuit.

27. A semi-finished radio frequency integrated circuit, comprising: a semiconductor substrate; an oxidised insulating layer arranged on the substrate; and semiconductor components extending from the semiconductor substrate through windows in the oxidised insulating layer at a plurality of locations distributed over the insulating layer, such that metallic components of conductive material can later be deposited on the oxidised insulating layer to complete the radio frequency integrated circuit.

28. A product manufactured by the method of any of claims 1 to 12.

29. A product manufactured by the method of any of claims 21 to 25.