JP2010141349A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having a low-power consumption and high-speed MOSFET, by using the combination of Si and an element belonging to the same group as Si, like Ge or C. <P>SOLUTION: In the method for manufacturing a semiconductor device including an Si layer 1, a gate electrode 16 of the MOSFET formed over the Si layer 1, a source region 14 and a drain region 15 formed in the Si layer 1, and a channel region formed in an area between them, the Si layer in an area where the source region 14 or the drain region 15 is formed is selectively etched, and SiGe is selectively grown in a groove formed by the selective etching. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a field effect transistor.

  In integrated circuits using SiMOS-type field effect transistors (Si-MOSFETs), reductions in power consumption and speed have been achieved by reducing device dimensions and operating voltage according to the so-called scaling law. It was.

  However, many problems have arisen, such as a problem of the short channel effect that occurs as a result of size reduction, and a reduction in operation margin due to the proximity of the drain voltage and the threshold voltage, which becomes noticeable when the voltage is lowered.

  Looking at the mobility, which is an index for speeding up, the various improvements described above ironically make the Si mobility in real devices less than 100, far below the bulk value. ing.

  As described above, it has become extremely difficult to improve the performance of the conventional Si-MOSFET.

  Note that Patent Document 1 and Non-Patent Document 1 suggest that when strain is applied to Si or Ge, the mobility of carriers can be increased compared to Si or Ge that is not subjected to strain.

JP-A-6-177375

M.M. V. Fischetti and S. E. Laux: J.M. Appl. Phys. 80 (1996) 2234

  For further performance improvement, it is necessary to increase the speed by improving the semiconductor material itself. The use of so-called compound semiconductors that are inherently high-speed is one solution, but is difficult in terms of compatibility with the manufacturing technology of Si integrated circuits, and the manufacturing cost is enormous, so it is realistic. Is not a good solution.

  An object of the present invention is to provide a semiconductor device having a low-power consumption and high-speed field effect transistor by using a combination of Si, Ge and C which are the elements of the same family.

  The above object can be achieved by applying a strain to the channel forming layer in which the channel of the field effect transistor is formed by the strain applying semiconductor layer so that the mobility of carriers in the channel is larger than the material of the unstrained channel forming layer. . For example, when the material of the channel formation layer is Si, the lattice constant in the surface of the Si channel formation layer is made larger than that of unstrained Si by applying strain.

  Non-Patent Document 1 suggests that when strain is applied to Si or Ge, the mobility of carriers can be increased as compared to Si or Ge that is not subjected to strain. This is the same as the phenomenon that when Si is deposited on sapphire, the mobility increases due to the in-plane strain of Si, and it has been known for a long time. The present invention applies this phenomenon to manufacture a field effect transistor and a semiconductor device such as an integrated circuit using the same.

  Another object of the present invention is to provide a p-type field effect transistor in which the energy at the apex of the valence band at the interface between the channel forming layer and the layer adjacent to both sides of the channel forming layer is larger on the gate insulating film side than on the other side. This can also be achieved by a semiconductor device.

  Another object of the present invention is to provide a semiconductor having an n-type field effect transistor in which the energy at the apex of the conduction band at the interface between the channel forming layer and the layer adjacent to both sides of the channel forming layer is smaller on the gate insulating film side than the other. It can also be achieved by a device.

  In addition, the above-mentioned purpose is to have a structure in which an energy barrier against carriers in the channel of the field effect transistor exists on the side opposite to the gate insulating film with respect to the channel, and distort the lattice of the channel forming layer in which the channel is formed, It can also be achieved by making the carrier mobility in the channel larger than the material of the unstrained channel forming layer.

  According to the present invention, a high speed and low power consumption complementary field effect transistor and a semiconductor device incorporating the same can be realized.

It is a band figure of the laminated structure of SiO ₂ gate insulating film / strained Si layer / Si _1-x Ge _x strain application layer which is a specific example of the present invention. FIG. 2 is a band diagram showing a state in which a positive bias is applied to the gate having the structure shown in FIG. 1. FIG. 2 is a band diagram showing a state in which a negative bias is applied to the gate having the structure shown in FIG. 1. FIG. 2 is a band diagram showing a state where steep n-type doping is applied to the uppermost portion of the Si _1-x Ge _x strain application layer having the structure shown in FIG. FIG. 2 is a band diagram in a state where a substrate bias voltage is applied to the structure shown in FIG. 1. It is a band figure of the laminated structure of SiO ₂ gate insulating film / strained Si layer / strained Si _1-y Ge _y layer / Si _1-x Ge _x strain application layer which is a specific example of the present invention. 1 is a cross-sectional structure diagram of a complementary field effect transistor according to a first embodiment of the present invention. It is a cross-section figure of the complementary field effect transistor of Example 2 of this invention. It is a cross-section figure of the complementary field effect transistor of Example 3 of this invention. It is a cross-section figure of the complementary field effect transistor of Example 4 of this invention. It is sectional structure drawing of the complementary field effect transistor of Example 5 of this invention. It is a cross-section figure of the complementary field effect transistor of Example 6 of this invention. It is a cross-section figure of the complementary field effect transistor of Example 7 of this invention. It is sectional drawing of the SOI substrate of Example 8 of this invention. It is sectional drawing of the SOI substrate of Example 9 of this invention. It is manufacturing process sectional drawing of the SOI substrate of Example 10 of this invention.

First, the band structure and operation principle of a field effect transistor having a strained Si channel will be described. It is appropriate to use Si _1-x Ge _x (0 <x <1) for the strain applying layer that applies strain to Si. FIG. 1 shows a band diagram of a laminated structure of SiO ₂ gate insulating film 3 / strained Si layer 1 / Si _1-x Ge _x strain applied layer 2. The band gap 6 of the strained Si layer 1 is wider than the band gap 7 of the Si _1-x Ge _x strain applying layer 2, and both the valence band 5 and the conduction band 4 exhibit band discontinuity of a type in which the energy decreases.

  In the case of an n-type field effect transistor, if a positive voltage is applied to the gate, the band bends near the interface between the gate insulating film 3 and the strained Si layer 1 as shown in FIG. Electrons are accumulated in the triangular well 10 of the conduction band in the layer 1 so that transistor operation can be performed. This is exactly the same as a normal MOS field effect transistor.

In the case of a P-type field effect transistor, if a negative voltage is applied to the gate, the band bends near the interface between the gate insulating film 3 and the strained Si layer 1 as shown in FIG. However, than the triangular well 11 of the valence band in the strained Si layer 1 made in this part, _{Si 1-x} Ge _x distortion made in the interface of the strained Si layer 1 and the _{Si 1-x} Ge _x strain applying layer 2 Many holes are accumulated in the triangular well 12 of the valence band in the application layer 2. However, since the mobility of holes in the Si _1-x Ge _x strain application layer 2 is significantly smaller than that of the strained Si layer 1, the speed cannot be improved as compared with a normal MOS field effect transistor. There is. In addition, when a complementary field effect transistor is configured, there is a problem that it is difficult to balance the pn channels.

In order to solve such a problem, it is only necessary to reduce the accumulation of holes in the triangular well 12, and there are the following methods. The first method prevents the outflow of holes to the Si _1-x Ge _x strain applying layer 2 by making the source / drain junction depth sufficiently shallower than the thickness of the strained Si layer 1. Specifically, the junction depth may be about 40 nm when the thickness of the strained Si layer 1 is, for example, 70 nm. This is a value that is not much different from the value used in a short channel device with a channel length of 0.1 microns or less, and is a sufficiently realizable value.

The second _method, preferably the depth 0.1~30nm range in the vicinity of the interface between the strained Si layer 1 of _{Si 1-x} Ge _x strain applying layer 2, a method of performing steeply n-type doping. By this method, as shown in FIG. 4, the energy level of the apex 43 of the triangular well 12 of the valence band in the Si _1-x Ge _x strain application layer 2 is lowered. For example, it becomes lower than the energy level of the apex 42 of the triangular well 11 of the valence band in the strained Si layer 1. As a result, the accumulation of holes in the triangular well 12 is reduced. This method can also be realized by performing n-type doping on the strained Si layer 1 or both the strained Si layer 1 and the Si _1-x Ge _x strain applying layer 2. In these cases, the doping depth is preferably in the range of 0.1 to 30 nm.

The third method is a method of controlling the substrate bias voltage so that a positive voltage is applied to the Si _1-x Ge _x strain application layer 2 side. By this method, as shown in FIG. 5, the Si _1-x Ge _x strain applying layer 2 side is lowered to the lower right band structure, and the energy level of the apex 42 of the triangular well 11 of the valence band in the strained Si layer 1 is obtained. Rather, the energy level of the apex 43 of the triangular well 12 in the valence band in the Si _1-x Ge _x strain application layer 2 is lower. As a result, the accumulation of holes in the triangular well 12 is reduced.

As described above, preventing the outflow of holes from the strained Si channel to the strain applying layer is an essential factor for realizing a p-type field effect transistor or a complementary field effect transistor. Furthermore, in order to increase the device speed and voltage, it is also effective to adopt the following configuration. That is, the material of the drain region in the case of a p-type field effect transistor and the source region in the case of an n-type field effect transistor are the same base material as the Si _1-x Ge _x strain application layer, preferably the same composition ratio. In this way, the distribution of the electric field between the source and drain changes due to the band discontinuity between strained Si and SiGe, and carriers can be accelerated more effectively. As a result, the speed can be further increased, and the operation at a lower voltage can be performed by lowering the pinch-off voltage.

Up to this point, transistors having strained Si as a channel for both electrons and holes have been described. However, for holes, the use of strained Si _1-y Ge _y (0 <y ≦ 1) as a channel further increases the mobility. That is, speeding up is realized. When Si _1-x Ge _x is used for the strain applying layer, in _- plane tensile strain is applied to Si laminated thereon, and in-plane compressive strain is applied to Si _1-y Ge _y .

When the strained Si _1-y Ge _y layer 25, the strained Si layer 1, and the gate insulating film 3 are stacked in this order on the Si _1-x Ge _x strain applying layer 2, a band diagram as shown in FIG. Si layer 1 and the electronic conical wells 10 of the conduction band in the strained Si layer 1 in the vicinity of the interface between the gate insulating film 3 is, the distortion near the interface of the strained Si layer 1 and the strained _{Si 1-y} Ge _y layer 25 _{Si 1-} Holes are accumulated in the triangular well 20 of the valence band in the _y Ge _y layer 25. Unlike the case where the strained Si layer 1 is used for a hole channel, the outflow of holes to the strain applying layer 2 is unlikely to occur. The strained Si layer 1 and the strained Si _1-y Ge _y layer 25 can be operated as a device regardless of the stacking order. However, since the mobility of holes in the strained Si _1-y Ge _y layer 25 is higher than the mobility of electrons in the strained Si layer 1, the mutual conductance of the complementary field effect transistor is reduced. Considering the equilibrium, it is desirable that the strained Si _1-y Ge _y layer 25 is far from the gate electrode, that is, the layer is under the strained Si layer 1.

Further, another SiGe layer may be interposed between the strained Si layer 1 or the strained Si _1-y Ge _y layer 25 and the gate insulating film 3. In this case, since electrons or holes are accumulated in the strained Si layer 1 or the strained Si _1-y Ge _y layer 25 near the interface with the SiGe layer, it is affected by the interface state and scattering of the gate insulating film 3. No need.

Also, the strained Si layer and the strained Si _1-y Ge _y layer are not stacked, and a selective growth method or the like is used to form a strained Si _1-y Ge _y layer in the p-channel region and a strained Si layer in the n-channel region. The layer may be grown.

It is desirable to use Si _1-x Ge _x for the strain applying layer. In Si and Ge, the lattice constant of Ge is as large as about 4%. The lattice constant of Si _1-x Ge _x takes an interpolated value according to the Ge composition ratio x. Therefore, if an appropriate x is selected, a desired strain can be applied to Si or Ge laminated thereon. For example, if x is 0.5, in-plane tensile strain and in-plane compressive strain of 2% each for Si and Ge can be applied. Depending on how x is selected, the magnitude of strain between Si and Si _1-y Ge _y can be controlled appropriately. That is, the in-plane lattice constant of the strained Si layer can be increased in a range of less than 4% with respect to the unstrained Si, and the in-plane lattice constant of the strained Si _1-y Ge _y layer can be increased with respect to the unstrained Ge. It can be reduced within a range of less than 4%. As a result, the balance between the mobility of electrons and holes can be controlled, so that the mutual conductance of the complementary field effect transistor can be balanced. Conventional complementary field effect transistors are adjusted only by changing the dimensions of the element, but this method further increases the degree of freedom in design and is advantageous for high integration.

Besides control of the distortion which changes the _{Si 1-x} Ge _x of the Ge composition ratio x, the addition of _{C (Si 1-x Ge x} ) may be changed the composition ratio y of _{1-y C y.} As a method of adding C, C may be added during the growth of the strain applying layer, or may be added by a method such as ion implantation after the strain applying layer is grown.

The strain applying layer may be a method of growing Si _1-x Ge _x having a constant composition, a method of gradually increasing the composition ratio x from the Si substrate in the growth direction, or a so-called graded buffer layer. Further, when a Si layer having a high defect density is grown on a Si substrate at a low temperature, or a defect layer is formed by a method such as ion implantation of hydrogen, Si or Ge, and then Si _1-x Ge _x is grown, Compared to the case where Si _1-x Ge _x is grown directly on the Si substrate, the threading transition density can be reduced, and the surface flatness is improved, which is preferable.

Further, if the substrate and the strain applying layer have a so-called SOI (Silicon on insulator) structure, the stray capacitance can be reduced to further increase the speed. Bonded SOI substrates and SIMOX (Separation by Implanted Oxigen) substrates are commercially available as SOI, and a strained Si that takes advantage of SOI by growing a Si _1-x Ge _x strain applying layer on this substrate. A (Si _1-y Ge _y (0 <y ≦ 1)) field effect transistor can be manufactured.

In addition, a Si _1-x Ge _x strain application layer is first grown on the Si substrate, and then oxygen ions are implanted and heat treatment is performed, so that SiO ₁ can be incorporated into the Si _1-x Ge _x strain application layer or Si immediately below it. ₍₂₎ Embedding an insulating layer and then growing a strained Si layer, or first growing a Si _1-x Ge _x strain applying layer and a strained Si layer on a Si substrate, and then implanting oxygen ions and performing heat treatment Thus, it is possible to use a method of embedding the SiO ₂ insulating layer inside the strained Si layer. When these methods are used, the thickness of the SOI active layer can be reduced, the element isolation is excellent, and the pMOS and nMOS well layers are not required. In the latter case, since there is a SiO ₂ insulating layer directly under the strained Si layer, the problem of outflow of holes to the strain applying layer in the pMOS as described above does not occur.

Alternatively, a Si _1-x Ge _x strain applying layer is grown on a Si substrate, and after further growing a Si layer, a substrate is prepared by thermally oxidizing part or all of the Si layer. Alternatively, instead of thermal oxidation of the Si layer, a SiO ₂ layer may be grown on the Si _1-x Ge _x strain application layer by vapor phase epitaxy or the like. And this with the bonded face to face the support substrate and the SiO ₂ prepared separately, further Si _1-x Ge _x polishing the Si substrate grown side strain applied layer, or implantation of hydrogen ions and middle porous When the Si _1-x Ge _x strain application layer is exposed by cutting by a technique such as inserting a Si layer, a bonded SOI substrate with the Si _1-x Ge _x strain application layer can be manufactured. According to this method, a portion having a high defect density close to the Si substrate in the Si _1-x Ge _x strain application layer can be removed, so that the defect density can be reduced. It becomes easy to ensure flatness. Also, this method makes it possible to reduce the thickness of the SOI active layer and provide excellent element isolation, eliminating the need for well layers for pMOS and nMOS.

Upon cleavage of the bonded SOI _substrate, it is not always necessary to leave the _{Si 1-x} Ge _x strained applied layer. That is, a Si _1-x Ge _x strain applying layer is grown on a Si substrate, a strained Si layer is further grown, and a support substrate prepared separately by thermally oxidizing a part thereof and SiO ₂ are bonded to each other. The substrate having the strained Si layer on the SiO ₂ layer can be manufactured by cutting or polishing while leaving the strained Si layer portion. This substrate looks exactly the same as a conventional bonded SOI substrate, and only the SOI layer is distorted.
Therefore, it can be handled in the same manner as a conventional SOI substrate, has excellent element isolation, eliminates the need for a well layer for pMOS and nMOS, and reduces the effective mass of the SOI active layer due to the strain effect. The strain Si is characterized by high hole mobility. In addition, since there is a SiO ₂ insulating layer directly under the strained Si layer, the problem of outflow of holes to the strain applying layer in the pMOS as described above does not occur.

There is a certain limitation on the thickness of the strained Si layer. This is because there is an upper limit of the thickness of the strained Si layer that can be grown without transition depending on the magnitude of strain. This is called the critical film thickness. In the case where a strained Si layer is grown on the Si _1-x Ge _x strain application layer, for example, when x = 0.2, the magnitude of the strain is about 0.8%. The critical film thickness is about 100 nm, and when x = 0.5, the strain is about 2% and the critical film thickness is about 10 nm. However, the critical film thickness depends on the growth conditions of the strained Si layer and cannot be determined uniquely. In addition, the above-described restriction is different in the case of a structure in which an oxide film layer is inserted between the SOI substrate and the strained Si layer. However, the strained Si layer film has a composition that realizes a practically significant strain magnitude in the range of x in the range of about 0.2 to 0.8, and in the range of about 0.8 to 3.2% in terms of strain. It is desirable that the thickness is in the range of 1 nm to 200 nm. If the thickness is less than 1 nm, the thickness of the active layer forming a channel in the field effect transistor is insufficient, and if the thickness is more than 200 nm, occurrence of transition starts and adverse effects on the electrical characteristics begin to occur.

  The selection of the plane orientation of the substrate crystal to be used and the selection of the relationship between the carrier traveling directions in the channels are necessary requirements for higher speed operation.

  The use of the {100} plane as the substrate plane orientation is advantageous in terms of coupling with conventional elements and the use of the same process, since many conventional Si semiconductor elements use this plane orientation. The mobility when applying is greatly increased, which is a desirable crystal orientation. In this case, it is advantageous to improve the controllability of processes such as epi-growth and etching when the in-plane direction of the channel is the <110> or <001> direction.

  It is also possible to use the {110} plane as the substrate plane orientation. In this case, the channel direction is preferably <110> or <001> from the viewpoint of increasing the mobility by applying strain. It is more desirable to use the <110> direction as the electron channel. However, this arrangement is not necessarily required in consideration of the balance between the nMOSFET and the pMOSFET.

  As described above, a field effect transistor or a complementary field effect transistor in which an active layer forming a channel is distorted and a semiconductor device using the field effect transistor have a lighter effective mass of carriers flowing through the channel than conventional ones. Therefore, the industrial value is extremely high because the mobility is high, the speed can be increased, and the integration and performance of the element can be increased.

  Hereinafter, the present invention will be described in detail by way of examples.

Example 1
FIG. 7 is a cross-sectional view of the CMOSFET according to this embodiment. After cleaning the Si substrate 13, it is immediately introduced into the chemical vapor deposition apparatus to grow the Si _0.7 Ge _0.3 strain application layer 2. The plane orientation of the Si substrate 13 is {100}. The film thickness is 500 nm. Si ₂ H ₆ and GeH ₄ are used as raw materials and grown at a growth temperature of 700 ° C. Here, doping for determining the conductivity type is not performed. The Ge composition ratio x of the Si _1-x Ge _x strain application layer 2 can be controlled in any way, but in order to optimize the strain applied to the strained Si layer 1, x is 0.2-0. A value of 4 gives good results.

Next, the strained Si layer 1 is formed on the Si _1-x Ge _x strain application layer 2 by chemical vapor deposition. Here, doping for determining the conductivity type is not performed. The film thickness was 60 nm. This layer is subjected to in-plane tensile strain because the lattice constant of the Si _1-x Ge _x strain application layer 2 is larger than Si. Thereby, the carrier (electron and hole) mobility in this becomes larger than in unstrained Si. Note that the growth of the Si layer and the SiGe layer is not limited to the chemical vapor deposition method.

Next, an element isolation insulating region 19 is formed by a trench isolation method, and ion implantation for well formation is performed over the lower portion of the strained Si layer 1 and the Si _1-x Ge _x strain application layer 2. A V group element such as P is implanted into the lower portion of the PMOS region to be n-type, and a III group element such as B is implanted into the lower portion of the NMOS region to be p-type. Further, a threshold value is adjusted by implanting a group III element in the PMOS region and a group V element in the NMOS region above the strained Si layer 1.

Next, the surface of the strained Si layer 1 is thermally oxidized to form a SiO ₂ gate insulating film 3. Furthermore, after the polysilicon gate electrode 16 is formed thereon, portions other than the gate region are removed by etching. Further, a source / drain region is formed by ion implantation by self-alignment. At this time, if a group III element such as B is implanted, a p-type source / drain region 17 can be formed, and if a group V element such as P is implanted, an n-type source / drain region 18 can be formed. Can be made. At this time, in order to reduce the leakage current to the Si _1-x Ge _x strain application layer 2, the ion implantation depth was set to 30 nm, which is half or less of the thickness of the strain Si layer 1. Finally, an interlayer insulating film (not shown) is formed, contact holes are opened, a metal film such as Al is deposited, patterned, and metal wiring is formed, thereby completing a field effect transistor. This transistor has a transconductance of about 3 times and a cutoff frequency of 2.4 times that of a non-strained Si field-effect transistor fabricated directly on a Si substrate with the same dimensions.

(Example 2)
FIG. 8 is a cross-sectional view of the CMOSFET according to this embodiment. In this example, instead of increasing the depth of 30 nm of the source / drain regions 17 and 18 in Example 1 to 50 nm in the normal case, the upper 30 nm range is formed in the formation of the Si _1-x Ge _x strain application layer 2. in, a mixture of P doping gas, at a high concentration of 10 ¹⁸ per cubic centimeter, in which was sharply n-type doping. At this time, in order to perform doping only in the pMOS region, the nMOS region is covered with an oxide film and removed after doping.

  However, ion implantation for forming wells is not performed in the pMOS region subjected to steep doping.

  Also in this example, the same effects as in Example 1 were obtained with respect to the mutual conductance and the cutoff frequency.

(Example 3)
FIG. 9 is a cross-sectional view of the CMOSFET according to this embodiment. In this embodiment, a positive bias is applied to the well region of the pMOS instead of the steep doping in the second embodiment.

Specifically, a contact hole is opened to the pMOS Si _1-x Ge _x strain application layer 2 outside the element region, an ohmic electrode is formed therein, and the bias application electrode 22 is formed.

  By applying a voltage of +1 V to the bias application electrode 22, it was possible to reduce the punch-through current to 5% or less compared to the case of no bias application.

  In addition, the method of Example 1 thru | or 3 is a method which can be applied simultaneously, and can combine 2 types or 3 types.

Example 4
FIG. 10 is a cross-sectional view of the CMOSFET according to this embodiment. In the present embodiment, the drain region 15 of the p-type MOSFET and the source region 14 of the n-type MOSFET of the strained Si layer 1 in the first embodiment are selectively etched, and a Si _1-x Ge _x layer 23 is selectively grown on the portions. And then backfill. Note that the surface layer 5 nm of this portion is made of Si to prevent the Si _1-x Ge _x layer 23 from being damaged by subsequent processes.

  The transistor of this embodiment can reduce this compared to the operating voltage of 3 V often used in the conventional MOSFET.

(Example 5)
FIG. 11 is a cross-sectional view of the CMOSFET according to this embodiment. The feature of this embodiment is that the strained Ge _y layer is used as a PMOS channel.

A high defect density layer is formed in advance on the Si substrate 13 over a region of 100 nm from the surface by hydrogen ion implantation. After cleaning this substrate, it was immediately introduced into the chemical vapor deposition apparatus, and the lower layer 2 of the strain applying layer made of Si _1-x Ge _{x in which x} was changed from 0.3 to 0.5 in the growth direction. grow up. The film thickness is 300 nm. Si ₂ H ₆ and GeH ₄ are used as raw materials and grown at a growth temperature of 700 ° C.

Further, the upper layer 24 of the strain applying layer made of Si _0.5 Ge _{0.5 is} formed in the same manner in this order by forming a layer with a thickness of 30 nm, a strained Ge layer 25 with a thickness of 10 nm, and a strained Si layer 1 with a thickness of 13 nm. Note that the growth of the Si, Ge and SiGe layers is not limited to the chemical vapor deposition method, and any method capable of crystal growth of the above composition may be used. The strained Ge layer 25 receives in-plane compressive stress, and the strained Si layer 1 receives in-plane tensile stress. As a result, the effective mass of both the holes in the strained Ge layer 25 and the electrons in the strained Si layer 1 is reduced as compared with normal Si, and the mobility is increased.

Next, in the same manner as in Example 1, the element isolation insulating region 19 was formed, and the Si _0.5 Ge _0.5 layer 24 as the upper layer of the strain applying layer and the Si _1-x Ge _x layer 2 as the lower layer were covered. Well forming ion implantation and low concentration ion implantation for threshold adjustment are performed on the upper portion of the strained Si layer 1 and the upper portion of the strained Ge layer 25. Subsequently, the SiO ₂ gate oxide film 3, the gate electrode 16, and the source / drain regions 17 and 18 are formed. The ion implantation depth of the source / drain regions 17 and 18 is set to 10 nm, which is about the same as the thickness of the strained Si layer 1 for nMOS, and 20 nm reaching the strained Ge layer 25 for pMOS. Finally, an interlayer insulating film, contact holes, and metal wiring are formed to complete the CMOSFET.

In this embodiment, since the Si _0.5 Ge _0.5 layer 24 with x = 0.5 is grown as the upper layer of the strain applying layer, the amount of strain applied to the strained Si layer 1 and the strained Ge layer 25 is large.

In this embodiment, a strained Ge _y layer is used for the channel, but a strained Si _1-y Ge _y layer (0 <y <1) mixed with Si can also be used. In this case, the composition ratio y is made larger than the composition ratio x of the Si _1-x Ge _x strain application layer.

(Example 6)
FIG. 12 is a cross-sectional view of the CMOSFET according to this embodiment. In this example and Example 5, the Si _0.5 Ge _0.5 barrier layer 30 is formed to 2 nm on the strained Si layer 1.

Thus, since the Si _0.5 Ge _0.5 barrier layer 30 is provided between the strained Si layer 1 and the gate insulating film 3, electrons are not scattered at the interface between the strained Si layer 1 and the gate insulating film 3. , Accumulated in the strained Si layer 1 near the interface between the Si _0.5 Ge _0.5 barrier layer 30 and the strained Si layer 1.

  In this embodiment, the strained Si layer 1 is laminated on the strained Ge layer 25, but this order may be reversed. The ion implantation depth of the source / drain region 1718 is 12 nm, which is about the same as the thickness of the strained Si layer 1 for nMOS, and 22 nm reaching the strained Ge layer 25 for pMOS.

(Example 7)
FIG. 13 is a cross-sectional view of the CMOSFET according to this embodiment. In the present embodiment, the strained Si layer 1 and the strained Ge layer 25 in the fifth embodiment are arranged in parallel without being stacked.

Specifically, on the Si _0.5 Ge _0.5 strain applying layer 24, the strained Ge layer 25 is selectively grown in the pMOS region by 10 nm and the strained Si layer 1 is selectively grown by 12 nm in the nMOS region. The strained Ge layer 25 is subjected to in-plane compressive stress, and the strained Si layer 1 is subjected to in-plane tensile stress. As a result, the effective mass of both the holes in the strained Ge layer 25 and the electrons in the strained Si layer 1 is reduced as compared with normal Si, and the mobility is increased.

(Example 8)
FIG. 14 is a cross-sectional view of an SOI substrate according to this example. After cleaning the Si substrate 13 on which a high defect density epilayer having a thickness of 100 nm is formed on the surface, the Si substrate 13 is immediately introduced into a chemical vapor deposition apparatus to grow the Si _1-x Ge _x strain application layer 2. The film thickness is 150 nm. Si ₂ H ₆ and GeH ₄ are used as raw materials and grown at a growth temperature of 700 ° C. The Ge composition ratio x of the Si _1-x Ge _x strain application layer 2 can be controlled in any way, but in order to optimize the strain applied to the strain Si layer 1 to be formed later, x is set to 0. A good result is obtained with 2-0.4. In this embodiment, it is 0.3.
Note that the growth of the Si and SiGe layers is not limited to the chemical vapor deposition method, but may be any method that allows crystal growth of the above composition.

Next, oxygen ions are implanted from above the Si _1-x Ge _x strain application layer 2 under conditions of an acceleration voltage of 180 KeV and a dose of 4 × 10 ¹⁷ / cm ² , and annealing is performed at 1350 ° C. for 8 hours. As a result, the SiO ₂ insulating layer 26 is formed immediately below the Si _1-x Ge _x strain applying layer 2. The thickness of the SiO ₂ insulating layer 26 is approximately 100 nm, and a dielectric breakdown voltage of 50 V or more is ensured. By the annealing treatment, the Si _1-x Ge _x strain application layer 2 has a very low defect density, is flat, and is sufficiently strain-relieved. Further, a strained Si layer 1 having a thickness of 60 nm is formed thereon by chemical vapor deposition.

  Thereafter, the CMOSFET can be manufactured by using the same process as in the first embodiment of the invention. By using this substrate, ion implantation of the well layer becomes unnecessary.

  In addition, since the stray capacitance is greatly reduced, the operation speed at the mounting level can be increased by about 40% compared to the case of using a normal Si substrate.

Example 9
FIG. 15 is a cross-sectional view of another embodiment of an SOI substrate. _{Si 1-x} Ge _x after forming up to the strain applied layer _{2, Si 1-x} Ge _x chemical vapor deposition strained Si layer 1 having a thickness of 120nm on the strain applied layer 2 in the same manner as in Example 8 Form with. Next, oxygen ions are implanted from above the strained Si layer 1 under conditions of an acceleration voltage of 50 KeV and a dose of 2 × 10 ¹⁷ / cm ² , and annealing is performed at 1300 ° C. for 8 hours. Thereby, the SiO ₂ insulating layer 26 is formed inside the strained Si layer 1. The thickness of the SiO ₂ insulating layer 26 is about 30 nm.

  In this embodiment, the well layer does not need to be ion-implanted, and holes in the pMOS hardly flow out to the SiGe strain application layer. Therefore, it is particularly necessary to use a hole outflow prevention measure by doping or bias application. There is no.

(Example 10)
FIG. 16 is a cross-sectional view of an SOI substrate manufacturing process according to this example. First, as shown in FIG. 16A, after cleaning the Si substrate 13 on which a high defect density epilayer having a thickness of 100 nm is formed on the surface, the Si substrate 13 is immediately introduced into the chemical vapor deposition apparatus and Si _1-x Ge _x strain is obtained. The application layer 2 is grown. The film thickness is 300 nm. Si ₂ H ₆ and GeH ₄ are used as raw materials and grown at a growth temperature of 700 ° C. The Ge composition ratio x of the Si _1-x Ge _x strain application layer 2 can be controlled in any way, but in order to optimize the strain applied to the strain Si layer 1, x is set to 0.2-0. A result of 4 is good. In this embodiment, it is 0.3. Note that the growth of the Si and SiGe layers is not limited to the chemical vapor deposition method, but may be any method that allows crystal growth of the above composition. Further, instead of the Si substrate 13, a Ge substrate or a SiGe mixed crystal substrate may be used. When the mixed crystal ratio x of Ge is large, the growth of the Si _1-x Ge _x strain applying layer 2 becomes easier or unnecessary when using a Ge substrate or a SiGe substrate having a large Ge mixed crystal ratio.

Next, the strained Si layer 1 is grown, the surface is thermally oxidized, hydrogen ions are then implanted to the depth of the cutting position 28, and a damaged layer is formed at this position. Thus, the state shown in FIG. The cutting position 28 may be inside the Si _1-x Ge _x strain applying layer 2 or inside the strained Si layer 1.

Further, a support substrate 29 prepared separately from the oxide film on the surface is bonded at the bonding position 27, and a state as shown in FIG. Next, when annealing is performed at 500 ° C., cutting is performed at the cutting position 28, and when the cutting position 28 is inside the Si _1-x Ge _x strain application layer 2, the state is as shown in FIG. In this case, the state is as shown in FIG. In the case shown in FIG. 16C, a 60 nm strained Si layer 1 is further epitaxially grown on the surface.

  Thereafter, the CMOSFET can be manufactured by using the same process as in the first embodiment of the invention. By using this substrate, ion implantation of the well layer becomes unnecessary. Further, in the case of the structure of FIG. 16 (d), holes do not flow out to the SiGe strain application layer in the pMOS, so that a hole outflow prevention measure by doping, bias application, or the like becomes unnecessary.

  In addition, since the stray capacitance is greatly reduced, the operation speed at the mounting level can be increased by about 40% compared to the case of using a normal Si substrate.

(Example 11)
A complementary field effect transistor is manufactured by using the {100} -plane Si substrate 13 by changing the Ge composition ratio x of the Si _1-x Ge _x strain applying layer 2 in various ways by the method shown in the first embodiment. When the mobility of electrons and holes in the <001> direction in the strained Si channel is estimated from the mutual conductance, as shown in Table 1, the increase in mobility is considerably large even when the mixed crystal ratio is about 0.2.
Units are% strain (positive value is tensile strain) and mobility is cm ² / Vs.
Table 1
Ge composition ratio x strain Electron mobility Hole mobility
0 0 1300 400
0.1 0.4 2600 850
0.2 0.8 3300 2000
0.3 1.2 3550 3100
0.4 1.6 3500 4500
0.5 2.0 3450 5200
0.6 2.4 3400 6100
Using the method shown in Example 7, a pMOSFET was produced using a {100} -plane Si substrate 13 by changing the Ge composition ratio x of the Si _1-x Ge _x strain applying layer 2 in various ways. When the mobility of holes in the <001> direction in the strained Ge channel is estimated, as shown in Table 2, the mobility increases dramatically as it receives in-plane compressive strain. Units are% strain (positive value is tensile strain) and mobility is cm ² / Vs.
Table 2
Ge composition ratio x strain Hole mobility
1.0 0 1900
0.9 -0.4 2800
0.8 -0.8 4100
0.7 -1.2 7000
0.6 -1.6 9000
0.5 -2.0 12000
0.4 -2.4 13500
A complementary field effect transistor is fabricated using the {110} -plane Si substrate 13 by the method shown in Example 1, and electrons in the <001> direction and the <110> direction in the strained Si channel are determined from the mutual conductance of the element. When the mobility of holes and holes is estimated, as shown in Table 3, the electron mobility is larger in the <110> direction. Units are% strain (positive value is tensile strain) and mobility is cm ² / Vs.
Table 3
Ge composition ratio x Strain orientation Electron mobility Hole mobility
0.2 0.8 <001> 900 1800
0.2 0.8 <110> 3100 1800
0.3 1.2 <001> 900 2700
0.3 1.2 <110> 3300 2700

1 ... strained Si layer, 2 _{... Si 1-x} Ge _x strained applied layer, 3 ... SiO ₂ gate insulating layer, 4 ... conduction band, 5 ... valence band, the band gap of 6 ... strained Si, 7 ... _{Si 1- x} Ge _x band gap, 8 ... conduction band discontinuity, 9 ... valence band ... discontinuity, 10 ... triangular well of conduction band in the strained Si layer near the gate insulating film / strained Si layer interface, 11 ... gate insulation film / strained Si layer triangular wells of the valence band of the strained Si layer in the vicinity of the interface, 12 ... strained Si layer _{/ Si 1-x} Ge _x of the strain applied layer near the interface _{Si 1-x} Ge _x strain applied layers 2 Valence band triangular well, 13 ... Si substrate, 14 ... source electrode, 15 ... drain electrode, 16 ... gate, 17 ... p-type source / drain region, 18 ... n-type source / drain region, 19 ... element isolation insulating region, 20 ... strained Si layer / strained _{Si 1-y} Ge strain of _y layer near the interface _{Si 1-y} Ge Valence band triangular well in _y layer, 21 ... steep n-type doping layer, 22 ... bias application electrode, 23 ... Si _1-x Ge _x drain layer, 24 ... Si _0.5 Ge _0.5 layer, 25 ... strained _{Si 1-y} Ge _y layer (0 <y ≦ 1), 26 ... SiO 2 insulating layer, 27 ... joining position, 28 ... cutting position, 29 ... supporting _{substrate, 30 ...} Si 0.5 _{Ge 0.5} barrier layer , 40, 41 ... vertex of the triangular well in the conduction band, 42, 43 ... vertex of the triangular well in the valence band.

Claims (7)

A Si layer;
A gate electrode of a MOSFET formed on the Si layer;
A source region and a drain region of the MOSFET formed in the Si layer;
A method for manufacturing a semiconductor device, comprising: a region between the source region and the drain region, and a channel region in which a channel is formed under the gate electrode during the operation of the MOSFET,
(A) forming a groove in the Si layer by selectively etching the region where the source region or the drain region is formed;
(B) filling the groove by selectively growing SiGe;
Distortion occurs in the channel region,
The method of manufacturing a semiconductor device, wherein the mobility of carriers in the channel region is larger than that in the case where the channel region is undistorted. A Si layer;
A gate electrode of a MOSFET formed on the Si layer;
A source region and a drain region of the MOSFET formed in the Si layer;
A method for manufacturing a semiconductor device, comprising: a region between the source region and the drain region, and a channel region in which a channel is formed under the gate electrode during the operation of the MOSFET,
(A) forming a groove in the Si layer by selectively etching the region where the source region or the drain region is formed;
(B) filling the groove by selectively growing SiGe;
Distortion occurs in the channel region,
A method of manufacturing a semiconductor device, wherein a lattice constant of Si in the channel region is larger than a lattice constant of unstrained Si. In the manufacturing method of the semiconductor device according to claim 1 or 2,
A method of manufacturing a semiconductor device, wherein a SiGe layer is formed under the Si layer. In the manufacturing method of the semiconductor device according to claim 3,
The SiGe layer formed under the Si layer is made of Si _1-x Ge _x (0 <x <1). In the manufacturing method of the semiconductor device of any one of Claims 1 thru / or 4,
A method of manufacturing a semiconductor device, wherein a Si film is formed on a surface of SiGe embedded in the groove. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The MOSFET is an n-type MOSFET,
The method of manufacturing a semiconductor device, wherein the SiGe buried in the trench is formed in the source region. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The MOSFET is a p-type MOSFET,
The method of manufacturing a semiconductor device, wherein the SiGe buried in the trench is formed in the drain region.

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