KR19980024649A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

In order to provide a semiconductor device having a field effect transistor having a high carrier mobility and a channel with few crystal defects, in the NMOS transistor on the Si substrate 10, the Si layer 13n and the SiGeC layer 14n are Formed. The carrier accumulation layer using the discontinuity of the conduction band existing in the hetero interface between the SiGeC layer 14n and the Si layer 13n is formed, and electrons travel as the channel, and the SiGeC layer 14n is formed of silicon. The mobility of electrons and the operating speed of the NMOS transistor are also increased compared to the channel, and the channel through which the hole of the PM0S transistor travels is formed by using discontinuities in the valence band generated at the interface between the SiGe layer 15p and the Si layer 17p. Since the SiGe layer is formed, the mobility of holes is larger than that of the Si layer, and the operation speed of the PMOS transistor is also increased.

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, to a semiconductor device having a heterojunction field effect transistor using a SiGeC layer or a SiGe layer and a method of manufacturing the same.

In recent years, high integration of semiconductor devices has progressed. However, in the ultrafine region in which the micronization gate length of the M0S-type transistor is less than 0.1 µm, the current driving capability is saturated due to the effect of a short channel effect or an increase in resistance component. It is expected that such a performance improvement cannot be expected. In particular, in order to increase the driving force of the fine M0S transistor, it is important to improve the carrier mobility of the channel and to reduce the resistance of the contact of the source and drain electrodes.

Therefore, instead of the complementary semiconductor device (CMOS device) using a single composition of Si formed on a silicon substrate, a heterostructure CMOS device (Heterostructure CMOS: hereinafter referred to as HCMOS device) by Si / SiGe system (Group IV mixed crystal) Is proposed. This is not the Si / SiO2 interface but the interface of the heterojunction by two kinds of semiconductors having different band gaps as the channel. It is expected that even higher speed devices can be realized by using a Si / SiGe system that gives higher carrier mobility than such Si. In this Si / SiGe system, it is possible to form an epitaxial growth layer having a desired amount of distortion and a band value on the Si substrate by controlling the composition. Ismail of IBM performs basic experiments on the improvement of characteristics by Si / SiGe-based HCMOS devices (K. Ismail, Si / SiGe High Speed Field-Effect Transistors, IEDM Tech. Dig. 1995. p509. And MA Armstrong) et al, Design of Si / SiGe Hetrojunction Complementary Metal-Oxide-Semiconductor Transistors (IEDM Tech.Dig. 1995, p701).

15 is a cross-sectional view showing an example of this HCMOS device. As shown in FIG. 15, a part of the Si substrate 101 is provided with a field effect transistor composed of a source / drain region 109, a gate insulating film 107, and a gate electrode 110 thereon. In the so-called channel region between the source region and the drain region under the gate electrode 110, the SiGe buffer layer 102, the δ doping layer 115, the space layer 103, and the i-Si layer ( 104, an i-SiGe layer 105 and an i-Si layer 106 are formed. In these regions, the SiGe buffer layer 102 is formed on the i-Si layer 104 to form an n-channel layer 112 between the i-Si layer 104 and the i-SiGe layer 105. It gives tensile distortion. In this SiGe buffer layer 102, the composition ratio is changed in stages so that the Ge composition ratio becomes 0% immediately above the Si substrate 101, and the Ge composition ratio becomes 30% at the top.

Here, when the negative bias is applied, the n-channel layer 112 is formed at the hetero interface with the SiGe buffer layer 102 below in the i-Si layer 104. The δ doping layer 115 supplies electrons as carriers to the n-channel layer 112 formed thereon. In addition, the space layer 103 spatially separates the ions of the δ doped layer 115 formed downward and the upper n-channel layer 112 to prevent a decrease in mobility due to ion scattering of the carrier. .

Further, when a positive bias is applied, the p-channel layer 111 is formed in the hetero interface with the i-Si layer 106 in the i-SiGe layer 105 above. The gate insulating film 107 is for insulating the gate electrode 110 and the p-channel layer 111.

As described above, in the hetero field effect transistor, a channel is formed in a hetero interface between two kinds of semiconductor layers having different band gaps. Thus, there are at least two semiconductor layers that inevitably differ in band gap for channel formation. In addition, in order to form a channel for moving electrons or holes at high speed in the semiconductor layer, it is necessary to have discontinuities in the conduction band or the valence band at the hetero interface. In the above-described Si / SiGe system, since the SiGe layer 105 has a discontinuity in the valence band with respect to the i-Si layer 106 with respect to the holes, a channel for holes is formed (see the left part of FIG. 15). ). However, since there are few discontinuities in the conduction band, by applying tensile distortion to the i-Si layer 104 to form channels for electrons, discontinuities in the conduction band are formed at the hetero interface with the i-SiGe layer 105. (See right side of FIG. 15).

From the results of the simulation, HCMOS devices having such a structure can realize twice the high-speed operation with 1/2 the power consumption with the same processing dimensions as compared to the conventional CMOS devices using the channel based on Si / Si02. It is expected. That is, a semiconductor device in which a hetero interface is formed by combining a Si semiconductor and a SiGe mixed crystal to form a high mobility channel, which realizes both high-speed operation of a device using a heterojunction and large scale integration of a M0S device. It is very attracting attention.

However, hetero-devices using group IV mixed crystals such as SiGe as described above are greatly expected as a method of overcoming the performance limitations of conventional CM0S devices, but hetero-field effect transistors using group IV mixed crystals represented by SiGe are In comparison with the heterobipolar transistor which is a hetero device using the same SiGe mixed crystal, the research and development are delayed due to the difficulty in manufacturing the same, and the structure and the manufacturing method are sufficiently studied to sufficiently exhibit the expected performance. Can not. In addition, among the hetero field effect transistors, in the case of the so-called hetero MOS structure having an insulating film between the gate electrode and the semiconductor layer as described above, since a good insulating film can be formed in the SiGe layer with good stability, the gate insulating film is made of SiO 2. An oxide film is used. Therefore, the Si layer must be immediately below the gate insulating film, but Si has a feature that the band gap is larger than that of SiGe.

Therefore, in the structure of the said conventional HCMOS apparatus, there existed the following problems.

First, in order to form an electron channel on the Si substrate 101 as described above, tensile distortion is applied to the i-Si layer 104 to form a band discontinuity on the Si / SiGe hetero interface. However, changing the lattice constant entails introducing a potential by lattice relaxation.

FIG. 16 is a cross-sectional view illustrating an SiGe buffer layer 102 and an i-Si layer 104 thereon. Since the i-Si layer 104 has a smaller lattice constant than the SiGe buffer layer 102, tensile strain is accumulated in the crystal growth step. As the accumulation of this distortion increases, a potential is input to the i-Si layer 104 as shown in FIG. As such, the introduction of dislocations or defects due to lattice mismatch distortion between the i-Si layer 104 and the SiGe buffer layer 102 is unavoidable. Therefore, the initial characteristic of the element using this crystal is considered to have the effect of deterioration of characteristics due to dislocation propagation from the viewpoint of reliability and lifetime.

The SiGe buffer layer 102 made of SiGe having a lattice constant larger than Si is laminated on the Si substrate 110, and the tensile strain is laminated on the i-Si layer 104 growing thereon, but the SiGe buffer layer 102 is formed. ), The lattice constant of the SiGe buffer layer 102 exceeds the critical film thickness that changes from the lattice constant of Si to the lattice constant of the original SiGe in the meantime, so that lattice relaxation occurs and the SiGe buffer layer 102 ), Defects such as dislocations are also introduced.

Although these defects may have little influence on the initial characteristics of the device, they may cause serious problems in terms of long-term reliability and lifetime. That is, there is a fear that the proliferation of defects caused by current or the deterioration due to diffusion through defects of metals or impurities may occur, resulting in a decrease in reliability.

The first object of the present invention is the mobility of carriers by using lattice match or near lattice matched heterojunctions with band discontinuities capable of forming a carrier accumulation layer as a structure across the channel region under the gate of the HCMOS device. The present invention provides a semiconductor device with high reliability and high reliability.

Secondly, the hetero field effect device using the group IV mixed crystal represented by SiGe is an effective technique as an element structure that overcomes the performance limitation of the conventional fine CM0S device. Examination of optimization of the contact of an electrode is further inadequate, and it does not become a structure which fully utilizes the high mobility. Although the above-described technology of the hetero CMOS device by IBM Corp. has been examined in detail in improving the mobility of the channel region, the contact resistance of the source and drain electrodes, which is another important factor for improving the performance of the fine transistor, has been reduced. There is hardly any examination.

That is, in the CM0S device structure using Si single crystal, various studies have been made in the structure of the contact area on the substrate side connected to the source and drain electrodes, but the structure of the optimal contact area in the general CM0S device and It is necessary to examine whether the formation method is the best even for heterofield effect devices having different device structures.

It is a second object of the present invention to provide a semiconductor device having a contact region capable of exerting a small contact resistance without impairing the excellent properties of the heterofield effector, and a manufacturing method thereof.

1 is a cross-sectional view showing the structure of an SiGeC-based HCMOS device according to a first embodiment of the present invention.

FIG. 2 illustrates the dependence of the Ge and C composition rates on the lattice distortion of SiGeC layers in HCMOS devices.

FIG. 3 is a diagram showing a relationship between the composition ratios of Si, Ge, and C, which generate lattice matching or tensile distortion between the SiCeC layer and the Si layer of the SiGeC-based HCMOS device.

4 shows the relationship between the C composition ratio and the energy gap value of the SiGeC layer.

Fig. 5 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

Fig. 6 is a diagram showing the relationship between the composition of the SiGeC layer and the distortion due to lattice mismatch in the second embodiment of the present invention.

FIG. 7 is a diagram showing a band-up of a lattice matching system SiGeC-HCMOS device according to a second embodiment of the present invention. FIG.

Fig. 8 is a sectional view showing the structure of an HCMOS device having a channel of a quantum well structure according to a third embodiment of the present invention.

Fig. 9 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

Fig. 10 is a sectional view showing the structure of an HCMOS device according to a fourth embodiment of the present invention.

Fig. 11 is a sectional view showing a first half portion in a manufacturing process of an HCMOS device according to a fourth embodiment of the present invention.

12 is a cross-sectional view showing a second half part in the manufacturing process of the HCMOS device according to the fourth embodiment of the present invention.

Fig. 13 is a sectional view showing the structure of an HCMOS device according to a fifth embodiment of the present invention.

Fig. 14 is a sectional view showing the structure of an HCMOS device according to a sixth embodiment of the present invention.

15 is a cross-sectional view showing the structure of a conventional HCMOS device.

Fig. 16 shows a defect such as potential due to lattice mismatch introduced into a hetero interface of a conventional HCMOS device.

* Explanation of symbols indicating major parts of drawing *

10, 30, 50: Si substrate 11, 31, 51n: p hole

12, 32, 51p: n hole 13: Si layer

14, 34: SiGeC layer 15, 36: SiGe layer

16 source and drain regions 17 Si layer

18, 38, 65: gate electrode 19, 39, 58: gate insulating film

21 and 41: source and drain electrodes 25, 45 and 61: source and drain contact W layers

33: first Si layer 35: second Si layer

37: third Si layer 42, 49: source / drain region

52 SiGe buffer layer 53 δ doped layer

54: space layer 55, 57: i-Si layer

56: i-Si _lx Ge _x layer 63: Al source-drain electrode

66 first layer insulating film 67 n-channel

68: p-channel

In order to achieve the said 1st object, in this invention, the means regarding the 1st semiconductor device of Claims 1-16, the means regarding the 2nd semiconductor device of Claims 17-29, and Claim 33 Means relating to the method for manufacturing the first semiconductor device described are devised.

MEANS TO SOLVE THE PROBLEM In order to achieve the said 2nd objective, in this invention, the means regarding the 3rd semiconductor device of Claims 30-32, and the means regarding the manufacturing method of the 2nd semiconductor device of Claims 34-37 are calculated | required. Doing.

A first semiconductor device of the present invention, as described in claim 1, includes a field effect transistor formed in a part of a semiconductor substrate and having a channel region between a gate electrode and a source / drain region and a corresponding source / drain region. A semiconductor device comprising: a Si layer and a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0y ≦ 1) formed in contact with the Si layer and having a composition ratio y of 0.01 to 0.03 in the channel region; The carrier accumulation layer is provided in the region adjacent to the Si layer in the Si _1-xy Ge _x C _y layer.

Accordingly, a band discontinuity for forming a carrier accumulation layer for confining the carrier two-dimensionally is formed at the interface between the Si _1-xy Ge _x C _y layer and the Si layer having a composition ratio y of 0 to 0.01 to 0.03. It is possible. And since this carrier accumulation layer functions as a channel, the field effect transistor with a large operation speed which makes a channel the Si _1-xy Ge _{x Cy} layer which gives carrier mobility larger than a Si layer can be obtained. Moreover, Si _1-xy Ge _x C _y layer and in between the Si layer because it can be controlled such that no lattice mismatch or or extremely small, it is possible to adjust the lattice strain of 0 or nearly so, Si _1-xy Ge _x C _y It is possible to configure so that crystal defects may not be introduced into the layer. Therefore, a semiconductor device having high reliability can be obtained.

As described in claim 2, it can be placed to adjust the composition ratio of the Si _1-xy Ge _x C _y each element of the layer, with the composition ratio of the lattice matching said Si _1-xy Ge _x C _y layer and the Si layer.

As a result, a channel is formed in the Si _1-xy Ge _x C _y layer without distortion due to lattice mismatch, and thus a semiconductor device having very high reliability can be obtained.

As described in claim 3, the Si _1-xy Ge _x C _y layer may have a film thickness that is smaller than that of the Si layer and that no lattice relaxation occurs.

Accordingly, in order to apply tensile distortion to the Si _1-xy Ge _x C _y layer, the amount of discontinuity of the band with the Si layer can be increased, thereby improving the closing efficiency of the carrier.

As described in claim 4, the semiconductor substrate may further include a M0S transistor formed on the semiconductor substrate and having a single layer semiconductor layer as a channel region.

As described in Claims 5 and 6, carriers accumulated in the carrier storage layer can be negative carriers.

As described in Claims 7-9, it is preferable to provide the carrier supply layer for supplying a carrier to the said carrier storage layer in the area | region adjacent to the said Si _1-xy Ge _x C _y layer in the said Si layer.

As described in claim 10, a carrier accumulated in the carrier storage layer is a negative carrier, and is formed on the other part of the semiconductor substrate and has a channel region between the gate electrode and the source / drain region and the source / drain region. Two field effect transistors are further provided, and a second Si layer and a SiGe layer formed adjacent to the second Si layer are provided in the channel region of the another field effect transistor, and the second in the SiGe is provided. It is preferable to form a second carrier storage layer for accumulating positive carriers in a region adjacent to the Si layer.

Thereby, a semiconductor device functioning as an HCMOS device having high carrier movement can be obtained in either of the n-channel side and the p-channel side.

As described in claim 11, the Si _1-xy Ge _x C _y layer can be a quantum well region.

As described in claim 12, the SiGe layer can be a quantum well region.

According to claim 11 or 12, it is possible to obtain a field effect transistor having a channel with a high closing efficiency of the carrier.

As described in Claims 13 to 16, a first semiconductor layer and a second semiconductor layer having a band gap larger than that of the first semiconductor layer are provided in the source / drain region, and a low layer formed directly on the first semiconductor layer. A source / drain contact layer made of a conductor film of resistance can be provided.

Thereby, the semiconductor device with a small contact resistance can be obtained in addition to the effect of each claim, using a heterojunction.

The second semiconductor device of the present invention, as described in claim 17, includes a field effect transistor formed in a part of a semiconductor substrate and having a gate electrode, a source region and a drain region, and a channel region between the source and drain regions, The channel region includes a first Si layer, a first Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0y ≦ 1) formed in contact with the Si layer, a second Si layer, and the second Si. is formed in contact with said first layer to install the Si _1-xy Ge _x C _y layer and has claim _{2 Si 1-xy Ge x C} y layer (0≤x≤1, 0≤y≤1) having different band gap It is, is from the first Si _1-xy Ge _x C _y with the first region close to the Si layer of the inside layer, the second Si and the second area close to the Si layer in the _1-xy Ge _x C _y layer First and second carrier accumulation layers for closing carriers of different conductivity types are formed, respectively.

As a result, it is possible to obtain a semiconductor device which functions as an HCMOS device each having a channel having a high closing efficiency of a carrier and having a large operation speed and an n-channel field effect transistor and a p-channel field effect transistor. Furthermore, crystallization defects in the first Si _1-xy Ge _x C _y layer can be controlled such that there is no lattice mismatch or very little between the first Si _1-xy Ge _x C _y layer and the first Si layer. It is possible to configure so that it is not introduced. Therefore, a semiconductor device having high reliability can be obtained.

As described in Claim 18, the composition ratio y of C in the said 2nd Si _1-xy Ge _x C _y layer can be made into zero.

As described in claim 9, a M0S transistor may be further formed on the semiconductor substrate, the semiconductor layer having a single composition as a channel region.

Accordingly, a transistor having the first Si _1-xy Ge _x C _y layer as a channel region is disposed in a portion where an operation speed is required, and a general M0S transistor is disposed in a portion other than the above, thereby limiting the application range of the semiconductor device. You can enlarge it.

As described in Claim 20, it is preferable to make composition ratio y of C in said 1st Si _1-xy Ge _x C _y layer into 0.01-0.03.

As described in Claim 21, wherein the _{1 Si 1-xy Ge x C} y layer to adjust the composition ratio of the elements in the first _{1 Si 1-xy Ge x C} y layer and the composition ratio of the lattice matching the claim 1 Si layer It is desirable to do so.

As a result, a semiconductor device having a highly reliable field effect transistor without lattice distortion can be obtained.

As described in claim 22, the first Si _1-xy Ge _x C _y layer may have a lattice constant smaller than the lattice constant of the first Si layer and a film thickness that does not cause lattice relaxation.

Accordingly, since tensile strain is applied to the first Si _1-xy Ge _x C _y layer, the amount of band discontinuity between the first Si layer and the first Si layer can be increased, thereby improving the closing efficiency of the carrier.

As described in Claim 23, it is preferable that the carrier accumulate | stored in a said 1st carrier storage layer is made into a negative carrier, and the carrier accumulate | stored in a said 2nd carrier storage layer is made into a positive carrier.

As described in claims 24 and 25, a carrier supply layer for supplying a carrier to the first carrier accumulation layer in a region proximate to the first Si _1-xy Ge _x C _y layer in the first Si layer It is preferable to form.

As described in claim 26, it is preferable that at least one Si _1-xy Ge _x C _y layer in the first and second Si _1-xy Ge _x C _y layers be a quantum well region.

27. A source comprising a low resistance conductor film formed directly on a Si _1-xy Ge _x C _y layer formed above _{one of} the first and second Si _1-xy Ge _x C _y layers, as described in claims 27 to 29 _; It is preferable to further provide a drain contact layer.

A third semiconductor device of the present invention is a semiconductor device having at least one field effect transistor formed on a semiconductor substrate as described in claim 30, wherein the field effect transistor comprises a Si _1-xy Ge _x C _y layer ( A first semiconductor layer comprising 0 ≦ X ≦ 1,0 ≦ y ≦ 1), between a second semiconductor layer formed of a semiconductor having a band gap different from that of the first semiconductor layer, and the first and second semiconductor layers A source region having a channel region having a carrier accumulation layer formed in a region near an interface of the semiconductor layer, a source semiconductor region having a third semiconductor layer and a fourth semiconductor layer composed of a semiconductor layer having a larger band gap than the third semiconductor layer, A source / drain contact layer made of a low resistance conductor film formed directly on the three semiconductor layers is provided.

As a result, it is possible to reduce the contact resistance to the source / drain region in the field effect transistor having a high carrier speed, which is high in carrier movement using a heterojunction.

As described in Claim 31, the said 1st semiconductor layer and the said 3rd semiconductor layer are formed with a common 1st semiconductor film, and the said 2nd semiconductor layer and the said 4th semiconductor layer are made of a common 2nd semiconductor film. And the second semiconductor film may be formed on the first semiconductor film.

The semiconductor layer of claim 32, wherein the first semiconductor layer and the third semiconductor layer are formed of different semiconductor films, the third semiconductor layer is formed above the first semiconductor layer, and the fourth semiconductor layer is formed. May be formed on the third semiconductor layer.

The manufacturing method of the 1st semiconductor device of this invention is a manufacturing method of the semiconductor device which has an n-channel field effect transistor and a p-channel field effect transistor as described in Claim 33, Comprising: A 1st semiconductor device is manufactured on a semiconductor substrate. A first Si _1-xy Ge _x C _y layer having a Si layer and a first carrier layer in contact with the Si layer and adjacent to the first Si layer as a channel of the n-channel field effect transistor ( A first process of forming 0 ≦ x ≦ 1,0y ≦ 1), a second Si layer on the semiconductor substrate, the first Si _1-xy Ge _x C _y layer in contact with the second Si layer, and Has a second band gap and has a second Si _1-xy Ge _x C _y layer (0≤x) having a second carrier storage layer in the region proximate to the second Si layer to become a channel of the p-channel field effect transistor. ≤ 1, 0 ≤ _y ≤ _{1), and} Si _1-x located above the first and second Si _1-xy Ge _x C _y layers a third process of depositing a conductor film on the _y Ge _x C _y layer and patterning the semiconductor film to form gate electrodes of the n-channel field effect transistor and the p-channel field effect transistor, respectively; N-type impurities are accumulated in the n-channel field effect transistor formation region at least to the depth reaching the first carrier layer, and at least the second carrier is accumulated in the p-channel field effect transistor formation region using the gate electrode of the mask as a mask. A p-type impurity is introduced to a depth reaching the layer, and a fourth step of forming source and drain regions of the n-channel field effect transistor and the p-channel field effect transistor is provided.

By this method, the semiconductor device having the structure of claim 17 can be easily formed.

A method for manufacturing a second semiconductor device of the present invention, as described in claim 34, includes a first semiconductor layer comprising a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1); The semiconductor which has a 2nd semiconductor layer which has a band gap different from a said 1st semiconductor layer, and the carrier accumulation layer used as a channel formed in the area | region near the interface between the said 1st, 2nd semiconductor layer, and functions as a field effect transistor. A device manufacturing method comprising: a first step of sequentially forming a third semiconductor layer and a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer in the field effect transistor formation region of the semiconductor substrate; and the fourth semiconductor layer Depositing a semiconductor film on the upper side of the semiconductor film, patterning the conductor film to form a gate electrode, and reaching the carrier storage layer at least in the field-effect transistor formation regions located on both sides of the gate electrode. Is a third process of introducing impurities to a depth to form source and drain regions, and a fourth process of removing the fourth semiconductor layer in the source and drain regions by etching until at least the third semiconductor layer is exposed. And a fifth step of forming a source / drain contact layer made of a low resistance conductor film on the surface where the third semiconductor layer is exposed.

By this method, the semiconductor device having the structure of claim 30 can be easily formed.

As described in Claim 35, the said 1st process can form the said 1st and 3rd semiconductor layer as a common 1st semiconductor film, and can form the said 2nd and 4th semiconductor layer as a common 2nd semiconductor film. have.

As described in Claim 36, further including the process of forming a said 1st and 2nd semiconductor layer before a said 1st process, The said 1st process provides a 3rd semiconductor layer above a said 1st semiconductor layer. Can be formed.

As described in Claim 37, it is preferable to set the said 4th process as the etching conditions with high etching selectivity with respect to the said 3rd semiconductor layer and the said 4th semiconductor layer.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

(Example)

(First embodiment)

In the HCMOS device according to the first embodiment, the SiGeC layer and the Si layer are almost lattice matched by using a SiGeC ternary mixed crystal system in which C is added to the SiGe / Si system, and the hetero boundary surface from the difference in the band gap energy. It is a field effect transistor which forms a band discontinuity in.

1 is a cross-sectional view showing the structure of the HCMOS device according to the first embodiment. As shown in FIG. 1, an NMOS transistor and a PMOS transistor are formed on the silicon substrate 10, but first, the structure of the NMOS transistor will be described.

In an NMOS transistor, a Si layer having a p-hole 11 (a high concentration p-type silicon layer) formed on the Si substrate 10 and having a δ doping layer and a space layer doped with a high concentration of the group V element thereon ( 13n) and a SiGeC layer 14n (the composition ratio of C is 1%, and the composition ratio of Ge is 8.2%) are formed in this order. As will be described later, the composition ratio of each element in the SiGeC layer 14n is a value at which the SiGeC layer 14n and the Si layer 13n beneath it are lattice matched.

At the hetero interface between the SiGeC layer 14n and the Si layer 13n, a band discontinuity of the conduction band Ec having the band offset value ΔEc exists as shown in the right part of FIG. 1, and the band discontinuity is a negative carrier. A carrier accumulation layer is formed for closing electrons as two-dimensional electron gas 2 DEG. The carrier accumulation layer formed near the boundary surface on the SiGeC layer 14n side is a channel through which electrons travel at high speed. In the SiGeC layer 14n, the mobility of electrons is larger than that in the Si layer, and the operating speed of the NMOS transistor can be increased.

On this SiGeC layer 14n, a SiGe layer 15n (a composition ratio of Ge is 30%, a composition ratio of Si is 70%), and a Si layer 17n are formed in this order, and a silicon oxide film is formed on the surface thereof. A gate insulating film 19n is formed. Since the Si layer 17n exists under this gate insulating film 19n, the gate insulating film 19n with high crystallinity can be easily formed only by oxidizing the surface of the Si layer 17n. The gate electrode 18n is formed on the gate insulating film 19n, and the source / drain layer 16n is formed in the board | substrate located on both sides of this gate electrode 18n. The travel of electrons in the SiGeC layer 14n is controlled by the voltage applied to the gate electrode 18n. Moreover, although the source-drain layer 16n is formed to the depth which reaches | attains the p-hole 11, what is necessary is just to form at least to the depth of the part used as the channel formed in the SiGeC layer 14n.

On the other hand, the PMOS transistor has a structure substantially the same as that of the NMOS transistor described above. An n-hole 12 (high-strength n-type Si layer) is formed on the Si substrate 10, and thereon, an Si layer 13p having a δ doped layer doped with a high concentration of group V elements, and a SiGeC layer ( 14p) (The composition ratio of Ge is 8.2%, and the composition ratio of C is 1%) in that order. On this SiGeC layer 14p, a SiGe layer 15p (a composition ratio of Ge is 30%, a composition ratio of Si is 70%), and a Si layer 17p are formed in this order. In the case of a PMOS transistor, the carrier becomes a hole, but the channel through which the hole flows is formed on the SiGe layer 15p side of the interface between the SiGe layer 15p and the Si layer 17p. A band discontinuity in the valence band having a band offset value ΔEv exists in the hetero interface between the SiGe layer 15p and the Si layer 17p, and a carrier layer is formed in this discontinuous portion. Therefore, although holes travel through the carrier accumulation layer channel formed at the interface on the SiGe layer 15p side, the mobility of the PM0S transistor also increases because the mobility of holes is larger in the SiGe layer 15p than in the Si layer.

In the PMOS transistor, a gate insulating film 19p made of a silicon oxide film is formed on the Si layer 17p. Source and drain layers 16p are formed on both sides of the gate electrode 18p, and the travel of the holes in the SiGe layer 15p is controlled by the voltage applied to the gate electrode 18p.

In addition, a trench isolation 20 is formed between the NMOS transistor and the PMOS transistor by filling a groove formed in the substrate with a silicon oxide film. By the trench isolation 20, the NMOS transistor and the PMOS transistor are separated from each other. Are electrically separated from each other.

In addition, each Si layer 13n, 13p, each SiGeC layer 14p, 14n, each SiGe layer 15n, 15p, and each Si layer 17n, 17p are formed simultaneously by crystal growth, respectively. In addition, the dimension of each layer can be made into the following dimensions, for example. However, it is not necessarily limited to the following dimensions.

The thickness of each Si layer 13n, 13p is about 0.6 micrometer, for example, and it is preferable to exist in the range of 0-1 micrometer. The thickness of the space layer is, for example, about 30 nm, and preferably in the range of 0 to 50 nm. It is preferable that the thickness of each SiGeC layer 14p, 14n is 3-50 nm. The thickness of each SiGe layer 15n, 15p is about 5 nm, and it is preferable to exist in the range of 3-5 nm. The thickness of each Si layer 17n, 17p is about 1 nm, and it is preferable to exist in the range of 0.5-5 nm. The thickness of the gate insulating films 19n and 19p is, for example, about 5 nm.

The gate lengths of the gate electrodes 18n and 18p are 0.25 μm, the gate width is 2.5 μm, and the width of the source and drain regions is about 1.2 μm. The contact area of the source and drain electrodes 21n and 21p is 0.5 μm. X 0.6 μm or so. The doping concentration of each hole 13n, 13p is about 1 * 10 <^{17> -1} * 10 <^18> cm <^-3> , and the doping concentration of the (delta) doping layer is about 1 * 10 <^{18> -1} * 10 <^20> cm <^-3> .

The characteristic of the HCMOS device (HeterostructureCMOS device) in this embodiment is that a SiGeC layer is used. This SiGeC layer can change the lattice mismatch rate with respect to a band gap layer and silicon by adjustment of each composition ratio of Si, Ge, and C. As shown in FIG. Here, the relationship between the composition ratio of Si, Ge, and C in the present embodiment, and the amount of distortion and band offset of each layer will be described in detail.

FIG. 2 shows that the SiGeC layer and the Si layer change the lattice mismatch rate (%) when the composition ratio (%) of C (carbon) on the horizontal axis and the Ge ratio (%) on the vertical axis are taken. have. A line with a mismatch ratio of zero indicates that the lattice constants of the SiGeC layer and the Si layer are the same. Since the lattice constant of the Ge (germanium) single crystal is larger than the lattice constant of the Si single crystal, and the lattice constant of the C (carbon) single crystal is smaller than the lattice constant of the Si single crystal, the lattice of the SiGeC layer 14n is adjusted by adjusting the composition ratio of Ge and C. The constant and lattice constant of the Si layer 13n can be matched.

Fig. 3 is a characteristic diagram showing the relationship of lattice matching to the composition ratio of three elements of Si, Ge, and C. The three vertices of FIG. 3 are points at which the composition ratio of Si, Ge, and C is 100% (composition ratio 1), and the lattice mismatch rate with Si is changed by adjusting the composition ratio of the ternary mixed crystal system of the SiGeC layer. Is showing. In Fig. 3, the hatching region shows the region of the composition ratio giving tensile strain to the SiGeC layer, and the solid line in Fig. 3 shows the conditions of the composition ratio of each element for lattice matching between the SiGeC layer and the Si layer. Since the lattice constant of Ge is 4.2% larger than the lattice constant of Si and the lattice constant of C is 34.3% smaller than the lattice constant of Si, the lattice constant of the SiGeC layer is increased by 8.2 times larger than that of C. Can match the grid constant.

In the SiGeC layer 14n according to the present embodiment, the composition ratio of Ge is 8.2% (x = 0.082), and the composition ratio of C is 1% (y = 0.01). It can be seen that the lattice mismatch is 0, and the SiGeC layer 14n and the lower Si layer 13n have the same lattice constant.

4 shows the band offset value? Ec of the conduction band and the band offset value? Ev of the valence band at the interface between the SiGeC layer and the Si layer when the composition ratio of C is taken on the horizontal axis and the energy level is taken on the vertical axis. It is showing form. Only the black ring represents the band offset value ΔEv of the valence band, and the white ring represents the band offset value ΔEc of the conduction band. In addition, the origin of energy is set to the energy value of the lower end of the conduction band of Si for the conduction band, and the energy value of the upper end of the valence band of Si for the valence band. In addition, the solid line of FIG. 4 corresponds to a distortion-free system, and the dotted line of FIG. 4 corresponds to a tensile distortion system.

As shown in Fig. 4, the band offset values of the conduction band and the valence band at the interface between the SiGeC layer (the composition ratio of C is 0.0l) and the Si layer of this embodiment are 300 meV and 0 meV, respectively, and the SiGeC layer and As the interface of the Si layer, it can be seen that there is no band discontinuity in the valence band, and a band discontinuity is formed only in the conduction band. In addition, since the composition ratio of C in the SiGeC layer 14n of this embodiment is 0.01, the SiGeC layer 14n and the Si layer 13n are lattice matched. Therefore, generation of defects such as dislocations due to lattice mismatch with the Si layer 13n below can be prevented in the SiGeC layer 14n in which the channel through which the two-dimensional electron gas travels is formed.

On the other hand, since there is no band discontinuity in the valence band at the interface between the SiGeC layer 14n and the Si layer 13n in this embodiment, holes cannot be closed in the SiGeC layer 14n. Therefore, in the case of a PM0S transistor having holes as a carrier, a heterojunction of the SiGe layer 15p and the Si layer 17p is used. The lattice constant of the SiGe single crystal is larger than the lattice constant of the Si single crystal. Moreover, since the SiGe layer 15p is located on the SiGeC layer 14p lattice matched with the Si layer 13p, the band structure changes due to compression distortion. As a result, the band offset value in the valence band is increasing. Also in this case, when the electric field is applied from the gate, the holes are closed two-dimensionally (2DHG) due to the band inclination to form a carrier accumulation layer. Therefore, the carrier accumulation layer in the SiGe layer 15p becomes a channel for holes to travel at high speed.

As described above, according to the structure of the present embodiment, in the NMOS transistor, the band offset value of the conduction band is sufficient to accumulate the two-dimensional electron gas by adjusting the composition ratio of each element Si, Ge, C in the SiGeC layer 14n. While maintaining the value, lattice matching between the SiGeC layer and the Si layer can be achieved. Therefore, the two-dimensional electron gas in the SiGeC layer can realize high reliability by reducing the defect density while realizing a high speed of operation using high carrier mobility. Further, since there is no band discontinuity in the valence band at the interface between the SiGeC layer 14n and the Si layer 13n, holes cannot be closed in the SiCeC layer 14n, but the SiGe layer 15p and the Si layer ( By using the heterojunction of 17p), a channel of the PM0S transistor using holes as a carrier can be formed, and high speed operation can be realized.

A high performance HCMOS device can be realized by forming a band discontinuity in the valence band using a high speed NMOS transistor and SiGe to integrate a high speed PM0S transistor.

In addition, in the present embodiment, the composition ratio of Ge is 8.2% and the composition ratio of C is 1%. However, in order to make the band discontinuity portion ie the band offset value ΔEv largest in the lattice matching system from FIG. You can see that you can increase it. By setting such a large band offset value ΔEv, the two-dimensional electron gas (2DEG) closed at the hetero interface can run stably without crossing the hetero interface even when the electron concentration becomes high. In particular, it is preferable to adjust the composition ratio of C to the range of 0.01-0.03. Within this range, a band offset value ΔEv (= −0.2 to −0.6 eV) suitable for forming a carrier accumulation layer for closing the two-dimensional electron gas can be obtained in either the distortionless system or the tensile distortion system.

In this embodiment, the composition ratio of Ge in the SiGe layer 15p is set to 30%. However, the composition ratio of Ge may be increased and the compression distortion may be increased so that the band offset value is the largest.

In addition, since the HCMOS device is formed on the Si substrate, the HCMOS device may be used where the speed of the element is required, and other than that, the CM0S device formed on the active region having a normal Si single composition may be manufactured. Such a configuration also enables integration of the M0S type field effect transistor directly fabricated on the Si substrate. Moreover, as an apparatus using SiGeC, it is not necessary to form p and n type transistors on the same substrate. For example, in the case of an integrated circuit used in a mobile communication device, an amplifier or a mixer used in a high frequency region requiring high speed operation does not need to configure a complementary circuit, so only one of p and n types (for example, n type) is used. It is conceivable to configure a MOS transistor using SiGeC, and to configure a digital signal processing portion that needs to form a complementary circuit with a CM0S device using a single Si composition.

Next, the manufacturing method of the HCMOS device of the first embodiment will be described with reference to Figs. 5A to 5F. 5 (a) to 5 (f) are cross-sectional views showing an example of a manufacturing process for realizing the structure of the HCMOS device shown in FIG.

First, in the step shown in FIG. 5 (a), p holes 11 and n holes 12 are formed in the Si substrate 10 by ion implantation.

Next, on the holes 11 and 12 in the step shown in FIG. 5B, the Si layer 13 including the δ doped layer by the UHV-CVD method, and the SiGeC layer 14 (Ge: 8.2%, C: 1%), SiGe layer 15, and Si layer 17 are grown, respectively. In addition, although the δ doping layer and the space layer are formed, the illustration of these layers is omitted for ease of viewing.

Next, in the process shown in FIG. 5C, in order to electrically separate the PMOS transistor and the NMOS transistor, trench trenches are formed, and then the trench trenches 20 are filled with silicon oxide films. Form. By this treatment, the Si layer 13, the SiCeC layer 14, the SiGe layer 15, and the Si layer 17 are respectively the Si layer 13n, the SiGeC layer 14n, and the SiGe layer 15n on the NMOS transistor side. ), The Si layer 17n, and the Si layer 13p on the PMOS transistor side, the SiGeC layer 14p, the SiGe layer 15p, and the Si layer 17p. The surfaces of the Si layers 17n and 17p are oxidized to form gate insulating films 19n and 19p, respectively.

Next, in the process shown in Fig. 5D, a polysilicon film is deposited on the entire surface of the substrate, and then patterned to form the gate electrodes 18b and 18p on the gate insulating films 19n and 19p of the NMOS transistor and the PMOS transistor. Form each. Subsequently, the source / drain regions 16n are formed on the NMOS transistor side by using the gate electrodes 18n and 18p as masks, and the boron ions B + are implanted on the PM0S transistor side. Source and drain regions 16p are formed, respectively. The depth of the source / drain region 16n of the NMOS transistor may be at least deeper than the carrier accumulation layer in the SiCeC layer 14n, and the depth of the source / drain region l6p of the PMOS transistor may be at least a carrier in the SiGe layer 15p. It is good if it is deeper than an accumulation layer. This is because a channel is formed in each carrier storage layer in the SiGeC layer 14n and the SiGe layer 15p.

Next, in the process shown in FIG. 5E, an opening is formed in the upper portion of the source / drain regions 16n and 16p among the gate insulating films 19n and 19p, and the process shown in FIG. 5F. The source and drain electrodes 21n and 21p are formed in the openings of the gate insulating films 19n and 19p, respectively.

As a result, an HCMOS device including an NMOS transistor and a PMOS transistor is formed on the Si substrate 10.

As described above, according to the manufacturing method of this embodiment, different channels must be formed in the NMOS transistor and the PMOS transistor, but the crystal growth can be made common to the NM0S transistor and the PM0S transistor, and thus can be easily manufactured.

(Second embodiment)

In the first embodiment described above, a field-effect transistor was formed using a lattice matched SiGeC layer to silicon, but in this embodiment, distortion is actively introduced into the SiGeC layer in a range where there is no deterioration of crystallinity. By using the change of the band structure by using the transistor. The structure of the HCMOS device according to the present embodiment is basically a structure in which the PM0S transistor and the NMOS transistor according to the first embodiment shown in FIG. 1 are realized in one transistor.

6 (a) to 6 (c) show compressive distortion in the SiGeC layer, lattice matching of the SiGeC layer to the Si layer (no distortion), and tensile strain in the SiGeC layer, respectively. It is a figure which shows the state of a crystal structure. As shown in Fig. 6A, when the lattice constant of the SiGeC layer is larger than the lattice constant of the Si layer, compressive distortion occurs in the SiGeC layer, so that the band gap between the lower end of the conduction band and the upper end of the valence band in the SiGeC layer. The value is expanded. On the other hand, when the lattice constant of the SiGeC layer is smaller than the lattice constant of the Si layer, as shown in Fig. 6C, tensile strain occurs in the SiGeC layer, and the band between the lower end of the conduction band and the upper end of the valence band in the SiGeC layer. The gap is reduced. That is, since the band structure changes due to the distortion of the SiGeC layer, the band offset value of a layer such as a Si layer close to the SiGeC layer can be changed by actively utilizing this effect.

Here, even when the lattice constant of the SiGeC layer is out of the lattice constant of the Si layer, the thickness of the SiGeC layer is such that the lattice relaxation does not occur and the distortion is accumulated, thereby reducing the reliability of the device due to the occurrence of crystal defects such as dislocations. It can be prevented efficiently.

7A and 7B are band structure diagrams and cross-sectional views in the channel region of the field effect transistor according to the present embodiment. After growing the Si layer 13n on the Si substrate, the band gap value in the SiGeC layer 14n is grown by growing the SiGeC layer 14n (10% Ge and 4% C) having a larger C composition ratio. Is large and the lattice constant can be set to be small. Then, the SiGeC layer 14n is subjected to tensile strain by making the thickness of the SiGeC layer 14n small enough that distortion is accumulated without lattice relaxation. Therefore, in addition to the effect of increasing the band gap value by increasing the composition ratio of C, the band offset of the conduction band at the interface between the SiGeC layer 14n and the Si layer 13n by the tensile strain of the SiGeC layer 14n. The value becomes large and the closing efficiency of the two-dimensional electron gas 2 DEG is improved.

Since the SiGeC layer 14n is not lattice relaxed, the lattice constant of the surface coincides with the lattice constant of the Si layer 13n. Therefore, when the SiGe layer 15p is grown on the SiGeC layer 14n, the SiGe layer 15p is subjected to compressive distortion because the lattice constant of the SiGe layer 15p becomes larger than the lattice constant of the Si layer 13n.

Therefore, according to the semiconductor device according to the present embodiment, the tensile strain is introduced into the SiGeC layer 14n and the compression strain is introduced into the SiGe layer 15p, whereby the conduction band at the interface between the SiGeC layer 14n and the Si layer 13n. The band offset value at and the band offset value at the valence band at the interface between the SiGe layer 15p and the Si layer 17p are increased, and the SiGeC layer 14n is used when this transistor is used as the NMOS transistor. In the case of using the channel formed in the PMOS transistor, the channel formed in the SiGe layer 15p can be used to form an HCMOS device having a different gate electrode or source / drain region and having different channel positions. .

Furthermore, by appropriately setting the thickness of each layer, an HCMOS device having a highly effective field effect transistor with no crystallinity potential or defects and good crystallinity can be obtained.

In addition, the dotted line of FIG. 4 mentioned above has shown a composition so that 0.25% tensile distortion may be added to the SiGeC layer 14n in a present Example. In general, when the composition ratio of Ge in the SiGeC layer is 8.2 times the composition ratio of C, lattice matching is performed on the Si layer. Therefore, tensile strain is introduced into the SiGeC layer 14n by making the composition ratio of Ge smaller than 8.2 times the composition ratio of C. You can do it. When the composition ratio of Ge is set to 8.2y-0.12 when the composition ratio of C is y, the lattice constant of the SiGeC layer 14n can be made 0.25% smaller than the lattice constant of the Si layer 13n.

As shown in FIG. 4, it can be seen that the band discontinuity is not formed in the valence band and only the conduction band is formed at the interface between the SiGeC layer 14n and the Si layer 13n as in the case of the distortion-free system. When the composition ratio of C is less than or equal to 2%, the band offset value of the conduction band is almost the same as that of no distortion, and even if the ratio of the composition ratio of C and the composition ratio of Ge deviates from the value satisfying the conditions of lattice matching, Device characteristics almost equal to the sum can be obtained. This is the composition ratio of C at the time of crystal growth of the SiGeC layer 14n and

In terms of controlling the composition ratio of Ge, it is meant to keep the width at this condition, which facilitates crystal growth of the SiGeC layer. In addition, when the composition ratio of C is 2% or more, the band offset value can be increased even at the composition ratio of C as compared with the case of no distortion. This makes it possible to deal with the case where the band offset value is made larger.

Here, although the lattice constant of SiGeC is used smaller than Si, since the layer thickness is a grade which the distortion which lattice relaxation does not generate | occur | produce, reliability of an element does not fall by crystal defects, such as electric potential.

(Third embodiment)

In the first embodiment described above, a heterostructure in which the SiGeC layer is lattice matched to the Si layer in the channel region of the field effect transistor is formed, and electrons or holes are closed in the band discontinuity at the hetero interface and used as a carrier.

In the present embodiment, the quantum well structure (SiGeC, SiGe), which forms a quantum well structure with a structure of Si / SiGeC / Si or Si / SiGe / Si, instead of a hetero interface, may be sandwiched by a barrier layer. Transistor is installed as a channel.

8 is a cross-sectional view of the HCMOS device according to the present embodiment. It is a CMOS device structure in which an NMOS transistor and a PMOS transistor are formed on the Si substrate 30. In this structure, the first Si layer 33n having the p-hole 31 and the n-hole 32 provided on the silicon substrate 30 and the δ doped layer doped with a high concentration of the Group V elements thereon. , 33p) is the same as that of the HCMOS device shown in FIG. 1 in the first embodiment. However, the structures of the PMOS transistors and NMOS transistors on the first Si layers 33n and 33p are different from those of the first embodiment.

In the NMOS transistor, a SiGeC layer 34n having a composition lattice matched to the first Si layer 33n is formed on the first Si layer 33n, and the second Si layer 35n is formed on the SiGeC layer 34n. ) Are stacked. In this embodiment, the quantum well region (SiGeC layer 34n) narrowed by two band discontinuities in the conduction band spanning the first Si layer 33n-SiGeC layer 34n and the second Si layer 35n. Because of this, the carrier accumulation layer for closing the two-dimensional electron gas 2 DEG serving as the carrier is formed in the SiGeC layer 34n which is the quantum well region (see also the band on the right side of FIG. 8). In other words, a channel is formed in the SiGeC layer 34n during operation of the NMOS transistor. Moreover, the small SiGe layer 36n and the 3rd Si layer 37n are formed in order on the 2nd Si layer 35n.

With this structure, as in the first embodiment, a channel for carrier movement is formed in the SiGeC layer 34n having higher electron mobility compared to the Si layer, so that an NMOS transistor having a high operating speed can be obtained. have. In addition, since the film thickness of the SiGeC layer 34n serving as a quantum well is small, the closing efficiency of the carrier can be improved than that in the structure of the first embodiment, and the mixing crystal ratio can be realized in a system having a small ratio. Therefore, the factor which degrades the mobility of the electron used as a carrier, such as scattering of a carrier resulting from deterioration of the regularity of the crystal structure accompanying mixed crystallization, can be suppressed.

Also in the PMOS transistor, a SiGeC layer 34p having a composition lattice matched to the first Si layer 33p on the first Si layer 33p, a second Si layer 35p, and a SiGe layer 36p having a small film thickness ) And the third Si layer 37p are formed in the same manner as that of the NMOS transistor. However, in the case of the PMOS transistor, in the valence band covering the second Si layer 35p, the SiGe layer 36p, and the third Si layer 37p, the quantum well region (SiGe layer) narrowed at two band discontinuities. (36p)), and a carrier accumulation layer for two-dimensionally closing holes, which are carriers, is formed in this quantum well region. In other words, a channel is formed in the SiGe layer 36p during the operation of the PM0S transistor. Since the SiGe layer 36p also has a higher hole mobility than the Si layer, the operation speed of this PM0S transistor also increases.

In the NMOS transistors and PMOS transistors, gate insulating films 39n and 39p made of silicon oxide films are formed on the substrate, and gate electrodes 38n and 38p are formed on the gate insulating films 39n and 39p. Source and drain regions 42n and 42p are formed on both sides of the gate electrodes 38n and 38p, and source and drain electrodes 41n and 41p are contacted on the source and drain regions 42n and 42p. Needless to say, in the NMOS transistor and the PMOS transistor, the electron and hole travel in the SiGeC layer 34n and the SiGe layer 36p, which are quantum well regions, are applied to the voltages applied to the gate electrodes 38n and 38p. It is controlled by each.

In addition, a trench isolation 40 is formed between the NMOS transistor and the PMOS transistor by embedding a silicon oxide film in a separation groove, and the trench isolation 40 electrically separates the NMOS transistor and the PMOS transistor from each other. .

According to the HCMOS device of the present embodiment, as in the first embodiment, in the NMOS transistor, a SiGeC layer 34n serving as a quantum well region is formed at the same time as lattice matching to the Si layer, and in this SiGeC layer 34n. The channel for driving the former is formed. Also in the PM0S transistor, a SiGe layer 36p serving as a quantum well region is formed, and a channel through which holes travel is formed in the SiGe layer 36p. Therefore, high-performance HCMOS can be realized by integrating a high switching speed NMOS transistor and PMOS transistor using a quantum well structure having high carrier closing efficiency.

In the present embodiment, however, the HCM0S device may be used for a circuit requiring an element speed, and in other circuits, the CM0S device formed on a normal Si substrate may be fabricated and directly formed on the Si substrate. It is also possible to integrate a M0S type field effect transistor.

Note that both the channels of the NMOS transistor and the PMOS transistor do not necessarily have to be a quantum well region.

Next, a method of manufacturing the HCMOS device according to the third embodiment will be described with reference to Figs. 9A to 9F. 9 (a) to 9 (f) are cross-sectional views showing an example of a manufacturing process for realizing the structure of the HCM0S device shown in FIG.

First, the outline of the manufacturing process will be described. When growing the SiGeC layer 34, the second Si layer 35, and the SiGe layer 36, the film thicknesses of the SiGeC layer 34 and the SiGe layer 36 are both determined. It is 10 nm or less, for example, 3 nm so that it may become a well structure. The other part is formed in a step substantially the same as the step shown in Figs. 5A to 5F.

First, in the process shown in FIG. 9A, the p-hole 31 and the n-hole 32 are formed in the Si substrate 30 by ion implantation.

In the process shown in FIG. 9B, the first Si layer 33 including the δ doping layer on the p-hole 31 and the n-hole 32 by the UHV-CVD method, and the SiGeC layer ( 34) (Ge: 36%, C: 4%), the second Si layer 35, the SiGe layer 36, and the third Si layer 37 are sequentially grown.

Next, in the process shown in Fig. 9C, trench isolation grooves are formed to electrically separate the PMOS transistors and the NMOS transistors, and then the trenches are filled with a silicon oxide film to form trench isolations 40. . By this treatment, the first Si layer 33, the SiGeC layer 34, the second Si layer 35, the SiGe layer 36, the third Si layer 37, and the gate insulating film 39 are respectively NMOS transistors. The first Si layer 33n on the side, the SiGeC layer 34n, the second Si layer 35n, the SiGe layer 36n, the third Si layer 37n and the first Si layer 33p on the PMOS transistor side, The SiGeC layer 34p, the second Si layer 35p, the SiGe layer 36p, and the third Si layer 37p are separated. Thereafter, the surfaces of the third Si layers 37n and 37p are oxidized to form gate insulating films 39n and 39p.

Next, in the step shown in FIG. 9D, after the gate electrodes 38n and 38p are formed, the source / drain regions 42n are formed on the NMOS transistor side by implantation of phosphorus ions P +. On the PMOS transistor side, source and drain regions 42p are formed by implantation of boron ions B +. The depth of the source / drain region 42n of the NMOS transistor may be at least deeper than the SiGeC layer 34n, and the depth of the source / drain region 42p of the PMOS transistor may be at least deeper than the SiGe layer 36p. This is because a channel is formed in the SiGeC layer 34n and the SiGe layer 36p.

Next, in the process shown in Fig. 9E, openings are formed in the gate insulating films 39n and 39p in the upper portions of the source and drain regions 42n and 42p, and in the process shown in Fig. 9F. Source and drain electrodes 41n and 41p are formed in the opening, respectively.

Through the above steps, the structure of the HCMOS device comprising the NMOS transistor and the PMOS transistor according to the third embodiment is realized.

According to the manufacturing method of this embodiment, HCMOS in which the channel of the NMOS transistor is a SiGeC layer 34n having a quantum well structure using a heterojunction, and the SiGe layer 36p having a quantum well structure using a heterojunction is a channel of the PMOS transistor. The device is easily formed. Moreover, according to the manufacturing method of the present embodiment, different channels must be formed in the NM0S transistor and the PM0S transistor, but the crystal growth can be made common to the NMOS transistor and the PMOS transistor, and thus can be easily manufactured.

(Example 4)

10 is a cross-sectional view showing the structure of the field effect transistor according to the fourth embodiment. This embodiment relates to a structure for providing a source / drain contact suitable for a hetero field effect transistor.

As shown in Fig. 10, on the hole 51 made of the Si layer, the SiGe buffer layer 52, the δ doping layer 53, the space layer 54, the n-channel layer 67, and i -Si layer 55, i-Si _1-x Ge _x layer 56, i-Si layer 57, and gate insulating film 58 are formed. A gate electrode 65 is formed on the gate insulating film 58, and a source / drain contact W layer (on the region located on both sides of the gate electrode 65 in the i-Si _1-x Ge _x layer 56) is formed. 61 and Al source-drain electrodes 63 are formed in this order. In addition, a portion of the SiGe buffer layer 52, a δ doping layer 53, a space layer 54, an n-channel layer 67, an i-Si layer 55, and an i-Si are formed on both sides of the gate electrode 65. _The source / drain region 59 is formed in the region covering the _1-x Ge _x layer 56 and the i-Si layer 57. In addition, between the gate electrode 65 and the Al source / drain electrode 63 is filled by the insulating film 66 of the first layer.

Here, the structure of each sound of the field effect transistor will be described.

First, the composition ratio of Ge in the SiGe buffer layer 52 is increasing as it goes upwards. The SiGe buffer layer 52 is formed with a film thickness sufficient to lattice the SiGe mixed crystal, so that the SiGe buffer layer 52 has a lattice constant larger than Si, and the n-channel can be formed thereon using a distortion effect thereon. When heterojunctions of Si and SiGe layers are formed in a lattice match to a Si substrate without using such a lattice relaxed SiGe buffer layer, discontinuous parts with a large step difference appear in the valence band, but almost no discontinuities appear in the conduction band. In this case, it is difficult to form the n-channel by closing the two-dimensional electron gas.

Here, the composition ratio of Ge in the SiGe buffer layer 52 changes continuously, for example from 0% to 30%, or stepwise for each thin layer. At this time, lattice relaxation occurs in each layer so that the lattice constant in the substrate surface at the uppermost surface of the buffer layer is equal to Si _0.7 Ge _0.3 . The change in the composition ratio in the vertical direction is because the influence of crystal defects such as dislocations due to lattice relaxation on the channel thereon is reduced. Moreover, the film thickness of the whole SiGe buffer layer 52 is required about 1 micrometer.

On this SiGe buffer layer 52, a space layer 54 made of Si _0.7 Ge _0.3 without impurity is disposed. A carrier structure is formed in the discontinuity of the conduction band existing at the hetero interface between the space layer 54 and the Si layer 55 thereon, and the carrier accumulation layer closes the electrons two-dimensionally in the n-channel 67. )

The δ doping layer 53 is a layer doped with a high concentration of an element of group V such as P or As to supply electrons as carriers to the n-channel 67. The space layer 54 on the δ doped layer 53 is composed of Si _0.7 Ge _0.3 which is not doped with impurities, and by spatially separating the carrier electrons of the n-channel 67 and the ions of the δ doped layer 53, It has a role of improving the mobility by reducing the scattering by the ions of the carrier electrons. The thicker the film thickness of the space layer 54 can reduce the scattering effect of carriers due to ionized impurities. On the contrary, since the carrier density decreases, the thickness of the space layer 54 is preferably about 3 nm.

The i-Si _1-x Ge _x layer 56 and the i-Si layer 57 are used to form the p-channel 68 by forming a step in the valence band at the hetero interface. It is preferable to set X to around 0.7.

The gate insulating film 58 insulates the gate electrode 65 from the semiconductor layer below, thereby reducing the gate leakage current and enabling low power consumption operation of the device. In addition, since the oxide film formed by oxidizing the SiGe layer 56 becomes a water-soluble unstable film, it is preferable to use a silicon oxide film as the gate insulation film also in the SiGe field effect transistor. Therefore, in the Si-based hetero M0S device, the semiconductor layer immediately below the gate insulating film is preferably a Si layer.

That is, the field effect transistor according to the present embodiment includes a channel region formed of the above-mentioned laminated film, a source / drain region 59 indicated by a dotted line in FIG. 10, and Al for introducing and acquiring current for operation of the transistor. It consists of the source-drain electrode 63 and the gate electrode 65 for applying the voltage for controlling an electric current. When the field effect transistor is used as an n-channel field effect transistor, a voltage is applied to the gate electrode 65 to form the n-channel 67, and used as a p-channel field effect transistor. In this case, a voltage is applied to the gate electrode 65 to form the p-channel 68.

The characteristics of the present invention according to the present embodiment include a first semiconductor layer including an i-Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1) and the first semiconductor layer. A channel region having a second semiconductor layer having a different band gap, a carrier storage layer formed in a region near the interface between the first and second semiconductor layers, a third semiconductor layer, and a band larger than this third semiconductor layer A source / drain contact layer having a source / drain region having a fourth semiconductor layer having a gap and a low resistance conductor film formed directly on the third semiconductor layer is provided.

When the field effect transistor of the present embodiment is used as an n-channel field effect transistor, the i-Si layer 55 has an i-Si _1-xy Ge _x C _y layer (0≤x≤1,0≤). (x = y = 0), the SiGe buffer layer 52 is the second semiconductor layer, and the i-Si _1-x Ge _x layer 56 is the third semiconductor layer i-Si layer 57 as the fourth semiconductor layer is larger band gap than the i-Si _1-x Ge _x layer 56, the third right of the semiconductor layer is an i-Si _1-x Ge _x layer 56 The source-drain contact W layer 61 is formed on it.

On the other hand, when the field effect transistor of the present embodiment is used as a p-channel field effect transistor, the i-Si _1-x Ge _x layer 56 has an i-Si _1-xy Ge _x C _y layer (0≤x (Y = 0), which is a first semiconductor layer comprising ≦ 1,0 ≦ y ≦ 1, and a third semiconductor layer, and i-Si layer 57 is a second semiconductor layer and at the same time has a band gap than that of the third semiconductor layer. As this large fourth semiconductor layer, a source-drain contact W layer 61 is formed directly on the i-Si _1-x Ge _x layer 56 that is the third semiconductor layer.

As described above, in the present embodiment, the region on the substrate side to which the A1 source / drain electrodes 63 are contacted is provided in a layer having a small band gap in each semiconductor layer for channel formation. The case of this embodiment, Si layer 57 and the _{i-Si 1-x} Ge _x layers of the hetero interface between the 56 and the small band gap _{i-Si 1-x} Ge _x layer 56, the p- channel for forming The source-drain contact W layer 61 is provided directly above. As a result, the contact resistance is smaller than that of providing the contact directly on the i-Si layer 57, which is the uppermost semiconductor layer, and the low power consumption and high speed operation of the device can be achieved.

Further, if W is grown on a Si _0.7 Ge _0.3 layer on a Si layer and then a metal (Al in this case) is deposited, a very low contact can be obtained. A contact using this SiGe film can obtain a contact having a lower one-digit resistance value than a low resistance contact using a silicide technology which is generally used as a low resistance contact in a conventional CMOS device (IEEE Electron Device Letters vol. L7.No.). .7, l996 pp360).

In this paper, the SiGe layer is grown only for source / drain electrode contact formation. However, as shown in the present embodiment, a structure for holding a contact on the SiGe layer for channel formation is evident, as will be apparent from the transistor manufacturing method described below. Productivity is improved by eliminating the need to grow new SiGe crystals.

In this embodiment, however, the HCMOS device may be used where the speed of the device is required, and in addition, a CMOS device formed on a normal Si substrate may be fabricated, or a M0S type formed directly on a Si substrate. Integration of field effect transistors is possible.

Next, a method of manufacturing the field effect transistor according to the present embodiment will be described. 11 (a) to 11 (e) and 12 (a) to 12 (e) are cross-sectional views illustrating examples of manufacturing processes for realizing the structure of the field effect transistor shown in FIG.

First, in the process shown in Fig. 11A, ions are implanted into the Si substrate 50 prior to epitaxial growth of channel formation, and the p-hole 51n serving as the basis for the NMOS transistor, the PMOS transistor, and n The hole 51p is formed.

Next, in the process shown in FIG. 11B, before the epitaxial growth on the substrate, the substrate is cleaned by using an RCA cleaning method or the like to remove impurities on the surface. After that, the oxide film on the surface is removed, the substrate is inserted into the epitaxial growth apparatus, and heated in a vacuum to obtain a clean surface. Then, epitaxial growth of the semiconductor layer for forming a channel region is performed on this clean surface. The semiconductor layer includes a SiGe buffer layer 52, a δ doping layer 53, a space layer 54, an n-channel layer 67, an i-Si layer 55, and an i-Si _1-x Ge _x layer ( 56), p-channel layer 68, i-Si layer 57, and the like. However, the illustrations of the δ doped layer 53, the space layer 54, the n-channel layer 67 and the p-channel layer 68 are omitted for ease of viewing. Hereinafter, the formation procedure of each layer in this semiconductor layer is demonstrated.

In the growth method of the semiconductor layer, an MBE method using a solid source, a UHV-CVD method using a gas source, or the like can be used. In the case of the UHV-CVD method, the atmosphere in the apparatus is first set to ultra high vacuum (about 10 ^-10 Torr), and a source necessary for crystal growth is introduced into the vacuum chamber, and then the vacuum degree of 10 ^{-5 to} 10 ^-6 Torr is reached. Crystal growth in the state.

Therefore, also in this embodiment, after a clean surface is produced on the substrate by the above-described process, the substrate temperature is set to about 500 to 700 ° C to grow each semiconductor crystal layer when the vacuum degree in the vacuum container becomes sufficiently high. . In addition, when the substrate temperature is changed, the substrate temperature is not changed while the single layer is grown, in order to affect the quality of the crystal, such as a change in composition ratio in a single semiconductor crystal layer. Further, at a high temperature of 800 ° C. or higher, Ge and Si diffuse to each other to impair the steepness of the hetero interface, or to mitigate distortion to deteriorate channel characteristics. Therefore, the growth temperature is 700 as described above. Choose below ° C.

In crystal growth, a source gas necessary for crystal growth is introduced into a vacuum vessel in an ultra-high vacuum state. As a source gas used for crystal growth, an indicator LAN is used for the growth of the Si layer. In the growth of the SiGe layer, germanium is used as a source gas of Ge in addition to a source gas for growing a Si layer such as an indicator LAN. At this time, the composition ratio of Si and Ge in the SiGe layer can be controlled by adjusting the partial pressure ratio of each source gas. The gas flow rate is adjusted so that the degree of vacuum becomes about 10 ^-5 to 10 ^-6 Torr.

First, the SiGe buffer layer 52 is formed by stacking a plurality of SiGe layers with lattice relaxation and changing the composition ratio step by step. At this time, in order to change the composition ratio step by step, the ratio of the partial pressure of the source gas of Si and the partial pressure of the source gas of Ge is changed step by step as described above.

Next, a dopant gas such as arsine or phosphine is introduced into the vacuum vessel simultaneously with the indicator LAN and germanium to form the δ doped layer 53.

Herein, when the impurities introduced into the δ doping layer 53 are mixed with the space layer 54, the transistor characteristics deteriorate. Therefore, once the dopant gas is introduced into the vacuum vessel, the supply of the source gas is stopped and the degree of vacuum After sufficiently improved, a gas for growing the space layer 54 is introduced to grow the space layer 54. The composition of the space layer 54 is made into Si _0.7 Ge _0.3 uniformly, and it grows by fixing the flow volume of an indicator LAN and germanium.

After the growth of the space layer 54, the supply of the source gas is once stopped and the degree of vacuum is improved, and then only the indicator LAN is introduced into the growth chamber to grow the i-Si layer 55 which is not doped with impurities.

After the growth of the i-Si layer 55, the iran and germanium are again introduced into the growth chamber to grow the i-Si _1-x Ge _x layer 56. The composition ratio of Ge is 70%. After the growth of the i-Si _1-x Ge _x layer 56, the supply of the source gas is once stopped, and after the degree of vacuum is improved, only the indicator LAN is introduced into the growth chamber to grow the i-Si layer 57.

By the above process, the epitaxial growth process of the semiconductor layer which comprises a channel region is complete | finished.

Next, in the process shown in Fig. 11C, the substrate is taken out from the UHV-CVD apparatus and introduced into the thermal oxidation furnace to oxidize the surface of the uppermost i-Si layer 57 to form a silicon oxide film. Form 58.

Next, in the process shown in FIG. 11D, the gate electrode 65 is formed on the gate insulating film 58. The formation method of this gate electrode is the same as that of the conventional CM0S apparatus process. That is, the polysilicon film is deposited, the impurities are ion implanted, and the polysilicon film is patterned by dry etching to form the gate electrodes 65n and 65p. As impurity ions, boron fluoride ion (BF2 +) can be used. In the step where the polysilicon film for the gate electrode is deposited, the source and drain regions are not formed.

Next, in the process shown in Fig. 11E, impurity ions serving as dopants are implanted into the substrate using the gate electrodes 65n and 65p as masks to form the source and drain regions 59n and 59p. Etching is performed to remove the oxide film exposed on the substrate to make contact. In ion implantation, the acceleration voltage of the ions is selected such that the peak of the impurity distribution provides the contact of the source and drain electrodes. As implanted impurity ions, arsenic ions (As +) or phosphorus ions (p +), which are n-type impurities, are used in the NMOS transistor region, and boron ions (B +), which are p-type impurities, are used in the PMOS transistor region. Therefore, it is necessary to use separate masks for ion implantation for forming the source and drain regions 59n of the NMOS transistors and ion implantation for forming the source and drain regions 59p of the PMOS transistors.

Immediately after ion implantation, annealing is performed for activation of impurities. However, RTA (Rapid thermal) for a short time (30 seconds) is about 100 ° C. so as to prevent the occurrence of crystal defects in the interfacial diffusion of Si and Ge at the hetero interface or relaxation of distortion present in the Si / SiGe system by annealing. It is preferable to do anylling.

Next, in the process shown in Fig. 12A, a photoresist mask (not shown) is formed once again on the substrate, and at least the channel region between the NMOS transistor formation region and the PMOS transistor formation region by dry etching. It goes deeper to form the device isolation groove 71.

Next, in the process shown in FIG. 12B, the first layer insulating film 72 is deposited on the entire surface of the substrate including the grooves 71. As the material constituting the insulating film, in order to avoid high temperature treatment, it is preferable to use a TEOS film or the like by the plasma CVD method which is formed at 500 ° C or lower. At this time, the trench isolation 73 is formed by an insulating film embedded in the groove 71.

Next, source and drain contacts, which are the features of the present embodiment, are formed in the following order. However, the process for realizing the structure shown in FIG. 10 is not limited to the following procedure.

In order to achieve the maximum effect of this embodiment, it is necessary to have a very thin specific semiconductor layer which finally forms the basis of the contact. Therefore, in this embodiment, as a specific semiconductor layer that underlies the i-Si ₁ selected -xGe _x layer (56n, 56p), until the exposure i-Si ₁ -xGe _x layer (56n, 56p) Etch. When exposing the i-Si ₁ - _x Ge _x layers 56n and 56p, it is preferable to use etching having high selectivity by wet etching. However, since wet etching is deficient in other directions and is not suitable for microfabrication, first, dry etching is performed to selectively remove regions of the insulating film 72 of the first layer to form the source and drain electrodes, thereby removing contact holes. After forming and exposing the gate insulating films 58n and 58p, it is preferable to perform wet etching. Examples of such processing include the following processing.

First, as is well known, a hydrofluoric acid-based solution is used to remove the oxide films (gate insulating films 58n and 58p) of the uppermost layer. When the i-Si layers 57n and 57p are exposed, the hydrofluoric acid hardly removes silicon, so the etching solution is changed to an etching solution capable of removing the i-Si layer 57. In this embodiment, since the contact is formed in the i-Si _1-x Ge _x layers 56n and 56p under the i-Si layers 57n and 57p, the i-Si _1-x Ge _x layer ( The etching liquid (etchant) capable of selectively etching the i-Si layers 57n and 57p is selected without etching the 56n and 56p much. Using this etchant, i-Si layers 57n and 57p are removed to expose i-Si _1-x Ge _x layers 56n and 56p. At this time, part of the i-Si _1-x Ge _x layers 56n and 56p may be removed by over etching. As described above, the i-Si _1-x Ge _x layers 56n and 56p are epitaxially grown to form n-channels in the channel region of the NMOS transistor. Therefore, using this embodiment, a process for newly growing i-Si _1-x Ge _x layers 56n and 56p is unnecessary in order to form a low resistance contact using a SiGe layer.

Next, a low resistance metal film is deposited on the exposed i-Si _1-x Ge _x layers 56n and 56p to form a contact. As the metal material constituting the metal film, when tungsten (W) is used as described above, a very low contact value can be formed. Thus, in the present embodiment, by using the LPCVD method, a gas diluted with hydrogen of WF6 is used as the source gas, and the temperature condition is 400 ° C., and the source is placed on the i-Si _1-x Ge _x layers 56n and 56p. The drain contact W layers 61n and 61p are selectively grown.

Next, in the process shown in Fig. 12E, the A1 alloy film is deposited on the entire surface of the substrate by sputtering and then patterned to form the A1 source / drain electrodes 63n and 63p. In the above steps, a low resistance contact can be formed on the source and drain regions.

As described above, in the Si-based hetero-M0S device, since the uppermost semiconductor layer is preferably a Si layer having a large band gap, since the silicon oxide film is used as the gate insulating film, the contact metal layer is removed after removing the semiconductor layer as in the present embodiment. The technique for forming the polymer is particularly suitable for the formation of a Si-based hetero-M0S device.

(Example 5)

In the above embodiment, a channel structure using a heterojunction composed of Si and SiGe has been exemplified. However, the invention for forming a low resistance contact in the source / drain region of the HCMOS device is not limited to this embodiment. Channels by heteroepitaxial layered films having a structure other than the stacked structure of SiGe in an embodiment, such as Si and i-Si _1-xy Ge _x C _y layers (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1) mixed crystal semiconductor The channel may be formed in between. The formation of such a low resistance contact layer becomes effective because the channel formation by the hetero interface requires the joining of two semiconductors having different band gaps.

FIG. 13 is a sectional view of an HCMOS device according to a fifth embodiment in which a low resistance contact metal layer is formed in the structure shown in FIG. 1.

As shown in FIG. 13, in the HCMOS device according to the present embodiment, source / drain contact W layers 25n and 25p are formed on the SiGe layers 15n and 15p.

The features of the invention according to this embodiment include, in addition to the features of the first embodiment, a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1), as in the fourth embodiment. A channel region having a first semiconductor layer, a second semiconductor layer having a band gap different from that of the first semiconductor layer, and a carrier storage layer formed in an area near an interface between the first and second semiconductor layers; A source / drain contact layer comprising a third semiconductor layer, a source / drain region having a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer, and a low resistance conductor film formed directly on the third semiconductor layer. It is provided with.

In the NMOS transistor of the present embodiment, the SiGeC layer 14n is a first semiconductor layer including a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1). 13n) is a second semiconductor layer, SiGe layer 15n is a third semiconductor layer, and Si layer 17n is a fourth semiconductor layer having a larger band gap than SiGe layer 15n, and is a SiGe layer that is a third semiconductor layer. The source-drain contact W layer 25n is formed just above 15n.

On the other hand, in the PMOS transistor of the present embodiment, the SiGe layer 15p includes a first semiconductor layer (y = 0) including a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1). At the same time, the third semiconductor layer, the Si layer 17p is a second semiconductor layer and a fourth semiconductor layer having a larger band gap than the third semiconductor layer. The source layer is placed directly on the SiGe layer 15p as the third semiconductor layer. A drain contact W layer 25p is formed.

As described above, in this embodiment, the region (source-drain contact W layers 25n, 25p) on the substrate side for making contact with the A1 source-drain electrodes 21n, 21p is a band among the semiconductor layers for channel formation. Since the gap is provided just above the small layer, the contact resistance is smaller than that of providing the contact directly above the Si layers 17n and 17p, which is the uppermost semiconductor layer, enabling low power consumption and high speed operation of the device. do.

In particular, since source / drain contact W layers 25n and 25p made of tungsten (W) are provided to contact the SiGe layers 15n and 15p, very low contact resistance can be obtained.

That is, in this embodiment, the contact resistance can be reduced while exhibiting the effect of the first embodiment.

(Example 6)

FIG. 14 is a sectional view of an HCMOS device according to a sixth embodiment in which a low resistance contact metal layer is formed in the structure shown in FIG. 8.

As shown in Fig. 14, in the HCMOS device according to the present embodiment, source / drain contact W layers 45n and 45p are formed on SiGe layers 36n and 36p serving as quantum well regions.

In addition to the features of the third embodiment, a feature of the present invention according to the present embodiment is a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1) as in the fourth embodiment. A channel region having a first semiconductor layer, a second semiconductor layer having a band gap different from the first semiconductor layer, and a carrier storage layer formed in an area near an interface between the first and second semiconductor layers; And a source / drain contact including a source / drain region having a third semiconductor layer, a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer, and a low resistance conductor film formed directly on the third semiconductor layer. It is a point provided with a layer.

In the NMOS transistor of the present embodiment, the SiGeC layer 34n, which is a quantum well region, is a first semiconductor layer including a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1). The first Si layer 33n is a second semiconductor layer, the SiGe layer 36n, which is a quantum well region, is a third semiconductor layer, and the third Si layer 37n has a larger band gap than the SiGe layer 36n. As the fourth semiconductor layer, a source-drain contact W layer 45n is formed directly on the SiGe layer 36n which is the third semiconductor layer.

On the other hand, in the PMOS transistor of the present embodiment, the SiGe layer 36p includes a first semiconductor layer (y = 0) including a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1). At the same time, the third semiconductor layer is a third semiconductor layer, and the third Si layer 37p is a second semiconductor layer and a fourth semiconductor layer having a larger band gap than the third semiconductor layer, and is directly above the SiGe layer 36p as the third semiconductor layer. The source-drain contact W layer 45p is formed.

As described above, in the present embodiment, a band gap is formed in each semiconductor layer for channel formation in the region (source / drain contact W layers 45n and 45p) on the substrate side for contacting the Al source and drain electrodes 41n and 41p. Since it is provided directly above the small layer, the contact resistance becomes smaller than providing the contact directly above the Si layers 37n and 37p, which is the uppermost semiconductor layer, thereby enabling low power consumption and high speed operation of the device.

In particular, since the source / drain contact W layers 45n and 45p made of tungsten (W) are provided so as to contact the SiGe layers 36n and 36p, a very low contact resistance can be obtained.

That is, in this embodiment, the contact resistance can be reduced while exhibiting the effect of the third embodiment.

(Other Modified Examples)

As the first to sixth embodiments, the MOS type field effect transistor having the gate insulating film provided under the gate electrode has been described, but the present invention is not limited to these embodiments. In particular, a field effect transistor using a hetero interface rather than a hetero M0S structure having an insulating film on the uppermost layer can be implemented using a device using a Schottky junction without using an insulating film, and the effect of reducing the resistance can be obtained. It is advantageous for power and high speed operation.

In the above first to sixth embodiments, the δ doping layer is formed, but the present invention is not limited to this embodiment, and the effects of the present invention can be obtained without providing the δ doping layer. In addition, even when the δ doped layer is formed, the space layer is not necessarily required.

In said 1st, 2nd, 3rd, 5th, and 6th Example, you may provide the SiGeC layer which added a trace amount C layer instead of a SiGe layer.

In addition, in the said 1st, 2nd, 3rd, 5th, 6th Example, you may reverse | vertise the vertical relationship of a SiGeC layer and a SiGe layer. In that case, in the fifth and sixth embodiments, the source / drain contact W layer may be formed directly on the SiGeC layer in the source / drain region.

According to claims 1 to 16, in the semiconductor device having a field effect transistor, and C install a Si layer of Si _1-xy Ge _x C _y layer has a composition ratio y of 0.01 to 0.03 and, Si _1-xy Ge _x C _y Since the carrier storage layer formed in the layer is used as a channel, it is possible to provide a semiconductor device having a field effect transistor having a high operating speed and high reliability.

According to claims 17 to 29, in a semiconductor device having a field-effect transistor, between the first Si layer and the first Si _1-xy Ge _x C _y layer, the second Si layer and the second Si _{1- The} band discontinuity in the interface between the _xy Ge _x C _y layers was used to form an accumulation layer that closes the electrons and holes two-dimensionally, and a field effect transistor having the accumulation layer as a channel was provided to close the carrier. It is possible to provide a semiconductor device which functions as an HCMOS device having an efficient channel, a high operation speed, and a highly reliable n-channel and p-channel field effect transistor.

The structure of this semiconductor device can be easily realized by the manufacturing method of the semiconductor device of Claim 33.

30. A semiconductor device having a field effect transistor having a band discontinuity as a channel formed between a first semiconductor layer and a second semiconductor layer including a Si _1-xy Ge _x C _y layer, Since the drain region is constituted by the third semiconductor layer and the fourth semiconductor layer having a larger band gap than the third semiconductor layer, and a source / drain contact layer made of a low resistance conductor film is provided directly on the third semiconductor layer. In addition, it is possible to provide a semiconductor device having a high operation speed using a heterojunction and a small source / drain contact resistance.

The structure of this semiconductor device can be easily realized by the manufacturing method of the semiconductor device of Claims 34-37.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the present invention as set forth in the appended claims.

Claims (37)

A semiconductor device which is formed on a part of a semiconductor substrate and has a field effect transistor having a channel region between the gate electrode and the source / drain region and the source / drain region, In the channel region Si layer, A Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0y ≦ 1) formed adjacent to the Si layer and having a composition ratio of C of 0.01 to 0.03, A semiconductor storage device, wherein a carrier storage layer is formed in a region proximate to the Si layer in a Si _1-xy Ge _x C _y layer. The method of claim 1, A semiconductor device, characterized in that the composition ratio of the Si _1-xy Ge _x C _y layer of each element is to be adjusted to a composition ratio which is lattice matched the Si _1-xy Ge _x C _y layer and the Si layer. The method of claim 1, The said Si _1-xy Ge _x C _y layer has a lattice constant smaller than the said Si layer, and has a film thickness which does not produce lattice relaxation. The method of claim 1, wherein And a M0S transistor formed on the semiconductor substrate, the semiconductor layer having a single composition as a channel region. The method according to any one of claims 1 to 3, A carrier accumulated in the carrier accumulation layer is a negative carrier. The method of claim 4, wherein A carrier accumulated in the carrier accumulation layer is a negative carrier. The method according to any one of claims 1 to 3 and 6, And a carrier supply layer for supplying a carrier to the carrier accumulation layer in a region proximate to the Si _1-xy Ge _x C _y layer in the Si layer. The method of claim 4, wherein And a carrier supply layer for supplying a carrier to the carrier accumulation layer in a region proximate to the Si _1-xy Ge _x C _y layer in the Si layer. The method of claim 5, And a carrier supply layer for supplying a carrier to the carrier accumulation layer in a region proximate to the Si _1-xy Ge _x C _y layer in the Si layer. The method of claim 1, The carriers accumulated in the carrier accumulation layer are negative carriers, A field effect transistor formed on another portion of the semiconductor substrate and having a gate electrode and a channel region between the source / drain region and the source / drain region, The channel region of the another field effect transistor is A second Si layer, A SiGe layer formed in proximity to the second Si layer, The semiconductor device according to claim 1, wherein a second carrier accumulation layer is formed in the region adjacent to the second Si layer in the SiGe to accumulate positive carriers. The method of claim 1, And the Si _1-xy Ge _x C _y layer is a quantum well region. The method of claim 10, And said SiGe layer is a quantum well region. The method according to any one of claims 1 to 3, 6 and 8 to 12, The source / drain region has a first semiconductor layer and a second semiconductor layer having a band gap larger than that of the first semiconductor layer, A semiconductor device further comprising a source / drain contact layer made of a low resistance conductor film formed directly on the first semiconductor layer. The method of claim 4, wherein The source / drain region has a first semiconductor layer and a second semiconductor layer having a band gap larger than that of the first semiconductor layer, A semiconductor device further comprising a source / drain contact layer made of a low resistance conductor film formed directly on the first semiconductor layer. The method of claim 5, The source / drain region has a first semiconductor layer and a second semiconductor layer having a band gap larger than that of the first semiconductor layer, A semiconductor device further comprising a source / drain contact layer made of a low resistance conductor film formed directly on the first semiconductor layer. The method of claim 7, wherein The source / drain region has a first semiconductor layer and a second semiconductor layer having a band gap larger than that of the first semiconductor layer, A semiconductor device further comprising a source / drain contact layer made of a low resistance conductor film formed directly on the first semiconductor layer. A field effect transistor formed on a part of the semiconductor substrate and having a gate electrode and a channel region between the source and drain regions and the source and drain regions; In the channel region, A first Si layer, A first Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, Oy ≦ 1) formed adjacent to the Si layer, A second Si layer, It formed adjacent to the Si layer of the second of said first Si _1-xy Ge _x C _y layer and has a second Si _1-xy Ge _x C _y layer (0≤x≤1 having different band gaps, 0≤y≤1) is installed, An area proximate to the first Si layer in the first Si _1-xy Ge _x C _y layer and an area proximate to the second Si layer in the second Si _1-xy Ge _x C _y layer And a first carrier accumulation layer for closing carriers of a different conductivity type from and formed respectively. The method of claim 17, The composition ratio y of C in said 2nd Si _1-xy Ge _x C _y layer is 0, The semiconductor device characterized by the above-mentioned. The method of claim 17, And a M0S transistor formed on said semiconductor substrate and having a single layer of semiconductor layer as a channel region. The method of claim 17, The composition ratio y of C in said 1st Si _1-xy Ge _x C _y layer is 0.01-0.03, The semiconductor device characterized by the above-mentioned. The method of claim 17, The composition ratio of said first Si _1-xy Ge _x C _y each element of the floor of Figure 1, characterized in that it is adjusted to a composition ratio that is lattice-matched Si _1-xy Ge _x C _y layer and said first Si layer of the first A semiconductor device. The method of claim 17, And said first Si _1-xy Ge _x C _y layer has a lattice constant smaller than the lattice constant of said first Si layer and has a film thickness that does not cause lattice relaxation. The method according to any one of claims 17 to 22, Carriers accumulated in the first carrier storage layer are negative carriers, The carrier accumulated in the second carrier storage layer is a positive carrier. The method according to any one of claims 17 to 22, A carrier supply layer for supplying a carrier to the first carrier accumulation layer is further formed in a region proximate to the first Si _1-xy Ge _x C _y layer in the first Si layer. Semiconductor device. The method of claim 23, A carrier supply layer for supplying a carrier to the first carrier accumulation layer is further formed in a region proximate to the first Si _1-xy Ge _x C _y layer in the first Si layer. Semiconductor device. The method of claim 17, At least one of the first and second Si _1-xy Ge _x C _y layers of the Si _1-xy Ge _x C _y layer is a semiconductor device, characterized in that the quantum well region. The method according to any one of claims 17 to 22, 25 and 26, And further comprising a source / drain contact layer made of a low resistance conductor film formed directly above the Si _1-xy Ge _x C _y layer formed on the upper side of the first and second Si _1-xy Ge _x C _y layers. A semiconductor device, characterized in that. The method of claim 23, And further comprising a source / drain contact layer made of a low resistance conductor film formed directly above the Si _1-xy Ge _x C _y layer formed on the upper side of the first and second Si _1-xy Ge _x C _y layers. A semiconductor device, characterized in that. The method of claim 24, And further comprising a source / drain contact layer made of a low resistance conductor film formed directly above the Si _1-xy Ge _x C _y layer formed on the upper side of the first and second Si _1-xy Ge _x C _y layers. A semiconductor device, characterized in that. A semiconductor device comprising at least one field effect transistor formed on a semiconductor substrate, The field effect transistor, A first semiconductor layer comprising a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ _y ≦ 1), and a second semiconductor layer composed of a semiconductor having a band gap different from that of the first semiconductor layer. And a channel region having a carrier accumulation layer formed in an area near an interface between the first and second semiconductor layers. A source / drain region having a third semiconductor layer and a fourth semiconductor layer composed of a semiconductor having a larger band gap than the third semiconductor layer; A semiconductor device comprising: a source-drain contact layer made of a low resistance conductor film formed directly on the third semiconductor layer. The method of claim 30, The first semiconductor layer and the third semiconductor layer are composed of a common first semiconductor film, The second semiconductor layer and the fourth semiconductor are composed of a common second semiconductor film, And the second semiconductor film is formed over the first semiconductor film. The method of claim 30, The first semiconductor layer and the third semiconductor layer are composed of different semiconductor films, The third semiconductor layer is formed above the first semiconductor layer, And the fourth semiconductor layer is formed on the third semiconductor layer. In the method of manufacturing a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor, A first carrier layer having a first Si layer and a first carrier storage layer serving as a channel of the n-channel field effect transistor in a region proximate to the first Si layer and adjacent to the Si layer; A first step of forming a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ l, Oy ≦ 1), On the semiconductor substrate, the second Si layer is adjacent to the second Si layer and has a band gap different from that of the first Si _1-xy Ge _x C _y layer. A second Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1) having a second carrier storage layer serving as a channel of the p-channel field effect transistor in an adjacent region; 2 processes, After depositing a conductor film on the Si _1-xy Ge _x C _y layer positioned above the first and second Si _1-xy Ge _x C _y layers, the conductor film is patterned to form the n-channel field effect transistor. And a third step of forming gate electrodes of the p-channel field effect transistor, respectively; Using the gate electrode of each transistor as a mask, at least n-type impurities are formed in the n-channel field effect transistor formation region to a depth reaching the first carrier storage layer, and at least in the p-channel field effect transistor formation region. And a fourth step of introducing p-type impurities to the depth reaching the second carrier storage layer and forming source and drain regions of the n-channel field effect transistor and the p-channel field effect transistor, respectively. A semiconductor device manufacturing method characterized by the above-mentioned. A first semiconductor layer comprising a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1,0 ≦ _y ≦ 1), a second semiconductor layer having a different band gap from the first semiconductor layer, and In the manufacturing method of the semiconductor device which has a carrier accumulation layer which becomes a channel formed in the area | region near the interface surface between a 1st, 2nd semiconductor layer, and functions as a field effect transistor, A first step of sequentially forming a third semiconductor layer and a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer in the field effect transistor formation region of the semiconductor substrate, A second step of depositing a conductor film on the fourth semiconductor layer, and then patterning the conductor film to form a gate film; A third step of forming a source / drain region by introducing impurities into the field-effect transistor formation region located on both sides of the gate electrode to a depth reaching at least the carrier storage layer; A fourth step of removing the fourth semiconductor layer in the source / drain region by etching until at least the third semiconductor layer is exposed, and And a fifth step of forming a source / drain contact layer made of a low resistance conductor film on the surface where the third semiconductor layer is exposed. The method of claim 34, wherein In the first step, the first and third semiconductor layers are configured with a common first semiconductor film, and the second and fourth semiconductor layers are configured with a common second semiconductor film. Manufacturing method. The method of claim 34, wherein Further comprising the step of forming the first and second semiconductor layers before the first step, The first step is performed to form a third semiconductor layer above the first semiconductor layer. The method according to any one of claims 34 to 36, The fourth step is a method of manufacturing a semiconductor device, characterized in that the etching conditions with a high etching selectivity with respect to the third semiconductor layer and the fourth semiconductor layer.