KR100495543B1 - Semiconductor device and method of producing the same - Google Patents

Abstract

In order to provide a semiconductor device having a field effect transistor having a high carrier mobility and a channel with few crystal defects, in the NMOS transistor on the Si substrate 10, the Si layer 13n and the SiGeC layer 14n are Formed. The carrier accumulation layer using the discontinuity of the conduction band existing in the hetero interface between the SiGeC layer 14n and the Si layer 13n is formed, and electrons travel as the channel, and the SiGeC layer 14n is formed of silicon. The mobility of electrons and the operating speed of the NMOS transistor are also increased compared to the channel, and the channel through which the hole of the PM0S transistor travels is formed by using discontinuities in the valence band generated at the interface between the SiGe layer 15p and the Si layer 17p. Since the SiGe layer is formed, the mobility of holes is larger than that of the Si layer, and the operation speed of the PMOS transistor is also increased.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME}

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a heterojunction field effect transistor using a SiGeC layer or a SiGe layer, and a manufacturing method thereof.

In recent years, high integration of semiconductor devices has been progressed, but in ultra-fine regions such as the miniaturization gate length of the M0S-type transistors being less than 0.1 µm, the current drive capability is increased due to the effect of a short channel effect or an increase in the resistance component. It is anticipated that such a performance improvement cannot be expected until now, such as being saturated. In particular, in order to increase the driving force of the fine M0S transistor, it is important to improve the carrier mobility of the channel and to reduce the resistance of the contact of the source and drain electrodes.

Therefore, instead of the complementary semiconductor device (CMOS device) using a single composition of Si formed on a silicon substrate, a heterostructure CMOS device (Heterostructure CMOS: hereinafter referred to as HCMOS device) by Si / SiGe system (Group IV mixed crystal) Is proposed. This is not the Si / SiO ₂ interface but the interface of the heterojunction by two kinds of semiconductors having different band gaps as the channel. It is expected that even higher speed devices can be realized by using a Si / SiGe system that gives higher carrier mobility than such Si. In this Si / SiGe system, it is possible to form an epitaxial growth layer having a desired amount of distortion and a band gap value on the Si substrate by controlling the composition. IBM's Ismail is conducting basic experiments on the improvement of characteristics by Si / SiGe-based HCMOS devices (K. Ismail, "Si / SiGe High Speed Field-Effect Transistors", IEDM Tech. Dig. 1995. p509. See MA Armstrong et al, "Design of Si / SiGe Heterojunction Complementary Metal-Oxide-Semiconductor Transistors" IEDM Tech.Dig. 1995, p701).

15 is a cross-sectional view showing an example of this HCMOS device. As shown in FIG. 15, a part of the Si substrate 101 is provided with a field effect transistor composed of a source / drain region 109, a gate insulating film 107, and a gate electrode 110 thereon. In the so-called channel region between the source region and the drain region under the gate electrode 110, the SiGe buffer layer 102, the δ doping layer 115, the spacer layer 103, and the i-Si layer ( 104, an i-SiGe layer 105 and an i-Si layer 106 are formed. In these regions, the SiGe buffer layer 102 is formed on the i-Si layer 104 to form an n-channel layer 112 between the i-Si layer 104 and the i-SiGe layer 105. It gives tensile distortion. In this SiGe buffer layer 102, the composition ratio is changed in stages so that the Ge composition ratio becomes 0% immediately above the Si substrate 101, and the Ge composition ratio becomes 30% at the top.

Here, when a negative bias is applied, the n-channel layer 112 is formed at the hetero interface with the SiGe buffer layer 102 below in the i-Si layer 104. The δ doping layer 115 supplies electrons as carriers to the n-channel layer 112 formed thereon. In addition, the spacer layer 103 spatially separates the ions of the δ doped layer 115 formed downward and the upper n-channel layer 112 to prevent a decrease in mobility due to ion scattering of the carrier.

When a positive bias is applied, the p-channel layer 111 is formed in the hetero interface with the i-Si layer 106 in the i-SiGe layer 105. The gate insulating film 107 is for insulating the gate electrode 110 and the p-channel layer 111.

As described above, in the hetero field effect transistor, a channel is formed in a hetero interface between two kinds of semiconductor layers having different band gaps. Therefore, at least two kinds of semiconductor layers having different band gaps exist for channel formation. In addition, in order to form a channel for moving electrons or holes at high speed in the semiconductor layer, it is necessary to have discontinuities in the conduction band or the valence band at the hetero interface. In the above-described Si / SiGe system, since the SiGe layer 105 has a discontinuity in the valence band with respect to the i-Si layer 106 with respect to the holes, a channel for holes is formed (see the left part of FIG. 15). ). However, since there are few discontinuities in the conduction band, by applying tensile distortion to the i-Si layer 104 to form channels for electrons, discontinuities in the conduction band are formed at the hetero interface with the i-SiGe layer 105. (See right side of FIG. 15).

The results of the simulation show that the HCMOS device having such a structure can realize twice the high-speed operation with the same processing dimensions with 1/2 the power consumption as compared with the conventional CMOS device using the Si / Si0 ₂ channel. It is expected. That is, a semiconductor device in which a hetero interface is formed by combining a Si semiconductor and a SiGe mixed crystal, and a channel having high mobility is formed, which realizes both high-speed operation of a device using a heterojunction and large-scale integration of a M0S device. As very attracting attention.

However, hetero-devices using group IV mixed crystals such as SiGe as described above are expected to be greatly overcome as a method of overcoming the performance limitations of conventional CM0S devices. Due to the difficulty in manufacturing, the research and development are delayed compared to the heterobipolar transistor, which is a hetero device using the same SiGe mixed crystal, and the structure and the manufacturing method are sufficiently studied to sufficiently exhibit the expected performance. Can't. In addition, among the hetero field effect transistors, in the case of the so-called hetero MOS structure having an insulating film between the gate electrode and the semiconductor layer as described above, since a good insulating film can be formed in the SiGe layer with good stability, SiO ₂ is used as the gate insulating film. An oxide film formed is used. Therefore, the Si layer must be immediately below the gate insulating film, but Si has a feature that the band gap is larger than that of SiGe.

Therefore, in the structure of the said conventional HCMOS apparatus, there existed the following problems.

First, in order to form an electron channel on the Si substrate 101 as described above, tensile distortion is applied to the i-Si layer 104 to form a band discontinuity on the Si / SiGe hetero interface. However, by changing the lattice constant, dislocations due to lattice relaxation occur.

16 is a cross-sectional view showing the SiGe buffer layer 102 and the i-Si layer 104 thereon separately. Since the i-Si layer 104 has a smaller lattice constant than the SiGe buffer layer 102, tensile strain is accumulated in the crystal growth step. As the accumulation of this distortion increases, a potential is input to the i-Si layer 104 as shown in FIG. 16. As such, the introduction of dislocations or defects due to lattice mismatch distortion between the i-Si layer 104 and the SiGe buffer layer 102 is unavoidable. Therefore, the initial characteristic of the element using this crystal is considered to have the effect of deterioration of characteristics due to dislocation propagation from the viewpoint of reliability and lifetime.

Further, a SiGe buffer layer 102 made of SiGe having a lattice constant larger than Si is laminated on the Si substrate 101, and tensile strain is accumulated in the i-Si layer 104 growing thereon, but the SiGe buffer layer 102 is formed. ), The lattice constant of the SiGe buffer layer 102 exceeds the critical film thickness that changes from the lattice constant of Si to the lattice constant of the original SiGe in the meantime, so that lattice relaxation occurs and the SiGe buffer layer 102 ), Defects such as dislocations are also introduced.

Although these defects may have little influence on the initial characteristics of the device, they may cause serious problems in terms of long-term reliability and lifetime. That is, there is a fear that a proliferation of defects caused by current or deterioration due to diffusion through defects of metals or impurities may occur, resulting in a decrease in reliability.

A first object of the present invention is to provide carrier mobility by using lattice matching or near lattice matching heterojunctions having a band discontinuity capable of forming a carrier accumulation layer as a structure in the channel region under the gate of the HCMOS device. The present invention provides a semiconductor device with high reliability and high reliability.

Secondly, the hetero field effect device using group IV mixed crystal represented by SiGe is an effective technique as an element structure that overcomes the performance limitations of the conventional fine CM0S device, but at present the source and drain compared to the study of improving channel mobility. The examination of the optimization of the contact of an electrode is further inadequate, and does not have the structure which fully utilizes the high mobility. Although the above-described technology of the hetero CMOS device by IBM Corp. has been examined in detail in improving the mobility of the channel region, the contact resistance of the source and drain electrodes, which is another important factor for improving the performance of the fine transistor, has been reduced. Almost no research has been carried out.

That is, in the CM0S device structure using Si single crystal, various studies have been made in the structure of the contact area on the substrate side connected to the source and drain electrodes, but the structure of the optimal contact area in the general CM0S device and It is necessary to examine whether the formation method is the best even for heterofield effect devices having different device structures.

It is a second object of the present invention to provide a semiconductor device having a contact region capable of exerting a small contact resistance without impairing the excellent properties of the heterofield effector, and a manufacturing method thereof.

In order to achieve the first object, the present invention seeks means for a first semiconductor device, means for a second semiconductor device, and means for a method for manufacturing the first semiconductor device.

MEANS TO SOLVE THE PROBLEM In order to achieve the said 2nd objective, in this invention, the means regarding a 3rd semiconductor device and the means regarding the manufacturing method of a 2nd semiconductor device are calculated | required.

A first semiconductor device of the present invention is a semiconductor device which is formed in a part of a semiconductor substrate and includes a field effect transistor having a channel region between a gate electrode and a source / drain region and a corresponding source / drain region. A Si layer and a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0y ≦ 1) formed in contact with the Si layer and having a composition ratio y of 0.01 to 0.03 are provided, and Si _1-xy Ge _x The carrier accumulation layer is formed in the region adjacent to the Si layer in the C _y layer.

Accordingly, it is possible to form a band discontinuity necessary to form a carrier accumulation layer that confines the carrier two-dimensionally at the interface between the Si _1-xy Ge _x C _y layer and the Si layer having a composition ratio y of 0.01 to 0.03. Do. And since this carrier accumulation layer functions as a channel, the field effect transistor with a large operation speed which makes a channel the Si _1-xy Ge _{x Cy} layer which gives carrier mobility larger than a Si layer can be obtained. Moreover, Si _1-xy Ge _x C _y layer and in between the Si layer because it can be controlled such that no lattice mismatch or or extremely small, it is possible to adjust the lattice strain of 0 or nearly so, Si _1-xy Ge _x C _y It is possible to configure so that crystal defects may not be introduced into the layer. Therefore, a semiconductor device having high reliability can be obtained.

In addition, the composition ratio of the Si _1-xy Ge _x C _y layer of each element may be placed to adjust the composition ratio of the lattice matching said Si _1-xy Ge _x C _y layer and the Si layer.

As a result, a channel is formed in the Si _1-xy Ge _x C _y layer without distortion due to lattice mismatch, and thus a semiconductor device having very high reliability can be obtained.

Further, the Si _1-xy Ge _x C _y layer may have a lattice constant smaller than that of the Si layer and a film thickness that does not cause lattice relaxation.

As a result, tensile strain is applied to the Si _1-xy Ge _x C _y layer, so that the amount of discontinuity of the band with the Si layer can be increased, thereby improving the efficiency of trapping the carrier.

In addition, the semiconductor substrate may further include a M0S transistor formed on the semiconductor substrate and having a single layer semiconductor layer as a channel region.

Further, carriers accumulated in the carrier storage layer can be negative carriers.

In addition, it is preferable to provide a carrier supply layer for supplying a carrier to the carrier accumulation layer in a region adjacent to the Si _1-xy Ge _x C _y layer in the Si layer.

In addition, another carrier field is formed in another part of the semiconductor substrate, with the carrier accumulated in the carrier storage layer as a negative carrier, and having a gate electrode, a source / drain region, and a channel region between the source / drain region. An effect transistor is further provided, and a second Si layer and a SiGe layer formed proximate to the second Si layer are provided in a channel region of the other field effect transistor, and the second Si layer in the SiGe is provided. It is preferable to form the second carrier storage layer for accumulating the positive carriers in the region adjacent to the second carrier.

Thereby, a semiconductor device functioning as an HCMOS device having high carrier movement can be obtained in either of the n-channel side and the p-channel side.

The Si _1-xy Ge _x C _y layer may be a quantum well region, and the SiGe layer may be a quantum well region.

As a result, it is possible to obtain a field effect transistor having a channel having a high efficiency of confining carriers.

A source comprising a first semiconductor layer and a second semiconductor layer having a band gap larger than that of the first semiconductor layer in the source / drain region, and having a low resistance conductor film formed directly on the first semiconductor layer. Drain contact layer can be provided.

Thereby, in addition to the above effects, a semiconductor device with a small contact resistance can be obtained while using a heterojunction.

A second semiconductor device of the present invention is formed in a part of a semiconductor substrate, and includes a field effect transistor having a gate electrode, a source / drain region, and a channel region between the source / drain region, and in the channel region, A first Si layer, a first Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 <y ≦ 1) formed in contact with the Si layer, a second Si layer, and the second Si layer contact is formed, and wherein the _{1 Si 1-xy Ge x C} y layer and has claim _{2 Si 1-xy Ge x C} y layer having different band gaps (0≤x≤1, 0≤y≤1) is provided, wherein the 1 Si _1-xy Ge _x C _y layer and the region close to the claim 1 Si layer within, and the second Si and the second area close to the Si layer in the _1-xy Ge _x C _y layer, First and second carrier storage layers are formed for confining carriers of different conductivity types, respectively.

As a result, it is possible to obtain a semiconductor device which functions as an HCMOS device having an n-channel field effect transistor and a p-channel field effect transistor each having a high efficiency of channel confining carriers and having a large operation speed. Furthermore, crystallization defects in the first Si _1-xy Ge _x C _y layer can be controlled such that there is no lattice mismatch or very little between the first Si _1-xy Ge _x C _y layer and the first Si layer. It is possible to configure so that it is not introduced. Therefore, a semiconductor device having high reliability can be obtained.

In addition, the composition ratio y of C in the said 2nd Si _1-xy Ge _x C _y layer can be made into zero.

In addition, a M0S transistor may be further formed on the semiconductor substrate, the semiconductor layer having a single composition as a channel region.

Accordingly, a transistor having the first Si _1-xy Ge _x C _y layer as a channel region is disposed in a portion where an operation speed is required, and a general M0S transistor is disposed in a portion other than the above, thereby limiting the application range of the semiconductor device. You can enlarge it.

Moreover, it is preferable to make composition ratio y of C in the said 1st Si _1-xy Ge _{x Cy} layer into 0.01-0.03.

Moreover, it is preferable to adjust the composition ratio of each element of the said 1st Si _1-xy Ge _x C _y layer to the composition ratio which the said 1st Si _1-xy Ge _x C _y and the said 1st Si layer lattice matched.

As a result, a semiconductor device having a highly reliable field effect transistor without lattice distortion can be obtained.

The first Si _1-xy Ge _x C _y layer may have a lattice constant smaller than the lattice constant of the first Si layer and a film thickness that does not cause lattice relaxation.

As a result, tensile strain is applied to the first Si _1-xy Ge _x C _y layer, so that the amount of band discontinuity between the first Si layer can be increased and the efficiency of trapping the carrier is improved.

In addition, it is preferable that the carrier accumulated in the first carrier storage layer be a negative carrier, and the carrier accumulated in the second carrier storage layer be a positive carrier.

In addition, it is preferable to further form a carrier supply layer for supplying a carrier to the first carrier accumulation layer in a region proximate to the first Si _1-xy Ge _x C _y layer in the first Si layer.

In addition, at least one of the first and second Si _1-xy Ge _x C _y layers, Si _1-xy Ge _x C _y is preferably a quantum well region.

Further, a source-drain contact layer made of a low resistance conductor film formed directly on the Si _1-xy Ge _x C _y layer formed on the upper side of the first and second Si _1-xy Ge _x C _y layers is further provided. It is desirable to.

A third semiconductor device of the present invention is a semiconductor device having at least one field effect transistor formed on a semiconductor substrate, the field effect transistor comprising a Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1, 0 A first semiconductor layer comprising ≤ y ≤ 1), a second semiconductor layer formed of a semiconductor having a band gap different from the first semiconductor layer, and formed in a region near an interface between the first and second semiconductor layers A source / drain region having a channel region having a carrier storage layer, a third semiconductor layer and a fourth semiconductor layer composed of a semiconductor layer having a band gap larger than that of the third semiconductor layer, and directly above the third semiconductor layer. A source / drain contact layer made of a low resistance conductor film is provided.

As a result, it is possible to reduce the contact resistance to the source / drain region in the field effect transistor having a high carrier movement using a heterojunction, that is, a high operating speed.

In addition, the first semiconductor layer and the third semiconductor layer are formed by a common first semiconductor film, and the second semiconductor layer and the fourth semiconductor layer are formed by a common second semiconductor film. 2 A semiconductor film can be formed on the said 1st semiconductor film.

The first semiconductor layer and the third semiconductor layer are formed of different semiconductor films, the third semiconductor layer is formed above the first semiconductor layer, and the fourth semiconductor layer is formed of the third semiconductor layer. Can be formed on top of the layer.

The manufacturing method of the 1st semiconductor device of this invention is a manufacturing method of the semiconductor device which has an n-channel field effect transistor and a p-channel field effect transistor, Comprising: A 1st Si layer and the said Si layer on a semiconductor substrate A first Si _1-xy Ge _x C _y layer (0 ≦ _x ≦ 1, 0, having a first carrier layer in the region adjacent to the first Si layer and at the same time as the channel of the n-channel field-effect transistor) A first step of forming <y≤1), a second Si layer and a second Si layer on the semiconductor substrate, and a band gap different from the first Si _1-xy Ge _x C _y layer; A second Si _1-xy Ge _x C _y layer having a second carrier storage layer serving as a channel of the p-channel field effect transistor in a region proximate the second Si layer (0 ≦ x ≦ 1, 0 ≦ y on top of the second step, the first and second Si _1-xy Ge _x C _y layer which is located on top of the Si _1-xy Ge _x C _y layer to form a ≤1) Fig. After depositing a film, patterning the conductor film to form gate electrodes of the n-channel field effect transistor and the p-channel field effect transistor, respectively; using the gate electrode of each transistor as a mask, n-type impurity to at least the depth reaching the first carrier storage layer in the n-channel field effect transistor formation region, and at least to the depth to reach the second carrier storage layer in the p-channel field effect transistor formation region. and a fourth step of forming source and drain regions of the n-channel field effect transistor and the p-channel field effect transistor, respectively, by introducing p-type impurities.

By this method, the second semiconductor device according to the present invention can be easily formed.

A method for manufacturing a second semiconductor device of the present invention includes a first semiconductor layer including a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ _y ≦ 1), and the first semiconductor layer. A semiconductor manufacturing method of a semiconductor device having a second semiconductor layer having a different band gap and a carrier storage layer serving as a channel formed in a region near an interface between the first and second semiconductor layers, and functioning as a field effect transistor. A first step of sequentially forming a third semiconductor layer and a fourth semiconductor layer having a larger band gap than the third semiconductor layer in the field effect transistor formation region of the substrate; and depositing a semiconductor film on the fourth semiconductor layer. Thereafter, the conductive film is patterned to form a gate electrode, and impurities are introduced into the field-effect transistor formation regions located on both sides of the gate electrode to at least a depth reaching the carrier storage layer. A third step of forming a source / drain region, a fourth step of removing the fourth semiconductor layer in the source / drain region by etching until at least the third semiconductor layer is exposed, and the third A fifth step of forming a source / drain contact layer made of a low resistance conductor film on a surface where the semiconductor layer is exposed is provided.

By this method, it is possible to easily form the third semiconductor device according to the present invention.

In the first step, the first and third semiconductor layers may be formed of a common first semiconductor film, and the second and fourth semiconductor layers may be formed of a common second semiconductor film.

The method may further include a step of forming the first and second semiconductor layers in front of the first step, wherein the first step allows the third semiconductor layer to be formed above the first semiconductor layer. .

Moreover, it is preferable to make the said 4th process into the etching conditions with high etching selectivity with respect to the said 3rd semiconductor layer and the said 4th semiconductor layer.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

(Example)

(First embodiment)

The HCMOS device according to the first embodiment employs a SiGeC ternary mixed crystal system in which C is added to a SiGe / Si system, and lattice-matches the SiGeC layer and the Si layer to form a hetero boundary surface from a difference in band gap energy. It is a field effect transistor which forms a band discontinuity in.

1 is a cross-sectional view showing the structure of the HCMOS device according to the first embodiment. As shown in FIG. 1, an NMOS transistor and a PMOS transistor are formed on the silicon substrate 10, but first, the structure of the NMOS transistor will be described.

In an NMOS transistor, a p well 11 (a high concentration p-type silicon layer) is formed on a Si substrate 10, and a Si layer having a δ doping layer and a spacer layer doped with a high concentration of a group V element thereon ( 13n) and a SiGeC layer 14n (the composition ratio of C is 1%, and the composition ratio of Ge is 8.2%) are formed in this order. As will be described later, the composition ratio of each element in the SiGeC layer 14n is a value at which the SiGeC layer 14n and the Si layer 13n immediately below are lattice matched.

In the hetero interface between the SiGeC layer 14n and the Si layer 13n, a band discontinuity of the conduction band Ec having a band offset value ΔEc exists as shown in the right part of FIG. A carrier accumulation layer for confining electrons as carriers of the film i) as two-dimensional electron gas (2 DEG) is formed. The carrier accumulation layer formed near the boundary surface on the SiGeC layer 14n side is a channel through which electrons travel at high speed. In the SiGeC layer 14n, the mobility of electrons is larger than that in the Si layer, and the operating speed of the NMOS transistor can also be increased.

On this SiGeC layer 14n, a SiGe layer 15n (a composition ratio of Ge is 30%, a composition ratio of Si is 70%) and a Si layer 17n are formed in this order, and the surface is made of a silicon oxide film. The gate insulating film 19n is formed. Since the Si layer 17n exists below this gate insulating film 19n, the gate insulating film 19n with high crystallinity can be easily formed only by oxidizing the surface of the Si layer 17n. The gate electrode 18n is formed on the gate insulating film 19n, and the source / drain layer 16n is formed in the board | substrate located on both sides of this gate electrode 18n. The travel of electrons in the SiGeC layer 14n is controlled by the voltage applied to the gate electrode 18n. In addition, although the source-drain layer 16n is formed to the depth which reaches | attains the p well 11, what is necessary is just to form to the depth of the part used as the channel formed in the SiGeC layer 14n at least.

On the other hand, the PMOS transistor has a structure substantially the same as that of the NMOS transistor described above. An n well 12 (a high-strength n-type Si layer) is formed on the Si substrate 10, and a Si layer 13p having a δ doping layer doped with a Group V element at a high concentration, and a SiGeC layer 14p. (Ge composition rate is 8.2%, C composition rate is 1%) are formed in this order. On this SiGeC layer 14p, a SiGe layer 15p (a composition ratio of Ge is 30%, a composition ratio of Si is 70%), and a Si layer 17p are formed in this order. In the case of a PMOS transistor, the carrier becomes a hole, but the channel through which the hole flows is formed on the SiGe layer 15p side of the interface between the SiGe layer 15p and the Si layer 17p. A band discontinuity in the valence band having a band offset value ΔEv exists in the hetero interface between the SiGe layer 15p and the Si layer 17p, and a carrier accumulation layer is formed in this discontinuous portion. Therefore, although holes travel through the carrier accumulation layer channel formed at the interface on the SiGe layer 15p side, even in the SiGe layer 15p, since the hole mobility is larger than that in the Si layer, the operation speed of the PM0S transistor also increases.

In the PMOS transistor, a gate insulating film 19p made of a silicon oxide film is formed on the Si layer 17p. Source and drain layers 16p are formed on both sides of the gate electrode 18p, and the travel of the holes in the SiGe layer 15p is controlled by the voltage applied to the gate electrode 18p.

In addition, a trench isolation 20 is formed between the NMOS transistor and the PMOS transistor by filling a groove formed in the substrate with a silicon oxide film. The trench isolation 20 allows the NMOS transistor and the PMOS transistor to be electrically connected to each other. Separated by.

In addition, each Si layer 13n, 13p, each SiGeC layer 14p, 14n, each SiGe layer 15n, 15p, and each Si layer 17n, 17p are formed simultaneously by crystal growth. In addition, the dimension of each layer can be made into the following dimensions, for example. However, the present invention is not necessarily limited to the following dimensions.

The thickness of each Si layer 13n, 13p is about 0.6 micrometer, for example, and it is preferable to exist in the range of 0-1 micrometer. The thickness of a spacer layer is about 30 nm, for example, and it is preferable to exist in the range of 0-50 nm. It is preferable that the thickness of each SiGeC layer 14p, 14n is 3-50 nm. The thickness of each SiGe layer 15n, 15p is about 5 nm, and it is preferable to exist in the range of 3-5 nm. The thickness of each Si layer 17n, 17p is about 1 nm, and it is preferable to exist in the range of 0.5-5 nm. The thickness of the gate insulating films 19n and 19p is, for example, about 5 nm.

The gate lengths of the gate electrodes 18n and 18p are 0.25 µm, the gate width is 2.5 µm, the width of the source and drain regions is about 1.2 µm, and the contact areas of the source and drain electrodes 21n and 21p are 0.5 µm. It is about 0.6 micrometer. The doping concentration of each well 13n, 13p is about 1 × 10 ¹⁷ -1 × 10 ¹⁸ cm ^-3 , and the doping concentration of the δ doping layer is about 1 × 10 ¹⁸ -1 × 10 ²⁰ cm ^-3 .

The characteristic of the HCMOS device (Heterostructure CMOS device) in this embodiment is that a SiGeC layer is used. This SiGeC layer can change the band gap amount and the lattice mismatch rate with respect to silicon by adjusting the composition ratio of Si, Ge, and C, respectively. Here, the relationship between the composition ratios of Si, Ge, and C in the present embodiment, and the amount of distortion and band offset of each layer will be described in detail.

2 shows the lattice mismatch (%) of the SiGeC layer and the Si layer when the composition ratio (%) of C (carbon) on the horizontal axis and the composition ratio (%) of Ge on the vertical axis are changed. A line with zero lattice mismatch indicates that the lattice constants of the SiGeC layer and the Si layer are the same. Since the lattice constant of the Ge (germanium) single crystal is larger than the lattice constant of the Si single crystal, and the lattice constant of the C (carbon) single crystal is smaller than the lattice constant of the Si single crystal, the lattice of the SiGeC layer 14n is adjusted by adjusting the composition ratio of Ge and C. It is possible to match the constant with the lattice constant of the Si layer 13n.

Fig. 3 is a characteristic diagram showing the relationship of lattice matching to the composition ratio of three elements of Si, Ge, and C. The three vertices of FIG. 3 are points at which the composition ratios of Si, Ge, and C are 100% (composition ratio 1), and the lattice mismatch rate with Si is changed by adjusting the composition ratio of the ternary mixed crystal system of the SiGeC layer. It is showing. In Fig. 3, the hatching area represents a region of the composition ratio giving tensile strain to the SiGeC layer, and the solid line in Fig. 3 represents the condition of the composition ratio of each element for the lattice mismatch between the SiGeC layer and the Si layer to be zero, that is, both. . Since the lattice constant of Ge is 4.2% larger than the lattice constant of Si and the lattice constant of C is 34.3% smaller than the lattice constant of Si, the lattice constant of the SiGeC layer is increased by 8.2 times larger than that of C. Can match the lattice constant.

In the SiGeC layer 14n of this embodiment, the composition ratio of Ge is 8.2% (x = 0.082), and the composition ratio of C is 1% (y = 0.01), so that the lattice mismatch with the Si substrate is zero than in FIG. 3. It is understood that the SiGeC layer 14n and the lower Si layer 13n have the same lattice constant.

4 shows the band offset value ΔEc of the conduction band and the band offset value ΔEv of the valence band at the interface between the SiGeC layer and the Si layer when the horizontal axis is the composition ratio of C and the vertical axis is the energy level. The form is shown. However, the black circle represents the band offset value ΔEv of the valence band, and the white circle represents the band offset value ΔEc of the conduction band. The origin of energy is taken as the energy value at the bottom of the conduction band of Si for the conduction band, and the energy value at the top of the valence band of Si for the valence band. In addition, the solid line of FIG. 4 corresponds to a distortion-free system, and the dotted line of FIG. 4 corresponds to a tensile distortion system.

As shown in Fig. 4, the band offset values of the conduction band and the valence band at the interface between the SiGeC layer (the composition ratio of C is 0.01) and the Si layer of this embodiment are 300 meV and 0 meV, respectively, and the SiGeC layer and the Si layer As the interface, it can be seen that there is no band discontinuity in the valence band and only a band discontinuity is formed in the conduction band. In addition, since the composition ratio of C in the SiGeC layer 14n of this embodiment is 0.01, the SiGeC layer 14n and the Si layer 13n are lattice matched. Therefore, it is possible to prevent the occurrence of defects such as dislocations due to lattice mismatch with the underlying Si layer 13n in the SiGeC layer 14n where the channel on which the two-dimensional electron gas travels is formed.

On the other hand, since there is no band discontinuity in the valence band at the interface between the SiGeC layer 14n and the Si layer 13n in this embodiment, holes cannot be trapped in the SiGeC layer 14n. Therefore, in the case of a PM0S transistor having holes as a carrier, a heterojunction of the SiGe layer 15p and the Si layer 17p is used. The lattice constant of the SiGe single crystal is larger than the lattice constant of the Si single crystal, and furthermore, since the SiGe layer 15p is located on the SiGeC layer 14p lattice matched with the Si layer 13p, the change in the band structure due to compression distortion As a result, the band offset value in the valence band is increasing. Also in this case, when the electric field is applied from the gate, holes are trapped two-dimensionally due to the inclination of the band (2DHG) to form a carrier accumulation layer. Therefore, the carrier accumulation layer in the SiGe layer 15p becomes a channel for holes to travel at high speed.

As described above, according to the structure of the present embodiment, in the NMOS transistor, the band offset value of the conduction band is sufficient to accumulate the two-dimensional electron gas by adjusting the composition ratio of each element Si, Ge, C in the SiGeC layer 14n. While maintaining the value, lattice matching between the SiGeC layer and the Si layer can be achieved. Therefore, it is possible to achieve high reliability by reducing the defect density while realizing a high speed of operation using the high carrier mobility of the two-dimensional electron gas in the SiGeC layer. Further, since there is no band discontinuity in the valence band at the interface between the SiGeC layer 14n and the Si layer 13n, holes cannot be trapped in the SiGeC layer 14n, but the SiGe layer 15p and the Si layer 17p are not included. By using a heterojunction, the channel of the PM0S transistor using holes as a carrier can be formed, and high speed operation can be realized.

High-performance HCMOS devices can be realized by integrating high speed NMOS transistors and band discontinuities in the valence band using SiGe and integrating high speed PM0S transistors.

In addition, in the present embodiment, the composition ratio of Ge is 8.2% and the composition ratio of C is 1%. However, in order to make the band discontinuity, i.e., the band offset value ΔEv, largest in the lattice matching system from FIG. It can be seen that if you increase the. By setting such a large band offset value ΔEv, the two-dimensional electron gas (2DEG) trapped in the hetero boundary surface can travel stably without crossing the hetero boundary surface even if the electron concentration becomes high. In particular, it is preferable to adjust the composition ratio of C to the range of 0.01-0.03. Within this range, a band offset value ΔEv (= −0.2 to −0.6 eV) suitable for forming a carrier accumulation layer for confining the two-dimensional electron gas can be obtained in either the distortionless system or the tensile distortion system.

In this embodiment, the composition ratio of Ge in the SiGe layer 15p is set to 30%. However, the composition ratio of Ge may be increased and the compression distortion may be increased so that the band offset value is the largest.

In addition, since the HCMOS device is formed on the Si substrate, the HCMOS device may be used where the speed of the device is required, and in addition, the CM0S device formed on the active region having a normal Si single composition may be manufactured. Such a configuration also enables integration of the MOS field effect transistor directly fabricated on the Si substrate. Moreover, as an apparatus using SiGeC, it is not necessary to form p and n type transistors on the same substrate. For example, in the case of an integrated circuit used in a mobile communication device, an amplifier or a mixer used in a high frequency region requiring high speed operation does not need to configure a complementary circuit, so only one of p and n types (for example, n type) is used. It is conceivable to configure a MOS transistor using SiGeC, and to configure a digital signal processing portion that needs to form a complementary circuit with a CM0S device using a single Si composition.

Next, the manufacturing method of the HCMOS device of the first embodiment will be described with reference to Figs. 5A to 5F. 5 (a) to 5 (f) are cross-sectional views showing an example of a manufacturing process for realizing the structure of the HCMOS device shown in FIG.

First, in the process shown in Fig. 5A, p wells 11 and n wells 12 are formed in the Si substrate 10 by ion implantation.

Next, in each of the wells 11 and 12 in the process shown in FIG. 5 (b), the Si layer 13 including the δ doped layer by the UHV-CVD method, and the SiGeC layer 14 (Ge). : 8.2%, C: 1%), SiGe layer 15, and Si layer 17 are grown, respectively. In addition, the δ doping layer and the spacer layer are also formed, but are omitted in the drawings of these layers for easy viewing.

Next, in the process shown in Fig. 5C, trench isolation trenches are formed to electrically separate the PMOS transistors and the NMOS transistors, and then the trench trenches 20 are filled with a silicon oxide film. To form. By this treatment, the Si layer 13, the SiGeC layer 14, the SiGe layer 15, and the Si layer 17 are respectively the Si layer 13n, the SiGeC layer 14n, and the SiGe layer 15n on the NMOS transistor side. ), The Si layer 17n, and the Si layer 13p on the side of the PMOS transistor, the SiGeC layer 14p, the SiGe layer 15p, and the Si layer 17p. The surfaces of the Si layers 17n and 17p are oxidized to form gate insulating films 19n and 19p, respectively.

Next, a polysilicon film is deposited on the entire surface of the substrate in the process shown in FIG. 5D, and then patterned to form gate electrodes 18n and 18p on the respective gate insulating films 19n and 19p of the NMOS transistor and the PMOS transistor. ) Respectively. Subsequently, the source / drain regions 16n are formed on the NMOS transistor side by implantation of phosphorus ions P + using the gate electrodes 18n and 18p as masks, and on the PM0S transistor side, the boron ions B + are implanted. As a result, source and drain regions 16p are formed, respectively. The depth of the source / drain region 16n of the NMOS transistor may be at least deeper than the carrier accumulation layer in the SiGeC layer 14n, and the depth of the source / drain region 16p of the PMOS transistor may be at least carrier accumulation in the SiGe layer 15p. It is good if it is deeper than a layer. This is because a channel is formed in each carrier storage layer in the SiGeC layer 14n and the SiGe layer 15p.

Next, in the process shown in Fig. 5E, an opening is formed in the upper portion of the source / drain regions 16n and 16p among the gate insulating films 19n and 19p, and shown in Fig. 5F. In this process, source and drain electrodes 21n and 21p are formed in the openings of the gate insulating films 19n and 19p, respectively.

As a result, an HCMOS device including an NMOS transistor and a PMOS transistor is formed on the Si substrate 10.

As described above, according to the manufacturing method of the present embodiment, it is necessary to form another channel in the NMOS transistor and the PMOS transistor, but the crystal growth can be made common to the NM0S transistor and the PM0S transistor, so that it can be easily manufactured.

(Second embodiment)

In the first embodiment described above, the field-effect transistor was formed by using lattice matching of the SiGeC layer to silicon, but in the present embodiment, distortion is actively introduced into the SiGeC layer in the range where there is no deterioration of crystallinity. The transistor using the change of the band structure due to The structure of the HCMOS device according to the present embodiment is basically a structure in which the PM0S transistor and the NMOS transistor according to the first embodiment shown in FIG. 1 are realized in one transistor.

6 (a) to 6 (c) show compressive distortion in the SiGeC layer, lattice matching of the SiGeC layer to the Si layer (no distortion), and tensile strain in the SiGeC layer. It is a figure which shows the state of a crystal structure. As shown in Fig. 6 (a), when the lattice constant of the SiGeC layer is larger than the lattice constant of the Si layer, compressive distortion occurs in the SiGeC layer, resulting in a band gap between the lower end of the conduction band and the upper end of the valence band in the SiGeC layer. The value is expanded. On the other hand, when the lattice constant of the SiGeC layer is smaller than the lattice constant of the Si layer, as shown in Fig. 6C, tensile strain occurs in the SiGeC layer, and the band between the lower end of the conduction band and the upper end of the valence band in the SiGeC layer. The gap is reduced. That is, since the band structure changes due to the distortion of the SiGeC layer, the band offset value of a layer such as a Si layer close to the SiGeC layer can be changed by actively utilizing this effect.

Here, even when the lattice constant of the SiGeC layer is out of the lattice constant of the Si layer, the thickness of the SiGeC layer is such that the lattice relaxation does not occur and distortion is accumulated, thereby reducing the reliability of the device due to the occurrence of crystal defects such as dislocations. It can be prevented efficiently.

7A and 7B are band structure diagrams and cross-sectional views in the channel region of the field effect transistor according to the present embodiment. After growing the Si layer 13n on the Si substrate, the band gap value in the SiGeC layer 14n is grown by growing the SiGeC layer 14n (10% Ge and 4% C) having a larger C composition ratio. It can be set to be large and the lattice constant small. Then, the SiGeC layer 14n is subjected to tensile strain by making the thickness of the SiGeC layer 14n small enough that distortion is accumulated without lattice relaxation. Therefore, in addition to the effect of increasing the band gap value by increasing the composition ratio of C, the band offset of the conduction band at the interface between the SiGeC layer 14n and the Si layer 13n by the tensile strain of the SiGeC layer 14n. The value is increased to improve the efficiency of trapping the two-dimensional electron gas (2 DEG).

In addition, since the SiGeC layer 14n is not lattice relaxed, the lattice constant of the surface coincides with the lattice constant of the Si layer 13n. Therefore, when the SiGe layer 15p is grown on the SiGeC layer 14n, the SiGe layer 15p is subjected to compressive distortion because the lattice constant of the SiGe layer 15p becomes larger than the lattice constant of the Si layer 13n.

Therefore, according to the semiconductor device according to the present embodiment, the tensile strain is introduced into the SiGeC layer 14n and the compression strain is introduced into the SiGe layer 15p, whereby the conduction band at the interface between the SiGeC layer 14n and the Si layer 13n. The band offset value at and the band offset value at the valence band at the interface between the SiGe layer 15p and the Si layer 17p are increased. When the transistor is used as an NMOS transistor, the SiGeC layer 14n is used. In the case of using the channel formed in the P-channel transistor and using the channel formed in the SiGe layer 15p, the HCMOS device having a common gate electrode or source / drain region and having different channel positions can be formed. have.

Furthermore, by appropriately setting the thickness of each layer, an HCMOS device having a highly effective field effect transistor can be obtained without introducing a potential or defect due to lattice mismatch and having good crystallinity.

In addition, the dotted line of FIG. 4 mentioned above has shown a composition so that 0.25% tensile distortion may be added to the SiGeC layer 14n in a present Example. In general, when the composition ratio of Ge in the SiGeC layer is 8.2 times the composition ratio of C, lattice matching is performed on the Si layer. Therefore, tensile strain is introduced into the SiGeC layer 14n by making the composition ratio of Ge smaller than 8.2 times the composition ratio of C. You can do it. When the composition ratio of Ge is set to 8.2y-0.12 when the composition ratio of C is y, the lattice constant of the SiGeC layer 14n can be made 0.25% smaller than the lattice constant of the Si layer 13n.

As shown in FIG. 4, it can be seen that the band discontinuity is not formed in the valence band and only the conduction band is formed at the interface between the SiGeC layer 14n and the Si layer 13n as in the case of the distortion-free system. When the composition ratio of C is less than or equal to 2%, the band offset value of the conduction band is almost the same as that of no distortion, and even if the ratio of the composition ratio of C and the composition ratio of Ge deviates from the value satisfying the conditions of lattice matching, Device characteristics almost equal to the sum can be obtained. This means that the width of the SiGeC layer 14n is kept in this condition in terms of the control of the composition ratio of C and the composition ratio of Ge when the crystal is grown, thereby facilitating crystal growth of the SiGeC layer. In addition, when the composition ratio of C is 2% or more, the band offset value can be increased even at the composition ratio of C as compared with the case of no distortion. This makes it possible to deal with the case where the band offset value is made larger.

Here, although the lattice constant of SiGeC is used smaller than Si, since the layer thickness is a grade which the distortion which lattice relaxation does not generate | occur | produce, reliability of an element does not fall by crystal defects, such as electric potential.

(Third embodiment)

In the first embodiment described above, a heterostructure in which the SiGeC layer is lattice matched to the Si layer in the channel region of the field effect transistor is formed, and electrons or holes are confined in the band discontinuity at the hetero interface and used as a carrier.

In this embodiment, the carrier confinement region forms a quantum well structure having a structure of Si / SiGeC / Si or Si / SiGe / Si instead of a hetero interface, and channels quantum wells (SiGeC, SiGe) that can be pinched as a barrier layer. A transistor acting as is provided.

8 is a sectional view of an HCMOS device according to the present embodiment. It is a CMOS device structure in which an NMOS transistor and a PMOS transistor are formed on a Si substrate 30. In this structure, the first Si layer 33n having the p well 31 and the n well 32 provided on the silicon substrate 30, and the δ doping layer doped with a high concentration of group V elements thereon, 33p) is the same as that of the HCMOS device shown in FIG. 1 in the first embodiment. However, the structures of the PMOS transistors and NMOS transistors on the first Si layers 33n and 33p are different from those of the first embodiment.

In the NMOS transistor, a SiGeC layer 34n having a composition lattice matched to the first Si layer 33n is formed on the first Si layer 33n, and the second Si layer 35n is formed on the SiGeC layer 34n. Is laminated. In this embodiment, the quantum well region (SiGeC layer 34n) narrowed by two band discontinuities in the conduction band spanning the first Si layer 33n-SiGeC layer 34n and the second Si layer 35n. Because of this, a carrier accumulation layer for trapping the two-dimensional electron gas 2 DEG serving as a carrier is formed in the SiGeC layer 34n which is the quantum well region (see also the band on the right side of FIG. 8). In other words, a channel is formed in the SiGeC layer 34n during operation of the NMOS transistor. Further, a small SiGe layer 36n and a third Si layer 37n are sequentially formed on the second Si layer 35n.

By this structure, since the channel for carrier movement is formed in the SiGeC layer 34n having higher electron mobility than the Si layer as in the first embodiment, an NMOS transistor having a high operating speed can be obtained. In addition, since the film thickness of the SiGeC layer 34n serving as the quantum well is small, the efficiency of trapping the carrier is improved over the structure in the first embodiment, so that the mixing crystal ratio can be realized in a system having a small ratio. Therefore, the factor which degrades the mobility of the electron used as a carrier, such as scattering of a carrier resulting from deterioration of the regularity of the crystal structure accompanying mixed crystallization, can be suppressed.

Also in the PMOS transistor, a SiGeC layer 34p having a composition lattice matched to the first Si layer 33p on the first Si layer 33p, a second Si layer 35p, and a SiGe layer 36p having a small film thickness ) And the third Si layer 37p are formed in the same manner as that of the NMOS transistor. However, in the case of the PMOS transistor, in the valence band covering the second Si layer 35p, the SiGe layer 36p, and the third Si layer 37p, the quantum well region (SiGe layer) narrowed at two band discontinuities. (36p)), and a carrier accumulation layer for confining holes, which are carriers, two-dimensionally in this quantum well region is formed. In other words, a channel is formed in the SiGe layer 36p during operation of the PM0S transistor. Since the SiGe layer 36p also has larger hole mobility than the Si layer, the operation speed of this PM0S transistor also increases.

In the NMOS transistors and PMOS transistors, gate insulating films 39n and 39p made of silicon oxide films are formed on the substrate, and gate electrodes 38n and 38p are formed on the gate insulating films 39n and 39p. Source and drain regions 42n and 42p are formed on both sides of the gate electrodes 38n and 38p, and source and drain electrodes 41n and 41p are contacted on the source and drain regions 42n and 42p. Needless to say, in the NMOS transistor and the PMOS transistor, the electron and hole travel in the SiGeC layer 34n and the SiGe layer 36p, which are quantum well regions, are applied to the voltages applied to the gate electrodes 38n and 38p. It is controlled by each.

Further, a trench isolation 40 is formed between the NMOS transistor and the PMOS transistor by filling a silicon oxide film in a separation groove, and the trench isolation 40 electrically separates the NMOS transistor and the PMOS transistor from each other. .

According to the HCMOS device of the present embodiment, in the NMOS transistor as in the first embodiment, a SiGeC layer 34n serving as a quantum well region is formed at the same time as lattice matching to the Si layer, and electrons are formed in the SiGeC layer 34n. A channel for running is formed. Also in the PM0S transistor, a SiGe layer 36p serving as a quantum well region is formed, and a channel through which holes travel is formed in the SiGe layer 36p. Therefore, high performance HCMOS can be realized by integrating a high switching speed NMOS transistor and a PMOS transistor using a highly efficient quantum well structure in which carriers are confined.

In the present embodiment, however, the HCM0S device may be used for a circuit requiring an element speed, and for other circuits, a CM0S device formed on a normal Si substrate may be fabricated and directly formed on the Si substrate. It is also possible to integrate a M0S type field effect transistor.

Note that both the channels of the NMOS transistor and the PMOS transistor do not necessarily have to be a quantum well region.

Next, a method of manufacturing the HCMOS device according to the third embodiment will be described with reference to FIGS. 9A to 9F. 9 (a) to 9 (f) are cross-sectional views showing an example of a manufacturing process for realizing the structure of the HCM0S device shown in FIG.

First, the outline of the manufacturing process will be described. When growing the SiGeC layer 34, the second Si layer 35, and the SiGe layer 36, the film thicknesses of the SiGeC layer 34 and the SiGe layer 36 are both determined. It is 10 nm or less, for example, 3 nm so that it may become a well structure. The other part is formed by the process substantially similar to the process shown to FIG. 5 (a)-(f).

First, in the process shown in FIG. 9A, the p well 31 and the n well 32 are formed in the Si substrate 30 by ion implantation.

In the process shown in FIG. 9B, on the p well 31 and the n well 32, a first Si layer 33 including a δ doped layer by the UHV-CVD method, and a SiGeC layer (34) (Ge: 36%, C: 4%), the second Si layer 35, the SiGe layer 36, and the third Si layer 37 are sequentially grown.

Next, in the process shown in FIG. 9C, trench isolation grooves are formed to electrically separate the PMOS transistors and the NMOS transistors, and then the trenches are filled with a silicon oxide film to form a trench isolation 40. . By this treatment, the first Si layer 33, the SiGeC layer 34, the second Si layer 35, the SiGe layer 36, the third Si layer 37, and the gate insulating film 39 are respectively on the NMOS transistor side. First Si layer 33n, SiGeC layer 34n, second Si layer 35n, SiGe layer 36n, third Si layer 37n and first Si layer 33p on PMOS transistor side, SiGeC Layer 34p, second Si layer 35p, SiGe layer 36p, and third Si layer 37p. Thereafter, the surfaces of the third Si layers 37n and 37p are oxidized to form gate insulating films 39n and 39p.

Next, after the gate electrodes 38n and 38p are formed in the process shown in FIG. 9D, the source / drain regions 42n are formed on the NMOS transistor side by implantation of phosphorus ions P + to form the PMOS. On the transistor side, source and drain regions 42p are formed by implantation of boron ions B +. The depth of the source / drain region 42n of the NMOS transistor may be at least deeper than the SiGeC layer 34n, and the depth of the source / drain region 42p of the PMOS transistor may be at least deeper than the SiGe layer 36p. This is because a channel is formed in the SiGeC layer 34n and the SiGe layer 36p.

Next, in the process shown in Fig. 9E, openings are formed in the gate insulating films 39n and 39p in the upper portions of the source and drain regions 42n and 42p, and in the process shown in Fig. 9F. Source and drain electrodes 41n and 41p are formed in the opening, respectively.

Through the above steps, the structure of the HCMOS device including the NMOS transistor and the PMOS transistor according to the third embodiment is realized.

According to the manufacturing method of this embodiment, HCMOS in which the channel of the NMOS transistor is a SiGeC layer 34n having a quantum well structure using a heterojunction, and the SiGe layer 36p having a quantum well structure using a heterojunction is a channel of the PMOS transistor. The device is easily formed. Moreover, according to the manufacturing method of the present embodiment, different channels must be formed in the NM0S transistor and the PM0S transistor, but the crystal growth can be made common to the NMOS transistor and the PMOS transistor, and thus can be easily manufactured.

(Example 4)

10 is a sectional view showing the structure of the field effect transistor according to the fourth embodiment. This embodiment relates to a structure for providing a source / drain contact suitable for a hetero field effect transistor.

As shown in Fig. 10, on the well 51 made of the Si layer, the SiGe buffer layer 52, the δ doping layer 53, the spacer layer 54, the n-channel layer 67, and i- The Si layer 55, the i-Si _1-x Ge _x layer 56, the i-Si layer 57, and the gate insulating film 58 are formed. A gate electrode 65 is formed on the gate insulating film 58, and a source / drain contact W layer (on the region located on both sides of the gate electrode 65 in the i-Si _1-x Ge _x layer 56) is formed. 61 and Al source-drain electrodes 63 are formed in this order. In addition, a portion of the SiGe buffer layer 52, a δ doping layer 53, a spacer layer 54, an n-channel layer 67, an i-Si layer 55, and an i-Si are formed on both sides of the gate electrode 65. _The source / drain region 59 is formed in the region covering the _1-x Ge _x layer 56 and the i-Si layer 57. In addition, a gap between the gate electrode 65 and the Al source / drain electrode 63 is filled by the insulating film 66 of the first layer.

Here, the structure of each part of the said field effect transistor is demonstrated.

First, the composition ratio of Ge in the SiGe buffer layer 52 is increasing upward. The SiGe buffer layer 52 is formed with a film thickness sufficient to lattice the SiGe mixed crystal, so that the SiGe buffer layer 52 has a lattice constant larger than Si, and the n-channel can be formed thereon using a distortion effect thereon. When heterojunctions of Si and SiGe layers are formed in a lattice match to a Si substrate without using such a lattice relaxed SiGe buffer layer, discontinuous parts with large steps appear in the valence band, but little discontinuities appear in the conduction band. Therefore, it is difficult to form an n-channel by confining the two-dimensional electron gas.

Here, the composition ratio of Ge in the SiGe buffer layer 52 changes continuously, for example, from 0% to 30%, or stepwise for each thin layer. At this time, lattice relaxation occurs in each layer so that the lattice constant in the substrate surface at the uppermost surface of the buffer layer is equal to Si _0.7 Ge _0.3 . The change in the composition ratio in the vertical direction is because the influence of crystal defects such as dislocations due to lattice relaxation on the channel thereon is reduced. In addition, the film thickness of the whole SiGe buffer layer 52 needs about 1 micrometer.

On this SiGe buffer layer 52, a spacer layer 54 made of Si _0.7 Ge _0.3 without impurity is disposed. An n-channel 67 which forms a carrier structure at a discontinuity in the conduction band existing at the hetero interface between the spacer layer 54 and the Si layer 55 thereon, thereby trapping electrons two-dimensionally. )

The δ doping layer 53 is a layer doped with a high concentration of an element of group V such as P or As to supply electrons as carriers to the n-channel 67. The spacer layer 54 on the δ doped layer 53 is composed of Si _0.7 Ge _0.3 that is not doped with impurities, and by spatially separating the carrier electrons of the n-channel 67 and the ions of the δ doped layer 53, It has a role of improving the mobility by reducing the scattering by the ions of the carrier electrons. The thicker the thickness of the spacer layer 54 is, the smaller the scattering effect of carriers due to ionized impurities can be. On the contrary, since the carrier density is reduced, the thickness of the spacer layer 54 is preferably about 3 nm.

The i-Si _1-x Ge _x layer 56 and the i-Si layer 57 are used to form the p-channel 68 by forming a step in the valence band at the hetero interface. It is preferable to set X to around 0.7.

The gate insulating film 58 insulates the gate electrode 65 from the semiconductor layer below, thereby reducing the gate leakage current, thereby enabling low power consumption operation of the device. In addition, since the oxide film formed by oxidizing the SiGe layer 56 becomes a water-soluble unstable film, it is preferable to use a silicon oxide film as the gate insulation film also in the SiGe field effect transistor. Therefore, in the Si-based hetero M0S device, the semiconductor layer immediately below the gate insulating film is preferably a Si layer.

That is, the field effect transistor according to the present embodiment includes a channel region composed of the above-described stacked film, a source / drain region 59 indicated by a dotted line in Fig. 10, and an Al source for inputting and outputting current for operation of the transistor. It is comprised by the drain electrode 63 and the gate electrode 65 for applying the voltage for controlling an electric current. When the field effect transistor is used as an n-channel field effect transistor, a voltage is applied to the gate electrode 65 to form the n-channel 67, and used as a p-channel field effect transistor. In this case, a voltage is applied to the gate electrode 65 to form the p-channel 68.

Features of the invention according to the present embodiment differ from the first semiconductor layer and the first semiconductor layer comprising an i-Si _1-xy Ge _x C _y layer (0≤x≤1, 0≤y≤1). A channel region having a second semiconductor layer having a band gap, a carrier region having a carrier accumulation layer formed in a region near an interface between the first and second semiconductor layers, a third semiconductor layer, and a band gap larger than the third semiconductor layer. It is a point provided with the source-drain contact layer which has a 4th semiconductor layer which has a semiconductor layer, and the low-resistance conductor film formed directly on the said 3rd semiconductor layer.

In the case where the field effect transistor of the present embodiment is used as an n-channel field effect transistor, the i-Si layer 55 is formed of an i-Si _1-xy Ge _x C _y layer (0≤x≤1, 0≤). (x = y = 0), the SiGe buffer layer 52 is the second semiconductor layer, and the i-Si _1-x Ge _x layer 56 is the third semiconductor layer i-Si layer 57 as the fourth semiconductor layer is larger band gap than the i-Si _1-x Ge _x layer 56, the third right of the semiconductor layer is an i-Si _1-x Ge _x layer 56 The source-drain contact W layer 61 is formed on it.

On the other hand, when the field effect transistor of the present embodiment is used as a p-channel field effect transistor, the i-Si _1-x Ge _x layer 56 has an i-Si _1-xy Ge _x C _y layer (0≤x (Y = 0), which is the first semiconductor layer containing ≤1, 0≤y≤1, is a third semiconductor layer, and i-Si layer 57 is a second semiconductor layer and has a band gap than that of the third semiconductor layer. As this large fourth semiconductor layer, a source-drain contact W layer 61 is formed directly on the i-Si _1-x Ge _x layer 56 that is the third semiconductor layer.

As described above, in the present embodiment, the region on the substrate side to which the A1 source / drain electrodes 63 are contacted is provided in a layer having a small band gap in each semiconductor layer for channel formation. The case of this embodiment, Si layer 57 and the _{i-Si 1-x} Ge _x layers of the hetero interface between the 56 and the small band gap _{i-Si 1-x} Ge _x layer 56, the p- channel for forming The source-drain contact W layer 61 is provided directly above. As a result, the contact resistance is smaller than that of providing the contact directly on the i-Si layer 57, which is the uppermost semiconductor layer, and the low power consumption and high speed operation of the device can be achieved.

Further, if W is grown on a Si _0.7 Ge _0.3 layer on a Si layer and then a metal (Al in this case) is deposited, a very low contact can be obtained. The contact using this SiGe film can obtain a contact having a single digit resistance value lower than that of the low resistance contact using the silicide technology which is generally used as a low resistance contact in a conventional CMOS device (IEEE Electron Device Letters vol. 17.No. .7, 1996 pp 360).

In this paper, the SiGe layer is grown only for source / drain electrode contact formation. However, as shown in the present embodiment, a structure for holding a contact on the SiGe layer for channel formation is evident, as will be apparent from the transistor manufacturing method described below. Productivity is improved by eliminating the need to grow new SiGe crystals.

In this embodiment, however, the HCMOS device may be used where the speed of the device is required, and in addition, a CMOS device formed on a normal Si substrate may be fabricated, and the M0S type field effect formed directly on the Si substrate. The integration of transistors is also possible.

Next, a method of manufacturing the field effect transistor according to the present embodiment will be described. 11 (a) to 11 (e) and 12 (a) to 12 (e) are cross-sectional views illustrating examples of manufacturing processes for realizing the structure of the field effect transistor shown in FIG.

First, in the process shown in Fig. 11A, ions are implanted into the Si substrate 50 prior to epitaxial growth of channel formation, and p wells 51n and n wells, which are the basis of NMOS transistors and PMOS transistors, are implanted. (51p) is formed.

Next, in the process shown in Fig. 11B, the substrate is cleaned by RCA cleaning or the like to remove impurities on the surface before epitaxial growth on the substrate. Thereafter, the oxide film on the surface is removed and the substrate is inserted into the epitaxial growth apparatus and heated in vacuum to obtain a clean surface. Then, epitaxial growth of the semiconductor layer for forming a channel region is performed on this clean surface. The semiconductor layer includes a SiGe buffer layer 52, a δ doping layer 53, a spacer layer 54, an n-channel layer 67, an i-Si layer 55, and an i-Si _1-x Ge _x layer 56. ), p-channel layer 68, i-Si layer 57, and the like. For the sake of clarity, the illustration of the δ doping layer 53, the spacer layer 54, the n-channel layer 67 and the p-channel layer 68 is omitted. Hereinafter, the formation procedure of each layer in this semiconductor layer is demonstrated.

As the growth method of the semiconductor layer, an MBE method using a solid source or a UHV-CVD method using a gas source may be used. In the case of the UHV-CVD method, the atmosphere in the apparatus is first ultra-high vacuum (about 10 ^-10 Torr), and a source for crystal growth is introduced into the vacuum chamber, and then the vacuum degree of about 10 ^-5 to 10 ^-6 Torr is reached. Crystal growth in the state.

Therefore, also in this embodiment, after a clean surface is produced on the substrate by the above-described process, the semiconductor crystal layer is grown by setting the substrate temperature at about 500 to 700 ° C when the vacuum degree in the vacuum container becomes sufficiently high. . In addition, when the substrate temperature is changed, the substrate temperature is not changed while the single layer is grown, in order to affect the quality of the crystal, such as a change in composition ratio in a single semiconductor crystal layer. Further, at a high temperature of 800 ° C. or higher, Ge and Si diffuse to each other to impair the steepness of the hetero interface, or to mitigate distortion to deteriorate channel characteristics. Therefore, the growth temperature is 700 as described above. Choose below ° C.

Crystal growth is to introduce source gas necessary for crystal growth into a vacuum vessel in an ultra high vacuum state. As a source gas used for crystal growth, disilane is used for the growth of the Si layer. For the growth of the SiGe layer, germanium is used as the source gas of Ge in addition to the source gas for growing the Si layer such as disilane. At this time, the composition ratio of Si and Ge in the SiGe layer can be controlled by adjusting the partial pressure ratio of each source gas. Gas flow rate is adjusted so that the degree of vacuum becomes about 10 ^-5 ~ 10 ^-6 Torr.

First, the SiGe buffer layer 52 is formed by stacking a plurality of SiGe layers with lattice relaxation and changing the composition ratio step by step. At this time, in order to change the composition ratio stepwise, the ratio of the partial pressure of the source gas of Si and the partial pressure of the source gas of Ge is changed step by step as described above.

Next, in forming the δ doped layer 53, a dopant gas such as arsine or phosphine is introduced into the vacuum vessel simultaneously with disilane and germanium.

In this case, when the impurities introduced into the δ doping layer 53 are mixed with the spacer layer 54, the transistor characteristics deteriorate. Therefore, once the dopant gas is introduced into the vacuum vessel, the supply of the source gas is stopped and the degree of vacuum is sufficiently increased. After enhancement, a gas for growing the spacer layer 54 is introduced to grow the spacer layer 54. The composition of the spacer layer 54 is made into Si _0.7 7 Ge _0.3 uniformly, and it grows by fixing the flow volume of disilane and germanium.

After the growth of the spacer layer 54, the supply of the source gas is once stopped and the degree of vacuum is improved, then only disilane is introduced into the growth chamber to grow the i-Si layer 55 which is not doped with impurities.

After the growth of the i-Si layer 55, disilane and germanium are again introduced into the growth chamber to grow the i-Si _1-x Ge _x layer 56. The composition ratio of Ge is 70%. After the growth of the i-Si _1-x Ge _x layer 56, the supply of the source gas is once stopped, and after the vacuum degree is improved, only disilane is introduced into the growth chamber to grow the i-Si layer 57.

By the above process, the epitaxial growth process of the semiconductor layer which comprises a channel region is complete | finished.

Next, in the process shown in FIG. 11C, the substrate is taken out from the UHV-CVD apparatus and introduced into a thermal oxidation furnace to oxidize the surface of the uppermost i-Si layer 57. A gate insulating film 58 made of a silicon oxide film is formed.

Next, in the process shown in FIG. 11D, the gate electrode 65 is formed on the gate insulating film 58. The formation method of this gate electrode is the same as that of the conventional CM0S apparatus process. That is, the polysilicon film is deposited, the impurities are ion implanted, and the polysilicon film is patterned by dry etching to form the gate electrodes 65n and 65p. As impurity ions, boron fluoride ion (BF2 +) can be used. In the step where the polysilicon film for the gate electrode is deposited, the source and drain regions are not formed.

Next, in the process shown in Fig. 11E, impurity ions serving as dopants are implanted into the substrate using the gate electrodes 65n and 65p as masks to form source and drain regions 59n and 59p. Then, etching is performed to remove the oxide film exposed on the substrate in order to make contact. In addition, at the time of ion implantation, the acceleration voltage of the ions is selected such that the peak of the impurity distribution provides the contact of the source and drain electrodes. As the impurity ions to be implanted, arsenic ions (As +) or phosphorus ions (p +), which are n-type impurities, are used in the NMOS transistor region, and boron ions (B +), which are p-type impurities, are used in the PMOS transistor region. Therefore, it is necessary to use separate masks for ion implantation for forming the source and drain regions 59n of the NMOS transistors and ion implantation for forming the source and drain regions 59p of the PMOS transistors.

Immediately after ion implantation, annealing for activation of impurities is performed. However, RTA (Rapid thermal) for a short time (30 seconds) at about 100 ° C to prevent the occurrence of crystal defects in the interdiffusion of Si and Ge in the hetero interface or mitigation of distortion in the Si / SiGe system by annealing heat treatment. preferably annealing).

Next, in the process shown in Fig. 12A, a photoresist mask (not shown) is formed once again on the substrate, and at least the channel region between the NMOS transistor formation region and the PMOS transistor formation region by dry etching. Digging deeper to form the device isolation groove 71.

Next, in the process shown in FIG. 12B, the first layer insulating film 72 is deposited on the entire surface of the substrate including the grooves 71. As the material constituting the insulating film, in order to avoid high temperature treatment, it is preferable to use a TEOS film or the like by the plasma CVD method which is formed at 500 ° C or lower. At this time, the trench isolation 73 is formed by an insulating film embedded in the groove 71.

Next, a source / drain contact, which is a feature of the present embodiment, is formed by the following procedure. However, the process for realizing the structure shown in FIG. 10 is not limited to the following procedure.

In order to achieve the maximum effect of this embodiment, it is necessary to have a very thin specific semiconductor layer which finally forms the basis of the contact. Therefore, by selecting this embodiment, the _{i-Si 1-x} Ge _x layer as a specific semiconductor layer to be the base (56n, 56p), i- Si 1-x Ge x layer (56n, 56p) when the exposure Etch until When exposing the i-Si _1-x Ge _x layers 56n and 56p, it is preferable to use etching with high selectivity by wet etching. However, wet etching is deficient in other orientations and is not suitable for microfabrication. First, by selectively removing the regions to form the source and drain electrodes of the insulating film 72 of the first layer by dry etching, contact holes are removed. After forming and exposing the gate insulating films 58n and 58p, it is preferable to perform wet etching. Examples of such processing include the following processing.

First, as is well known, a hydrofluoric acid-based solution is used to remove the oxide films (gate insulating films 58n and 58p) of the uppermost layer. When the i-Si layers 57n and 57p are exposed, hydrofluoric acid hardly removes silicon, so the etching solution is changed to an etching solution capable of removing the i-Si layer 57. In this embodiment, since a contact is formed in the i-Si _1-x Ge _x layers 56n and 56p below the i-Si layers 57n and 57p, the i-Si _1-x Ge _x layer 56n , 56p) is selected, and an etchant (etchant) capable of selectively etching the i-Si layers 57n and 57p is selected. Using this etchant, i-Si layers 57n and 57p are removed to expose i-Si _1-x Ge _x layers 56n and 56p. At this time, part of the i-Si _1-x Ge _x layers 56n and 56p may be removed by over etching. As described above, these i-Si _1-x Ge _x layers 56n and 56p are epitaxially grown to form n-channel in the channel region of the NMOS transistor. Therefore, using this embodiment, a process for newly growing the i-Si _1-x Ge _x layers 56n and 56p is unnecessary to form a low resistance contact using the SiGe layer.

Next, a low resistance metal film is deposited on the exposed i-Si1-xGex layers 56n and 56p to form a contact. As the metal material constituting the metal film, when tungsten (W) is used as described above, a very low contact value can be formed. Thus, in the present embodiment, by using the LPCVD method, a gas diluted with hydrogen of WF6 is used as the source gas, and the temperature condition is 400 ° C., and the source is placed on the i-Si _1-x Ge _x layers 56n and 56p. The drain contact W layers 61n and 61p are selectively grown.

Next, in the process shown in Fig. 12E, the A1 alloy film is deposited on the entire surface of the substrate by sputtering and then patterned to form the A1 source / drain electrodes 63n and 63p. In the above steps, a low resistance contact can be formed on the source and drain regions.

As described above, in the case of using a silicon oxide film as the gate insulating film in the Si-based hetero-M0S device, since the uppermost semiconductor layer is preferably a Si layer having a large band gap, the contact metal layer is removed after removing the semiconductor layer as in the present embodiment. The technique to form is a technique especially suitable for formation of a Si type hetero M0S device.

(Example 5)

In the above embodiment, a channel structure using a heterojunction composed of Si and SiGe is exemplified. However, the invention of forming a low resistance contact in the source / drain region of the HCMOS device is not limited to this embodiment. Examples of channels with heteroepitaxial layered films having a structure other than the stacked structure of SiGe, such as Si and i-Si _1-xy Ge _x C _y layers (0 ≦ x ≦ 1, 0 ≦ _y ≦ 1) of mixed crystal semiconductors The channel may be formed in between. The formation of such a low-resistance contact layer becomes effective because the channel formation by the hetero interface requires the joining of two semiconductors having different band gaps.

FIG. 13 is a sectional view of an HCMOS device according to a fifth embodiment in which a low resistance contact metal layer is formed in the structure shown in FIG.

As shown in Fig. 13, in the HCMOS device according to the present embodiment, source / drain contact W layers 25n and 25p are formed on the SiGe layers 15n and 15p.

The feature of the invention according to the present embodiment includes, in addition to the feature of the first embodiment, a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ _y ≦ 1), as in the fourth embodiment. A channel region having a first semiconductor layer, a second semiconductor layer having a band gap different from that of the first semiconductor layer, and a carrier storage layer formed in an area near an interface between the first and second semiconductor layers; A source / drain contact layer comprising a third semiconductor layer, a source / drain region having a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer, and a low resistance conductor film formed directly on the third semiconductor layer. It is provided with.

In the NMOS transistor of the present embodiment, the SiGeC layer 14n is a first semiconductor layer including a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ _y ≦ 1). 13n) is a second semiconductor layer, SiGe layer 15n is a third semiconductor layer, and Si layer 17n is a fourth semiconductor layer having a larger band gap than SiGe layer 15n, and is a SiGe layer that is a third semiconductor layer. The source-drain contact W layer 25n is formed just above 15n.

On the other hand, in the PMOS transistor of this embodiment, the SiGe layer 15p includes a first semiconductor layer (y = 0) including a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ _y ≦ 1). At the same time, the third semiconductor layer, the Si layer 17p is a second semiconductor layer and a fourth semiconductor layer having a larger band gap than the third semiconductor layer. The source layer is placed directly on the SiGe layer 15p as the third semiconductor layer. A drain contact W layer 25p is formed.

As described above, in the present embodiment, a band gap among the semiconductor layers for channel formation is formed in the region (source / drain contact W layers 25n and 25p) on the substrate side that contacts the A1 source / drain electrodes 21n and 21p. Since it is provided directly above this small layer, the contact resistance becomes smaller than providing a contact directly above the Si layers 17n and 17p, which is the uppermost semiconductor layer, thereby enabling low power consumption and high speed operation of the device. .

In particular, since source / drain contact W layers 25n and 25p made of tungsten (W) are provided to contact the SiGe layers 15n and 15p, very low contact resistance can be obtained.

That is, in this embodiment, the contact resistance can be reduced while exhibiting the effect of the first embodiment.

(Example 6)

FIG. 14 is a sectional view of an HCMOS device according to a sixth embodiment in which a low resistance contact metal layer is formed in the structure shown in FIG.

As shown in Fig. 14, in the HCMOS device according to the present embodiment, source / drain contact W layers 45n and 45p are formed on the SiGe layers 36n and 36p serving as quantum well regions.

In addition to the features of the third embodiment, a feature of the present invention according to the present embodiment is a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ _y ≦ 1) as in the fourth embodiment. A channel region having a first semiconductor layer, a second semiconductor layer having a band gap different from the first semiconductor layer, and a carrier storage layer formed in an area near an interface between the first and second semiconductor layers; And a source / drain contact including a source / drain region having a third semiconductor layer, a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer, and a low resistance conductor film formed directly on the third semiconductor layer. It is a point provided with a layer.

In the NMOS transistor of the present embodiment, the SiGeC layer 34n, which is a quantum well region, is a first semiconductor layer including a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ _y ≦ 1). The first Si layer 33n is a second semiconductor layer, the SiGe layer 36n, which is a quantum well region, is a third semiconductor layer, and the third Si layer 37n has a larger band gap than the SiGe layer 36n. As the fourth semiconductor layer, a source-drain contact W layer 45n is formed directly on the SiGe layer 36n which is the third semiconductor layer.

On the other hand, in the PMOS transistor of this embodiment, the SiGe layer 36p includes a first semiconductor layer (y = 0) including a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ _y ≦ 1). At the same time, the third semiconductor layer is a third semiconductor layer, and the third Si layer 37p is a second semiconductor layer and a fourth semiconductor layer having a larger band gap than the third semiconductor layer, and is directly above the SiGe layer 36p which is the third semiconductor layer. The source-drain contact W layer 45p is formed.

As described above, in the present embodiment, the band gap of each semiconductor layer for forming the channel is formed in the region (source / drain contact W layers 45n and 45p) on the substrate side that contacts the Al source / drain electrodes 41n and 41p. Since it is provided directly above the small layer, the contact resistance becomes smaller than providing the contact directly above the Si layers 37n and 37p, which is the uppermost semiconductor layer, thereby enabling low power consumption and high speed operation of the device.

In particular, since the source / drain contact W layers 45n and 45p made of tungsten (W) are provided so as to contact the SiGe layers 36n and 36p, a very low contact resistance can be obtained.

That is, in the present embodiment, the contact resistance can be reduced while exhibiting the effect of the third embodiment.

(Other Modified Examples)

In the first to sixth embodiments, the MOS field effect transistor having the gate insulating film provided below the gate electrode has been described, but the present invention is not limited to these embodiments. In particular, a field effect transistor using a hetero interface rather than a hetero M0S structure having an insulating film on the uppermost layer can be implemented even by a device using a Schottky junction without using an insulating film, and the effect of reducing the resistance can be obtained. It is advantageous for power and high speed operation.

In the above first to sixth embodiments, the δ doping layer is formed, but the present invention is not limited to these embodiments, and the effects of the present invention can be obtained even without providing the δ doping layer. In addition, even when forming the δ doping layer, the spacer layer is not necessarily required.

In said 1st, 2nd, 3rd, 5th, and 6th Example, you may provide the SiGeC layer which added a trace amount C layer instead of a SiGe layer.

In addition, in the said 1st, 2nd, 3rd, 5th, 6th Example, you may reverse | vertise the vertical relationship of a SiGeC layer and a SiGe layer. In that case, in the fifth and sixth embodiments, the source / drain contact W layer may be formed directly on the SiGeC layer in the source / drain region.

According to the first semiconductor device of the present invention described above, in a semiconductor device having a field effect transistor, a Si _1-xy Ge _x C _y layer having a composition ratio y of 0.01 to 0.03 in a Si layer and C is provided, and a Si _{1- Since} the carrier accumulation layer formed in the _xy Ge _x C _y layer is used as a channel, it is possible to provide a semiconductor device having a field effect transistor having a high operation speed and high reliability.

Further, according to the second semiconductor device of the present invention, in a semiconductor device having a field effect transistor, a second Si layer and a second Si layer are formed between the first Si layer and the first Si _1-xy Ge _x C _y layer. By using a band discontinuity at the interface between the Si _1-xy Ge _x C _y layers of, an accumulation layer for confining electrons and holes in two dimensions is formed, and a field effect transistor is formed using the accumulation layer as a channel. In addition, it is possible to provide a semiconductor device which functions as an HCMOS device having a highly efficient channel confining carrier and having a high operation speed and high reliability n-channel and p-channel field effect transistors.

The structure of this semiconductor device can be easily realized by the manufacturing method of a 1st semiconductor device.

Further, according to the third semiconductor device of the present invention, a semiconductor device having a field effect transistor in which a band discontinuity as a channel is formed between a first semiconductor layer and a second semiconductor layer including a Si _1-xy Ge _x C _y layer. A source / drain contact comprising a source / drain region having a third semiconductor layer and a fourth semiconductor layer having a larger band gap than the third semiconductor layer, and formed of a low resistance conductor film directly on the third semiconductor layer. Since the layer is provided, it is possible to provide a semiconductor device having a high operation speed using a heterojunction and a small source / drain contact resistance.

The structure of this semiconductor device can be easily realized by the manufacturing method of a 2nd semiconductor device.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the present invention as set forth in the appended claims.

1 is a cross-sectional view showing the structure of a SiGeC-based HCMOS device according to a first embodiment of the present invention.

FIG. 2 illustrates the dependence of the Ge and C composition rates on the lattice distortion of SiGeC layers in HCMOS devices.

3 is a diagram showing a relationship between the composition ratios of Si, Ge, and C that cause lattice matching or tensile distortion between the SiGeC layer and the Si layer of the SiGeC-based HCMOS device.

4 shows the relationship between the C composition ratio and the energy gap value of the SiGeC layer.

Fig. 5 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

Fig. 6 is a diagram showing the relationship between the composition of the SiGeC layer and the distortion due to lattice mismatch in the second embodiment of the present invention.

FIG. 7 is a diagram showing a band-up of a lattice matching system SiGeC-HCMOS device according to a second embodiment of the present invention. FIG.

Fig. 8 is a sectional view showing the structure of an HCMOS device having a channel of a quantum well structure according to a third embodiment of the present invention.

Fig. 9 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

Fig. 10 is a sectional view showing the structure of an HCMOS device according to a fourth embodiment of the present invention.

Fig. 11 is a sectional view showing a first half portion in a manufacturing process of an HCMOS device according to a fourth embodiment of the present invention.

12 is a cross-sectional view showing a second half part in the manufacturing process of the HCMOS device according to the fourth embodiment of the present invention.

Fig. 13 is a sectional view showing the structure of an HCMOS device according to a fifth embodiment of the present invention.

Fig. 14 is a sectional view showing the structure of an HCMOS device according to a sixth embodiment of the present invention.

Fig. 15 is a sectional view showing the structure of a conventional HCMOS device.

Fig. 16 shows a defect such as a potential due to lattice mismatch introduced into a hetero interface of a conventional HCMOS device.

* Explanation of symbols indicating major parts of drawing *

10, 30, 50 Si substrate 11, 31, 51n: p well

12, 32, 51p: n well 13: Si layer

14, 34: SiGeC layer 15, 36: SiGe layer

16 source and drain regions 17 Si layer

18, 38, 65: gate electrode 19, 39, 58: gate insulating film

21 and 41: source and drain electrodes 25, 45 and 61: source and drain contact W layers

33: first Si layer 35: second Si layer

37: third Si layer 42, 49: source / drain region

52 SiGe buffer layer 53 δ doped layer

54 spacer layer 55, 57 i-Si layer

56: i-Sil-xGex layer 63: Al source and drain electrode

66 first layer insulating film 67 n-channel

68: p-channel

Claims (42)

(Three times of correction) A semiconductor device formed on a part of a semiconductor substrate and including a field effect transistor having a gate electrode, a source / drain region, and a channel region between the source / drain region, In the channel region, a Si layer and a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 <y ≦ 1) formed in contact with the Si layer are provided. A carrier accumulation layer is formed in the region proximate to the Si layer in the Si _1-xy Ge _x C _y layer, A carrier supply layer for supplying a carrier to the carrier accumulation layer is formed in a region proximate to the Si _1-xy Ge _x C _y layer in the Si layer, A M0S transistor formed on the semiconductor substrate, the semiconductor layer having a single composition as a channel region, And a distortion due to the lattice constant difference between the Si layer and the Si _1-xy Ge _x C _y layer is within 0.25%. The method of claim 1, A semiconductor device, characterized in that the composition ratio of the Si _1-xy Ge _x C _y layer of each element is to be adjusted to a composition ratio which is lattice matched the Si _1-xy Ge _x C _y layer and the Si layer. (correction) The method of claim 1, The Si _1-xy Ge _x C _y layer has a lattice constant smaller than that of the Si layer and has a film thickness that does not cause lattice relaxation. (delete) (delete) (delete) (delete) (delete) (delete) (Twice) A first field effect transistor formed on a portion of the semiconductor substrate and having a channel region between the gate electrode and the source / drain region and the source / drain region, and formed on the other portion of the semiconductor substrate, A semiconductor device comprising a second field effect transistor having a channel region between the source and drain regions, In the channel region of the first field effect transistor, A first Si layer, A first Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 <y ≦ 1) formed in contact with the first Si layer, A second Si layer, A second Si _1-xy Ge _x C _y layer formed in contact with the second Si layer and having a band gap different from the first Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ y ≤1) is installed, Wherein the _{1 Si 1-xy Ge x C} y and the region close to the claim 1 Si layer in the layer, wherein the 2 Si _1-xy Ge _x C _y is the region close to the claim 2 Si layer in the layer, the different First and second carrier accumulation layers for trapping the conductive carrier are formed, respectively, Distortion due to a lattice constant difference between the first Si layer and the first Si _1-xy Ge _x C _y layer is within 0.25%, Distortion due to the lattice constant difference between the second Si layer and the second Si _1-xy Ge _x C _y layer is within 0.25%, The second field effect transistor channel region is  A third Si layer, A SiGe layer formed in proximity to the third Si layer, And a third carrier accumulation layer for accumulating positive carriers in a region proximate to the third Si layer in the SiGe layer. (Twice) The method of claim 10, And the Si _1-xy Ge _x C _y layer and the SiGe layer are quantum well regions. (delete) (Twice correction) The method of claim 10, The source / drain region has a first semiconductor layer and a second semiconductor layer having a band gap larger than that of the first semiconductor layer, A semiconductor device further comprising a source / drain contact layer made of a low resistance conductor film formed directly on the first semiconductor layer. (delete) (delete) (delete) (delete) (Twice) The method of claim 10, The composition ratio y of C in said Si _1-xy Ge _x C _y layer is 0, The semiconductor device characterized by the above-mentioned. (correction) The method of claim 10, And a M0S transistor formed on said semiconductor substrate and having a single layer of semiconductor layer as a channel region. (correction) The method of claim 10, The composition ratio y of C in said 1st Si _1-xy Ge _x C _y layer is 0.01-0.03, The semiconductor device characterized by the above-mentioned. (correction) The method of claim 10, The composition ratio of said first Si _1-xy Ge _x C _y each element of the floor of Figure 1, characterized in that it is adjusted to a composition ratio that is lattice-matched Si _1-xy Ge _x C _y layer and said first Si layer of the first A semiconductor device. (Twice) The method of claim 10, And the first Si _1-xy Ge _x C _y layer has a lattice constant smaller than the lattice constant of the first Si layer and has a film thickness that does not cause lattice relaxation. (correction) The method of claim 10, Carriers accumulated in the first carrier storage layer are negative carriers, The carrier accumulated in the second carrier storage layer is a positive carrier. (correction) The method of claim 10, A carrier supply layer for supplying a carrier to the first carrier accumulation layer is further formed in a region proximate to the first Si _1-xy Ge _x C _y layer in the first Si layer. Semiconductor device. (delete) (correction) The method of claim 10, At least one of the first and second Si _1-xy Ge _x C _y layers of the Si _1-xy Ge _x C _y layer is a semiconductor device, characterized in that the quantum well region. (Twice) The method of claim 10, And further comprising a source / drain contact layer made of a low resistance conductor film formed directly above the Si _1-xy Ge _x C _y layer formed on the upper side of the first and second Si _1-xy Ge _x C _y layers. A semiconductor device, characterized in that. (delete) (delete) (delete) (delete) (delete) (delete) (delete) (delete) (delete) (delete) (delete) The method of claim 1, The composition ratio of said C is 0.01-0.03, The semiconductor device characterized by the above-mentioned. The method of claim 10, The composition ratio of C in said Si _1-xy Ge _x C _y layer is 0.01-0.03, The semiconductor device characterized by the above-mentioned. (delete) (delete)

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