JPH06216376A - Field effect type semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having a gate insulating film without deforming SiGe/Si heterostructure and the profile of doping of impurities, by depositing an oxide film which makes a semiconductor substrate one or the components, and an insulating film, on the semiconductor substrate having an impurity layer wherein the impurity distribution is specified. CONSTITUTION:On Si and SiGe/Sl heterostructure wherein the spread of impurity distribution is smaller than 10nm, a thermal oxide film of 5nm or smaller in thickness is formed at 800 deg.C, and thereon an insulating film is deposited. For example, Si layers 12, 14 having a delta doping layer of B are epitaxially grown on a silicon substrate 11, and the surface is oxidized to be 2nm thick at 800 deg.C, thereby forming an oxide film 15. An insulating film 16 of 3nm in thickness is deposited on the film 15 by a plasma CVD method. A gate insulating film having necessary thickness can be formed without deteriorating the SiGe heterointerface and the sharpness of a doping profile.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a field effect semiconductor device having an insulating film on Si and SiGe / Si heterostructures having a steep doping profile.

[0002]

2. Description of the Related Art Si integrated circuits are being highly integrated and speeded up by miniaturization. A metal-oxide film-semiconductor type field effect transistor (Metal
Oxide Semiconductor Feild Effect Transistor ； MO
SFET) is suitable. However, in a device having a gate length of submicron level, suppression of a short channel effect such as punch-through in which a current flows between sources and drains other than the channel is a major problem. Further, when operating at a low voltage of 1.5V level for the purpose of low power consumption, there is a problem that sufficient current driving capability cannot be obtained unless the threshold voltage is set to ± 0.3V or less.

Currently, in order to suppress the short channel effect,
A method of forming a punch-through stopper layer by ion-implanting impurities of the same conductivity type as that of the substrate just below the channel is used. It is necessary to make the depth of the punch-through stopper layer shallower as the device is miniaturized, but since the spread of the impurity distribution cannot be suppressed to 10 nm or less by the ion implantation method, the punch-through stopper layer is formed from the substrate surface. If it is attempted to form it in a shallow place, the impurity concentration on the substrate surface will increase. This causes an increase in the threshold voltage, which is against the lowering of the threshold voltage.

Therefore, a technique for forming a high-concentration doping layer and growing a low-concentration channel layer thereon by using a low-temperature epitaxial growth method such as a molecular beam epitaxy method is described in Applied Physics Letters, Vol. 54 (1989) p.
1869 (Applied Physics Letters 54, p.1869 (1989))
Have been proposed in.

On the other hand, in order to improve the performance of complementary field effect transistors, Si-Ge heterostructure FETs with high carrier mobility and high current driving capability are being studied. For example, IDM Technical Digest (1991) p.25 (IEDM Technical Di
gest p.25 (1991)), a prototype of a p-channel Si / SiGe heterostructure MOSFET is reported.

[0006]

However, a doping layer (δ-doping layer) having an impurity distribution of 10 nm or less or a SiGe heterostructure manufactured by the above molecular beam epitaxy method is subjected to gate oxidation at 900 ° C. or higher by a thermal oxidation method. When the film is formed, there is a problem that the SiGe hetero interface and the steepness of the doping profile are destroyed by heat and the expected transistor characteristics cannot be obtained.

This problem can be solved if the substrate temperature is made as low as possible to form the insulating film. As a typical technique for forming an insulating film at a low temperature at which the steepness of the doping profile and the SiGe hetero interface are not deteriorated, plasma-enhanced chemical vapor deposition (Plasma-enhanced Chemical V
apor Deposition: hereinafter abbreviated as plasma CVD method). However, this method has a drawback that the interface state density of the semiconductor / insulator hetero interface is large and the withstand voltage of the insulating film is low as compared with the thermal oxidation method.

[0008]

In order to solve the above problems, a thermal oxide film of 5 nm or less is first formed at about 800 ° C. on a Si and SiGe / Si heterostructure having a steep doping profile, Then on top of that plasma C
A method of depositing an insulating film by the VD method was devised. Furthermore, it was confirmed that the electrical characteristics were further improved by heat treatment at a substrate temperature of 500 ° C. or higher in an inert gas atmosphere.

For example, as shown in FIG. 1, a Si layer 12 having a B δ-doping layer 13 on a silicon substrate 11,
14 is epitaxially grown, and the surface is grown at 800 ° C for 2
nm oxidation is performed to form an oxide film 15. Further, an insulating film 16 having a thickness of 3 nm is deposited thereon by the plasma CVD method. In this figure,
Reference numeral 18 is a source region, 19 is a drain region, and 17 is a gate electrode.

[0010]

As described above, since the heat treatment required for producing the thermal oxide film 15 is relatively low and the thickness of the thermal oxide film is thin, the oxidation time can be shortened within 300 seconds. Further, if the insulating film 16 is deposited by the plasma CVD method, SiG
e A gate insulating film having a required thickness can be formed without deteriorating the steepness of the hetero interface and the doping profile. FIG. 2 shows the heat treatment time dependence of the impurity profile when B is δ-doped in Si (at a substrate temperature of 800 ° C.). From this figure, 800 ℃, 300
It can be seen that in the heat treatment for about a second, the spread of the profile in the depth direction of the δ-doped layer is not greatly expanded as compared with the case where the heat treatment is not performed. In addition, the insulator / semiconductor interface characteristics and the withstand voltage of the insulating film are improved as compared with the case where only the plasma CVD method is used. Furthermore, this plasma CV
The film produced by the D method has a thickness of 500 in an inert gas atmosphere.
It was found that the heat treatment at a temperature of ℃ or more improves the insulator / semiconductor interface characteristics and the withstand voltage of the insulating film (FIG. 3).

[0011]

Example 1 First, an example in which an n-channel MOSFET having a punch-through stopper layer made of a δ-doping layer of boron (B) was produced (FIG. 1).

The sample was prepared by the molecular beam epitaxy method. First, a low concentration p is formed on the p-type Si (100) substrate 11.
The type Si layer 12 was epitaxially grown to a thickness of 50 nm at a substrate temperature of 750 ° C., and then B was vapor-deposited at 1 × 10 ¹³ / cm ² in order to form a δ-doping layer 13 of B. Then, the temperature of the substrate is set to room temperature, and amorphous Si containing p-type impurities is added.
0 nm was deposited. The substrate was heated at 550 ° C. for 5 minutes to crystallize the amorphous Si. Further, in order to improve the crystallinity of the crystallized low-concentration p-type Si layer 14, the substrate temperature was set to 750 ° C. and heating was performed for 5 minutes. Next, in a short-time oxidizing device, the sample was oxidized for 200 seconds at a substrate temperature of 800 ° C. in an O ₂ atmosphere containing water vapor. The film thickness of the thermal oxide film 15 at this time is 2 nm. Further, a 3 nm SiO ₂ film 16 was deposited at a substrate temperature of 250 ° C. by the plasma CVD method. Next, the gate electrode 17 was formed on the insulating film.
Then, the high-concentration n-type source region 18 and the drain region 19 were formed.

It has been found that the MOSFET operates at Vth = 0.3 V without punch through even when the gate length is 0.1 μm.

Example 2 Next, Si / Si _0.7 Ge _0.3
An example of producing a p-channel MOSFET having a / Si heterostructure will be described (FIG. 4).

Ultrahigh vacuum chemical vapor deposition (UHV-CVD) was used for the preparation of the sample. A non-doped Si _0.7 Ge _0.3 layer 42 is formed on the n-type Si (100) substrate 41 at the substrate temperature.
Epitaxial growth was performed at 550 ° C. for 10 nm. Further, the non-doped Si layer 43 is grown to 7.5 nm. Next, in a short-time oxidizing device, the grown sample was treated with O containing water vapor.
₂ atmosphere, the thermal oxide film 44 of 2nm at a substrate temperature of 800 ° C.
Was produced. Further, the substrate temperature is 25 by the plasma CVD method.
A 7.5 nm SiO ₂ film 45 was deposited at 0 ° C. And
The source and drain regions 47 and 48 are formed by forming the gate electrode 46 on the insulating film and making it a high-concentration p-type.

The p-channel MOSFET has a hole mobility of 165 cm ² / V · s and a gate length of 0.1 at 300K.
For 25 μm, transconductance is 170 mS / m
It showed higher carrier mobility and higher transconductance than the Sip channel MOSFET under the same conditions as m.

<Embodiment 3> Next, Si / Si _0.5 Ge _0.5
/ Si _0.7 Ge _0.3 n-channel MOS with heterostructure
An example of manufacturing the FET will be described (FIG. 5).

The sample was prepared by the molecular beam epitaxy method. First, a thickness of 1 μm is formed on the p-type Si (100) substrate 11.
m p-type Si _0.7 Ge _0.3 buffer layer 51 with a substrate temperature of 50
Grow at 0 ° C. Then, the non-doped Si _0.5 Ge _0.5 layer 52 is set to 20 nm, and the non-doped Si layer 54 is set to the substrate temperature 50.
20 nm was epitaxially grown at 0 ° C. Here, in the Si _0.5 Ge _0.5 layer 52 as a carrier supply source, Si /
A Sb δ-doping layer 53 was formed at a position 5 nm from the Si _0.5 Ge _0.5 interface.

Next, in a short-time oxidizing apparatus, the grown sample was subjected to a substrate temperature of 800 in an O ₂ atmosphere containing water vapor.
A thermal oxide film 55 having a thickness of 2 nm was formed at 0 ° C. Plasma C
A 20 nm SiO ₂ film 56 was deposited at a substrate temperature of 250 ° C. by the VD method. Then, the gate electrode 57, the source region 18, and the drain region 19 were formed.

The n-channel MOSFET has a high electron mobility of 1400 cm ² / V · s at 300K.

The δ-doping layer of Sb is made of Si _0.5
Although it is in the Ge _0.5 layer 52, good electrical characteristics are obtained without the steepness of the doping profile being lost by the heat treatment of this method. In addition, Si _0.5 Ge _0.5
The layer 52 and the Si layer 54 are grown with the same lattice constant as that of the Si _0.7 Ge _0.3 bulk layer 51. That is, Si
_{The 0.5} Ge _0.5 layer 52 and the Si layer 54 have strain. Therefore, strain may be relaxed when the thermal oxide film 55 and the insulating film 56 are formed. However, cross-sectional observations by Raman spectroscopy and electron microscopy confirmed that these films were not strain-relieved.

<Embodiment 4> Next, Si / Si _0.5 Ge _0.5 /
P-channel MOSF composed of Si _0.7 Ge _0.3 heterostructure
An example of producing ET will be described (FIG. 6).

First, an n-type Si _0.7 Ge _0.3 layer 61 having a thickness of 1 μm is formed on an n-type Si (100) substrate 41 at a substrate temperature of 500.
It was grown at ℃. Then, a non-doped Si _0.5 Ge _0.5 layer 52 of 20 nm is formed at a substrate temperature of 500 ° C.
Layer 54 was epitaxially grown to 20 nm. Here, as a carrier supply source, Si / Si _0.5
A δ-doping layer 62 of HBO ₂ or B was formed at a position 5 nm from the Ge _0.5 interface.

Next, in a short-time oxidation device, the grown sample was subjected to an O ₂ atmosphere containing water vapor at a substrate temperature of 800 ° C.
To form a 2 nm oxide film 63. Further plasma CVD
20 nm SiO ₂ film 64 at a substrate temperature of 250 ° C.
Was deposited. Next, the gate electrode 65 and the source region 47
And the drain region 48 was formed.

The p-channel MOSFET showed a high hole mobility of 400 cm ² / V · s at 300K.

The influence of heat treatment on the strained layer is the same as in the case of the third embodiment.

[0027]

According to the present invention, it is possible to fabricate a MOSFET having a gate insulating film having excellent electric characteristics without degrading the profile of SiGe / Si heterostructure and δ doping.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a Si MOSFET in which B is δ-doped.

FIG. 2 is a characteristic diagram showing the heat treatment time dependence of the B profile of a film in which B is δ-doped in Si.

FIG. 3 is a characteristic diagram of interface temperature density and annealing temperature dependency of breakdown voltage of a SiO ₂ film deposited by a plasma CVD method.

FIG. 4 is a cross-sectional view of a Si / Si _0.7 Ge _0.3 / Si heterostructure p-channel MOSFET.

FIG. 5 is a cross-sectional view of a Si / Si _0.5 Ge _0.5 / Si _0.7 Ge _0.3 heterostructure n-channel MOS-FET.

FIG. 6 is a cross-sectional view of a Si / Si _0.5 Ge _0.5 / Si _0.7 Ge _0.3 heterostructure p-channel MOS-FET.

[Explanation of symbols]

11 ... p-type Si (100) substrate, 12 ... low-concentration p-type Si
Layer, 13 ... B delta doping layer, 14 ... low concentration p-type Si
Layer, 15 ... Thermal oxide film, 16 ... Deposited SiO ₂ film, 17
... Gate electrode, 18 ... High concentration n-type source region.

Claims (4)

[Claims] 1. An electric field comprising an oxide film having the semiconductor substrate as one of its components and a deposited insulating film on a semiconductor substrate having an impurity layer whose impurity distribution spread is 10 nm or less. Effective semiconductor device. 2. A field effect semiconductor device comprising an SiGe / Si hetero thin film containing a SiGe mixed crystal, an oxide film containing Si as one of its components, and an insulating film deposited on the SiGe / Si hetero thin film. 3. The substrate temperature according to claim 1 or 2,
A field effect semiconductor device formed at a temperature of 00 ° C. or less and a growth time of 300 seconds or less. 4. The field effect semiconductor device according to claim 1, wherein the insulating film is deposited by plasma-induced vapor phase growth method and the film is heat-treated at a temperature of 500 ° C. or higher in an inert gas atmosphere.