JPH09237896A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH09237896A JPH09237896A JP7100096A JP7100096A JPH09237896A JP H09237896 A JPH09237896 A JP H09237896A JP 7100096 A JP7100096 A JP 7100096A JP 7100096 A JP7100096 A JP 7100096A JP H09237896 A JPH09237896 A JP H09237896A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- drain
- mixed crystal
- crystal layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＭＯＳ−ＦＥＴを含
む半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a MOS-FET.
【０００２】[0002]
【従来の技術】以下、図面を参照して説明する。図４は
従来技術によるｎチャネル型ＭＯＳ−ＦＥＴ（Ｍｅｔａ
ｌ−Ｏｘｉｄｅ−Ｓｅｍｉｃｏｎｎｄｕｃｔｏｒ−Ｆｉ
ｅｌｄ−Ｅｆｆｅｃｔ−Ｔｒａｎｓｉｓｔｏｒ）の構造
を示す断面図である。１はｐ型Ｓｉ基板、２はソ−ス、
３はドレイン、４はゲ−ト電極、５はゲ−ト絶縁膜、６
はソ−ス電極、７はドレイン電極、８は空乏層、１１は
金属、ｌ0 はゲ−ト長である。2. Description of the Related Art A description will be given below with reference to the drawings. FIG. 4 shows a conventional n-channel MOS-FET (Meta).
l-Oxide-Semiconductor-Fi
It is sectional drawing which shows the structure of (eld-Effect-Transistor). 1 is a p-type Si substrate, 2 is a source,
3 is a drain, 4 is a gate electrode, 5 is a gate insulating film, 6
Is a source electrode, 7 is a drain electrode, 8 is a depletion layer, 11 is a metal, and l 0 is a gate length.
【０００３】ｐ型Ｓｉ基板１中には所定の深さまでｎ型
拡散されたソ−ス２とドレイン３とが所定の間隔だけ保
たれて形成されている。ｐ型Ｓｉ基板１上ではソ−ス２
とドレイン３の一部に跨がってゲ−ト絶縁膜５が形成さ
れ、前記ゲ−ト絶縁膜５上にはゲ−ト電極４及び金属１
１が積層されている。ソ−ス２及びドレイン３上にはソ
−ス電極６及びドレイン電極７が形成されている。通
常、ｐ型Ｓｉ基板１中に形成されたソ−ス２及びドレイ
ン３中のｎ型層のキャリア濃度はｐ型Ｓｉ基板１のキャ
リア濃度よりも高いため、空乏層８の大部分はソ−ス２
及びドレイン３側からｐ型Ｓｉ基板１側に広がってい
る。In the p-type Si substrate 1, a source 2 and a drain 3 which have been n-type diffused to a predetermined depth are formed with a predetermined space therebetween. Source 2 on p-type Si substrate 1
A gate insulating film 5 is formed so as to extend over a part of the gate 3 and the drain 3, and the gate electrode 4 and the metal 1 are formed on the gate insulating film 5.
1 are stacked. A source electrode 6 and a drain electrode 7 are formed on the source 2 and the drain 3. Usually, since the carrier concentration of the n-type layer in the source 2 and the drain 3 formed in the p-type Si substrate 1 is higher than the carrier concentration of the p-type Si substrate 1, most of the depletion layer 8 is a source. Space 2
And spreads from the drain 3 side to the p-type Si substrate 1 side.
【０００４】次に、ｎチャネル型ＭＯＳ−ＦＥＴの動作
について説明する。図５はゲ−ト電圧Ｖg を金属１１に
印加し、反転層８を生じた時の図４のＡＡ断面のエネル
ギ−バンド図である。ゲ−ト電圧Ｖg がしきい値電圧Ｖ
THよりも高くなると、ゲ−ト絶縁膜５とｐ型Ｓｉ基板１
の界面に反転層９が形成され、ソ−ス２とドレイン３と
の間で繋がるようになる。この結果、ドレイン３から注
入された電流は反転層９を通りソ−ス２へ流れるように
なる。Next, the operation of the n-channel MOS-FET will be described. FIG. 5 is an energy band diagram of the AA cross section of FIG. 4 when the gate voltage V g is applied to the metal 11 to form the inversion layer 8. The gate voltage V g is the threshold voltage V
When it becomes higher than TH , the gate insulating film 5 and the p-type Si substrate 1
An inversion layer 9 is formed at the interface between the source 2 and the drain 3, and the source 2 and the drain 3 are connected to each other. As a result, the current injected from the drain 3 flows through the inversion layer 9 to the source 2.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、ＭＯＳ
−ＦＥＴを高集積化する場合にはＭＯＳ−ＦＥＴの微細
化に伴い、ゲ−ト長ｌ0 が短くなってくると、ソ−ス２
側とドレイン３側に形成された空乏層８はゲ−ト電圧Ｖ
g の印加の有無にかかわらず繋がりパンチスル−が生じ
る。また、ＭＯＳ−ＦＥＴのしきい値電圧ＶTHの絶対値
が小さくなるという短チャネル効果が発生する。これを
解決する方法として、ｐ型Ｓｉ基板１の不純物濃度を高
くし、空乏層８の広がりを抑制する方法がある。しか
し、ゲ−ト電圧Ｖg は空乏層８に印加されるため空乏層
８の広がりが抑制されると反転層９中を流れる電流の進
行方向に対して垂直方向の電界は強くなる。電界強度が
大きくなると反転層９に沿ってドレイン３からソ−ス２
へ流れる電流は進行方向に対して垂直方向に電界作用を
受けながら流れるため移動度は小さくなる。その結果、
導電率が低くなり、駆動電流も減少する。SUMMARY OF THE INVENTION However, MOS
-When the FET is highly integrated, if the gate length l 0 becomes shorter with the miniaturization of the MOS-FET, the source 2
The depletion layer 8 formed on the drain side and the drain 3 side is the gate voltage V
A punch punch through occurs regardless of whether or not g is applied. Further, a short channel effect occurs in which the absolute value of the threshold voltage V TH of the MOS-FET becomes small. As a method of solving this, there is a method of increasing the impurity concentration of the p-type Si substrate 1 and suppressing the expansion of the depletion layer 8. However, since the gate voltage V g is applied to the depletion layer 8, when the expansion of the depletion layer 8 is suppressed, the electric field perpendicular to the traveling direction of the current flowing in the inversion layer 9 becomes strong. When the electric field strength increases, the drain 3 and the source 2 move along the inversion layer 9.
The mobility of the current flowing to the device becomes small because it flows while receiving an electric field effect in the direction perpendicular to the traveling direction. as a result,
The conductivity is low and the drive current is also low.
【０００６】そこで、本発明は上記の点に着目してなさ
れたものであり、基板濃度を上げても大きな移動度が得
られる半導体装置及びその製造方法を提供することを目
的とするものである。Therefore, the present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device which can obtain a large mobility even if the substrate concentration is increased, and a manufacturing method thereof. .
【０００７】[0007]
【課題を解決するための手段】本発明になる半導体装置
は、第１の発明として、第１の導電型を有するＳｉ基板
１と、前記Ｓｉ基板中に形成されたＳｉＧｅ混晶層１０
と、前記ＳｉＧｅ混晶層１０上に形成されたゲ−ト絶縁
膜５と、前記ゲ−ト絶縁膜上に形成されたゲ−ト電極４
と、前記Ｓｉ基板中に形成され、かつ前記ＳｉＧｅ混晶
層１０を介して互いに近接配置された第２の導電型の一
対の拡散層２，３とを備え、前記一対の拡散層２，３の
間に前記ＳｉＧｅ混晶層１０を設けたことを特徴とす
る。A semiconductor device according to the present invention is, as a first invention, a Si substrate 1 having a first conductivity type, and a SiGe mixed crystal layer 10 formed in the Si substrate.
, A gate insulating film 5 formed on the SiGe mixed crystal layer 10, and a gate electrode 4 formed on the gate insulating film.
And a pair of second conductivity type diffusion layers 2 and 3 formed in the Si substrate and arranged close to each other through the SiGe mixed crystal layer 10, the pair of diffusion layers 2 and 3 being provided. The SiGe mixed crystal layer 10 is provided between the two.
【０００８】第２の発明になる請求項１記載の半導体装
置において、前記ＳｉＧｅ混晶層は１０前記Ｓｉ基板１
中の所定深さ位置でＧｅ濃度が最大値を得るようにした
層とすることを特徴とする。According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the SiGe mixed crystal layer is 10 of the Si substrate 1.
The layer is characterized in that the Ge concentration is maximized at a predetermined depth position inside.
【０００９】第３の発明になる請求項１記載の半導体装
置において、前記ゲ−ト電極４は金属膜または半導体膜
１４からなることを特徴とする。In the semiconductor device according to the first aspect of the present invention, the gate electrode 4 is made of a metal film or a semiconductor film 14.
【００１０】第４の発明になる半導体装置の製造方法に
おいて、第１導電型Ｓｉ基板１にＧｅをイオン注入する
工程と、Ｇｅをイオン注入された前記第１導電型Ｓｉ基
板１上にゲ−ト絶縁膜５を順次形成する工程と、前記ゲ
−ト絶縁膜５上に金属膜又は半導体膜１４を形成する工
程と、前記金属膜または半導体膜１４をエッチングして
ゲ−ト電極４を形成する工程と、前記ゲ−ト電極４をマ
スクとして第２の導電型の一対の拡散層２、３を形成す
る工程とを有することを特徴とする。In the method for manufacturing a semiconductor device according to the fourth aspect of the present invention, a step of ion-implanting Ge into the first conductivity type Si substrate 1 and a step on the first conductivity-type Si substrate 1 into which the Ge ions are ion-implanted A step of sequentially forming a gate insulating film 5, a step of forming a metal film or a semiconductor film 14 on the gate insulating film 5, and a step of etching the metal film or the semiconductor film 14 to form a gate electrode 4. And a step of forming the pair of diffusion layers 2 and 3 of the second conductivity type by using the gate electrode 4 as a mask.
【００１１】第５の発明になる半導体装置の製造方法に
おいて、第１導電型Ｓｉ基板１上にＳｉＧｅ層をエピタ
キシャル成長する工程と、ＳｉＧｅ層をエピタキシャル
成長した前記第１導電型Ｓｉ基板１上にゲ−ト絶縁膜５
を形成する工程と、前記ゲ−ト絶縁膜５上に金属膜又は
半導体膜１４を形成する工程と、前記金属膜または半導
体膜１４をエッチングしてゲ−ト電極４を形成する工程
と、前記ゲ−ト電極４をマスクとして第２の導電型の一
対の拡散層２、３を形成する工程とを有することを特徴
とする。In the method of manufacturing a semiconductor device according to the fifth aspect of the invention, a step of epitaxially growing a SiGe layer on the first conductivity type Si substrate 1 and a step of gaining the first conductivity type Si substrate 1 on which the SiGe layer is epitaxially grown. Insulating film 5
A step of forming a metal film or a semiconductor film 14 on the gate insulating film 5, a step of etching the metal film or the semiconductor film 14 to form a gate electrode 4, And a step of forming a pair of second conductivity type diffusion layers 2 and 3 using the gate electrode 4 as a mask.
【００１２】ＳｉＧｅ混晶層１０はイオン注入またはエ
ピタキシャル成長により前記ＳｉＧｅ混晶層１０の厚さ
の所定深さ位置において、Ｇｅ濃度が高くなるように形
成しているので、ゲ−ト電極に電圧を印加すると従来の
Ｓｉ基板のみの場合に比較し、ＳｉＧｅ混晶層の表面の
エネルギ−バンドの伝導帯の曲りは緩やかになる。この
ため、動作時において、前記ＳｉＧｅ混晶層１０を介し
て互いに近接配置された第２の導電型の一対の拡散層
２，３間を流れる電流に垂直方向の電界は緩和される。
その結果、移動度は向上し、大きな駆動電流が得られ
る。Since the SiGe mixed crystal layer 10 is formed by ion implantation or epitaxial growth so that the Ge concentration becomes high at a predetermined depth position of the thickness of the SiGe mixed crystal layer 10, a voltage is applied to the gate electrode. When applied, the bending of the conduction band of the energy band on the surface of the SiGe mixed crystal layer becomes gentle as compared with the case of only the conventional Si substrate. Therefore, during operation, the electric field in the direction perpendicular to the current flowing between the pair of diffusion layers 2 and 3 of the second conductivity type that are arranged close to each other through the SiGe mixed crystal layer 10 is relaxed.
As a result, the mobility is improved and a large drive current can be obtained.
【００１３】[0013]
【発明の実施の形態】以下、図面を参照して本発明の一
実施例を説明する。本発明の第１の実施例を図１及び図
２により説明する。図１は、本発明のＭＯＳ−ＦＥＴの
構造を示す断面図である。図２はゲ−ト電圧Ｖg を金属
１１に印加し、反転層９を生じた時の図１のＡＡ断面の
エネルギ−バンド図である。前述した構成と同一構成部
分は同一符号を付し、その説明を省略する。１０はＳｉ
Ｇｅ混晶層、Ｅa はＳｉＧｅ混晶層の伝導帯の底、ＥC
はＳｉの伝導帯の底、Ｅv はＳｉ及びＳｉＧｅ混晶層の
価電子帯の頂上である。本発明のＭＯＳ−ＦＥＴの構造
は前述した従来例の図４においてソ−ス２とドレイン３
との間にＳｉとＧｅとの混晶層を設けたものに等しい。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view showing the structure of a MOS-FET of the present invention. FIG. 2 is an energy band diagram of the AA cross section of FIG. 1 when the gate voltage V g is applied to the metal 11 to form the inversion layer 9. The same components as those described above are designated by the same reference numerals, and the description thereof will be omitted. 10 is Si
Ge mixed crystal layer, E a is the bottom of the conduction band of the SiGe mixed crystal layer, E C
Is the bottom of the conduction band of Si, and E v is the top of the valence band of the Si and SiGe mixed crystal layer. The structure of the MOS-FET of the present invention is the same as that of the conventional example shown in FIG.
It is equivalent to a mixed crystal layer of Si and Ge provided between and.
【００１４】以下、詳細に説明する。Ｓｉ基板１中には
Ａｓのイオン注入によりｎ型層を有したソ−ス２とドレ
イン３とが所定の間隔に保たれ、形成されている。ソ−
ス２とドレイン３との間にはイオン注入により所定の深
さでＧｅ濃度が最大値を得るように数％濃度のＧｅを含
んだＳｉＧｅ混晶層１０が形成されている。ｐ型Ｓｉ基
板１上ではソ−ス２とドレイン３との間にはソ−ス２と
ドレイン３の一部に跨がってゲ−ト絶縁膜５が形成さ
れ、前記ゲ−ト絶縁膜５上にはゲ−ト電極４、金属１１
が積層されている。ソ−ス２及びドレイン３上にはソ−
ス電極６及びドレイン電極７が形成されている。通常、
Ｓｉ基板１中に形成されたソ−ス２及びドレイン３中の
ｎ型層のキャリア濃度はｐ型Ｓｉ基板１のキャリア濃度
よりも高くしているため、空乏層８はソ−ス２及びドレ
イン３側からｐ型Ｓｉ基板１側に広がっている。The details will be described below. A source 2 and a drain 3 each having an n-type layer are formed in the Si substrate 1 by ion implantation of As while being kept at a predetermined interval. Saw
A SiGe mixed crystal layer 10 containing several% of Ge is formed between the drain 2 and the drain 3 by ion implantation so that the maximum Ge concentration can be obtained at a predetermined depth. On the p-type Si substrate 1, a gate insulating film 5 is formed between the source 2 and the drain 3 so as to extend over a part of the source 2 and the drain 3. A gate electrode 4 and a metal 11 are provided on the surface 5.
Are laminated. Sources on source 2 and drain 3
A drain electrode 6 and a drain electrode 7 are formed. Normal,
Since the carrier concentration of the n-type layer in the source 2 and the drain 3 formed in the Si substrate 1 is higher than the carrier concentration of the p-type Si substrate 1, the depletion layer 8 is the source 2 and the drain. It spreads from the 3 side to the p-type Si substrate 1 side.
【００１５】次に、図２を用いてＭＯＳ−ＦＥＴの動作
について説明する。破線はＳｉの伝導帯ＥC である。数
％濃度のＧｅを含んだＳｉＧｅ混晶層１０のエネルギ−
バンドギャップはＳｉよりも約０．２ｅＶ程度狭く、Ｇ
ｅ濃度の変化に応じてバンドギャップは変化している。
前記ＳｉＧｅ混晶層１０のフェルミレベルＥF とＳｉＧ
ｅ混晶層１０の価電子帯の頂上ＥV の差はＳｉのフェル
ミレベルＥF とＳｉＧｅ混晶層１０の価電子帯の頂上Ｅ
V の差と略等しいので、ＳｉＧｅ混晶層１０の価電子帯
Ｅv はＳｉと略等しいが、ＳｉＧｅ混晶層１０の伝導帯
の底Ｅc はエネルギ−バンドギャップの差に相当してＳ
ｉの伝導帯の底Ｅc よりも低くなっている。ゲ−ト電極
４に正のゲ−ト電圧Ｖg を印加すると、ゲ−ト絶縁膜５
に接するＳｉＧｅ混晶層１０表面のバンドは下向きに曲
り、ＳｉＧｅ混晶層１０中の正孔がゲ−ト電極４側と反
対側に追いやられ、空乏層８が形成される。更に、大き
な正のゲ−ト電圧Ｖg を印加していくと、ＳｉＧｅ混晶
層１０表面のバンドは更に下向きに曲り、ＳｉＧｅ混晶
層１０表面の電子濃度はｐ型Ｓｉ基板１中の正孔濃度よ
りも大きくなり、ソ−ス２からドレイン３間に反転層９
が形成される。ドレイン電圧ＶD をドレイン電極７に印
加すると反転層９表面の電子はソ−ス２側からドレイン
３側へ即ち、ドレイン３側からソ−ス２側に電流は流れ
る。ＳｉＧｅ混晶層１０表面の伝導帯Ｅa の曲りはｐ型
Ｓｉの伝導帯Ｅc の曲りよりも小さくなるため、反転層
９中を流れる電流に対して垂直方向に印加されているゲ
−ト電圧Ｖｇの電界（垂直電界）による電流が受ける力
は小さくなる。このため、電子の移動度は従来よりも大
きくなり、大きな電流を流すことができるようになる。
このようにしたＭＯＳ−ＦＥＴは微小化しても垂直電界
の影響を軽減することができるので、移動度が高く駆動
電流を向上させることができる。Next, the operation of the MOS-FET will be described with reference to FIG. The broken line is the conduction band E C of Si. Energy of SiGe mixed crystal layer 10 containing several% concentration of Ge
The band gap is narrower than Si by about 0.2 eV, and G
The band gap changes in accordance with the change in the e concentration.
Fermi level E F and SiG of the SiGe mixed crystal layer 10
The difference between the top E V of the valence band of the e mixed crystal layer 10 is the Fermi level E F of Si and the top E of the valence band of the SiGe mixed crystal layer 10.
Since the difference is substantially equal to V , the valence band E v of the SiGe mixed crystal layer 10 is substantially equal to Si, but the bottom E c of the conduction band of the SiGe mixed crystal layer 10 corresponds to the energy-bandgap difference.
It is lower than the bottom E c of the conduction band of i. When a positive gate voltage V g is applied to the gate electrode 4, the gate insulating film 5
The band on the surface of the SiGe mixed crystal layer 10 in contact with is bent downward, holes in the SiGe mixed crystal layer 10 are driven to the side opposite to the gate electrode 4 side, and the depletion layer 8 is formed. Further, when a large positive gate voltage V g is applied, the band on the surface of the SiGe mixed crystal layer 10 bends further downward, and the electron concentration on the surface of the SiGe mixed crystal layer 10 becomes positive in the p-type Si substrate 1. It becomes larger than the hole concentration, and the inversion layer 9 is formed between the source 2 and the drain 3.
Is formed. When the drain voltage V D is applied to the drain electrode 7, the electrons on the surface of the inversion layer 9 flow from the source 2 side to the drain 3 side, that is, from the drain 3 side to the source 2 side. Since the bend of the conduction band E a on the surface of the SiGe mixed crystal layer 10 is smaller than the bend of the conduction band E c of p-type Si, the gate applied in the direction perpendicular to the current flowing in the inversion layer 9. The force received by the current due to the electric field (vertical electric field) of the voltage Vg becomes small. Therefore, the mobility of electrons becomes higher than that of the conventional one, and a large current can flow.
Since the influence of the vertical electric field can be reduced even if the MOS-FET thus configured is miniaturized, the mobility is high and the drive current can be improved.
【００１６】次に本発明の半導体装置のイオン注入法に
よる製造工程を図３（ａ）〜（ｅ）に示す第１工程から
第５工程を参照しながら順次説明する。 （第１工程）ｐ型Ｓｉ基板１上に犠牲酸化膜１２を形成
し、イオン注入法によりｐ型Ｓｉ基板１中の所定の深さ
で所定濃度になるようにＧｅを注入する（図３
（ａ））。その後、所定温度でアニ−ルを行うことによ
って、ＳｉＧｅ混晶層１０を形成する。 （第２工程）犠牲酸化膜１２を除去後、ＳｉＯ2 膜１３
からなるゲ−ト絶縁膜５、ＣＶＤ（Ｃｈｅｍｉｋａｌ
Ｖａｐｏｒ Ｄｐｏｓｉｔｉｏｎ）法により、半導体膜
１４を順次積層し、更にレジスト１５を塗布する（図３
（ｂ））。 （第３工程）次に、レジストパタ−ニングを行い、半導
体膜１４をエッチングし、ゲ−ト電極４を形成する（図
３（ｃ））。 （第４工程）その後レジスト１５を除去し、ゲ−ト電極
４をマスクとして、イオン注入法によりゲ−ト絶縁膜５
を通してｐ型Ｓｉ基板１中にＡｓを注入し、ｎ＋拡散を
行い、ソ−ス２及びドレイン３を形成する（図３
（ｄ））。この後、活性化するために８００℃でアニ−
ルを行う。 （第５工程）更に、レジストパタ−ニングを行い、ソ−
ス２及びドレイン３上のゲ−ト絶縁膜５を除去する。こ
の後、ゲ−ト電極４、ソ−ス２及びドレイン３上にそれ
ぞれ金属１１、ソ−ス電極６及びドレイン電極７を形成
する（図３（ｅ））。なお工程中、ゲ−ト電極４を形成
した後、ソ−ス２及びドレイン３を形成したが、ソ−ス
２及びドレイン３を形成した後、ゲ−ト電極４を形成し
ても良い。Next, the steps of manufacturing the semiconductor device of the present invention by the ion implantation method will be sequentially described with reference to the first to fifth steps shown in FIGS. (First Step) A sacrificial oxide film 12 is formed on the p-type Si substrate 1, and Ge is implanted by an ion implantation method so that the p-type Si substrate 1 has a predetermined depth and a predetermined concentration (FIG. 3).
(A)). After that, the SiGe mixed crystal layer 10 is formed by annealing at a predetermined temperature. (Second step) After removing the sacrificial oxide film 12, a SiO 2 film 13 is formed.
Gate insulating film 5 made of, CVD (Chemical)
The semiconductor films 14 are sequentially laminated by the vapor deposition method, and a resist 15 is further applied (FIG. 3).
(B)). (Third step) Next, resist patterning is performed to etch the semiconductor film 14 to form the gate electrode 4 (FIG. 3C). (Fourth step) After that, the resist 15 is removed, and the gate insulating film 5 is formed by ion implantation using the gate electrode 4 as a mask.
As is implanted into the p-type Si substrate 1 through the n-type Si substrate 1 and n + diffusion is performed to form the source 2 and the drain 3 (FIG. 3).
(D)). After this, annealed at 800 ° C. for activation.
Do (Fifth step) Further, resist patterning is performed, and the
The gate insulating film 5 on the drain 2 and the drain 3 is removed. After that, a metal 11, a source electrode 6 and a drain electrode 7 are formed on the gate electrode 4, the source 2 and the drain 3 respectively (FIG. 3 (e)). In the process, the source 2 and the drain 3 are formed after forming the gate electrode 4, but the gate electrode 4 may be formed after forming the source 2 and the drain 3.
【００１７】また本発明の半導体装置は化学気相エピタ
キシャル成長法によっても作製することができる。化学
気相エピタキシャル成長法では、イオン注入法による製
造工程中、ＳｉＧｅ混晶層１０の形成をエピタキシャル
成長により行うようにしたものに等しい。即ち、図３に
おける第１工程において、ｐ型Ｓｉ基板１上には犠牲酸
化膜１２は形成せず、ｐ型Ｓｉ基板１上に直接、化学気
相エピタキシャル成長法により、成長層厚さ方向のＧｅ
濃度が所定の深さ位置で最大値を得られるようにＳｉＧ
ｅ層１０を成長する。以下における製造工程は図３にお
ける第２工程から第５工程まではイオン注入法の場合と
同様である。なお、第２工程から第５工程において形成
しされるゲ−ト電極４は、半導体膜１４の代わりに金属
膜を用いても良い。本実施例ではｐ型Ｓｉ基板を使用し
た場合で説明したが、ｎ型Ｓｉ基板に適用しても同様の
効果が得られることはいうまでもない。The semiconductor device of the present invention can also be manufactured by the chemical vapor deposition method. The chemical vapor phase epitaxy method is equivalent to a method in which the SiGe mixed crystal layer 10 is formed by epitaxial growth during the manufacturing process by the ion implantation method. That is, in the first step in FIG. 3, the sacrificial oxide film 12 is not formed on the p-type Si substrate 1, and the Ge in the growth layer thickness direction is directly formed on the p-type Si substrate 1 by the chemical vapor deposition method.
SiG so that the concentration can reach the maximum value at a predetermined depth position
The e-layer 10 is grown. The manufacturing process below is the same as the case of the ion implantation method from the second step to the fifth step in FIG. The gate electrode 4 formed in the second to fifth steps may use a metal film instead of the semiconductor film 14. In this embodiment, the case of using the p-type Si substrate has been described, but it goes without saying that the same effect can be obtained even when applied to the n-type Si substrate.
【００１８】[0018]
【発明の効果】以上説明したように、本発明の半導体装
置及び製造方法によれば、ＳｉＧｅ混晶層の厚さ方向に
おいて、イオン注入またはエピタキシャル成長によりＧ
ｅ濃度が所定の深さで最も高くなるように形成している
ので、反転層が形成された時の基板表面の伝導帯の底の
曲りは緩和させることができる。このため、動作時にお
いて、ゲ−ト絶縁膜とＳｉＧｅ混晶層の界面に形成され
る反転層を流れる電流に垂直方向の電界は緩和されるの
で、半導体装置の移動度を高くすることができ、高速応
答が可能となる。As described above, according to the semiconductor device and the manufacturing method of the present invention, G is formed by ion implantation or epitaxial growth in the thickness direction of the SiGe mixed crystal layer.
Since the e concentration is formed so as to be the highest at a predetermined depth, the bending of the bottom of the conduction band on the substrate surface when the inversion layer is formed can be relaxed. Therefore, during operation, the electric field in the direction perpendicular to the current flowing through the inversion layer formed at the interface between the gate insulating film and the SiGe mixed crystal layer is relaxed, so that the mobility of the semiconductor device can be increased. It enables high-speed response.
【図１】本発明のＭＯＳ−ＦＥＴの構造を示す断面図で
ある。FIG. 1 is a sectional view showing a structure of a MOS-FET of the present invention.
【図２】図１に示すＭＯＳ−ＦＥＴにゲ−ト電圧を印加
した時のＡＡ断面のエネルギ−バンド図である。FIG. 2 is an energy band diagram of an AA cross section when a gate voltage is applied to the MOS-FET shown in FIG.
【図３】本発明のＭＯＳ−ＦＥＴの製造工程図である。FIG. 3 is a manufacturing process diagram of a MOS-FET of the present invention.
【図４】従来例のＭＯＳ−ＦＥＴの構造を示す断面図で
ある。FIG. 4 is a sectional view showing the structure of a conventional MOS-FET.
【図５】図４に示すＭＯＳ−ＦＥＴにゲ−ト電圧を印加
した時のＡＡ断面のエネルギ−バンド図である。5 is an energy band diagram of an AA cross section when a gate voltage is applied to the MOS-FET shown in FIG.
１…ｐ型Ｓｉ基板、２…ソ−ス、３…ドレイン、４…ゲ
−ト電極、５…ゲ−ト絶縁膜、６…ソ−ス電極、７…ド
レイン電極、８…反転層、９…空乏層、１０…ＳｉＧｅ
混晶層、１１…金属、１２…犠牲酸化膜、１３…ＳｉＯ
2 膜、１４…半導体膜、１５…レジスト、ｌ0 …ゲ−ト
長、Ｅc …Ｓｉの伝導帯の底、Ｅa …ＳｉＧｅ混晶層の
伝導帯の底、Ｅv …Ｓｉ及びＳｉＧｅ混晶層の価電子帯
の頂上、Ｖg …ゲ−ト電圧、ＶD …ドレイン電圧DESCRIPTION OF SYMBOLS 1 ... P-type Si substrate, 2 ... Source, 3 ... Drain, 4 ... Gate electrode, 5 ... Gate insulating film, 6 ... Source electrode, 7 ... Drain electrode, 8 ... Inversion layer, 9 ... Depletion layer, 10 ... SiGe
Mixed crystal layer, 11 ... Metal, 12 ... Sacrificial oxide film, 13 ... SiO
2 film, 14 ... semiconductor film, 15 ... resist, l 0 ... gate - DOO length, the bottom of the conduction band of E c ... Si, E a ... bottom of the conduction band of the SiGe mixed crystal layer, E v ... Si and SiGe mixed Top of valence band of crystal layer, V g ... gate voltage, V D ... drain voltage
Claims (5)
介して互いに近接配置された第２の導電型の一対の拡散
層とを備え、 前記一対の拡散層の間に前記ＳｉＧｅ混晶層を設けたこ
とを特徴とする半導体装置。1. A Si substrate having a first conductivity type, a SiGe mixed crystal layer formed in the Si substrate, a gate insulating film formed on the SiGe mixed crystal layer, and the gate. A gate electrode formed on the gate insulating film, and a pair of diffusion layers of the second conductivity type formed in the Si substrate and arranged close to each other via the SiGe mixed crystal layer. A semiconductor device, wherein the SiGe mixed crystal layer is provided between the pair of diffusion layers.
定深さ位置でＧｅ濃度が最大値を得るようにした層とす
ることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the SiGe mixed crystal layer is a layer which has a maximum Ge concentration at a predetermined depth position in the Si substrate.
らなることを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the gate electrode is made of a metal film or a semiconductor film.
る工程と、 Ｇｅをイオン注入された前記第１導電型Ｓｉ基板上にゲ
−ト絶縁膜を形成する工程と、前記ゲ−ト絶縁膜上に金
属膜又は半導体膜を形成する工程と、 前記金属膜又は半導体膜をエッチングしてゲ−ト電極を
形成する工程と、 前記ゲ−ト電極をマスクとして第２の導電型の一対の拡
散層を形成する工程とを有することを特徴とする半導体
装置の製造方法。4. A step of implanting Ge into a first conductivity type Si substrate, a step of forming a gate insulating film on the first conductivity type Si substrate into which Ge ions have been implanted, and the gate. A step of forming a metal film or a semiconductor film on the insulating film; a step of etching the metal film or the semiconductor film to form a gate electrode; and a pair of the second conductivity type using the gate electrode as a mask. And a step of forming a diffusion layer.
タキシャル成長する工程と、 ＳｉＧｅ層をエピタキシャル成長した前記第１導電型Ｓ
ｉ基板上にゲ−ト絶縁膜形成する工程と、 前記ゲ−ト絶縁膜上に金属膜又は半導体膜を形成する工
程と、 前記金属膜又は半導体膜をエッチングしてゲ−ト電極を
形成する工程と、 前記ゲ−ト電極をマスクとして第２の導電型の一対の拡
散層を形成する工程とを有することを特徴とする半導体
装置の製造方法。5. A step of epitaxially growing a SiGe layer on a first conductivity type Si substrate, and the first conductivity type S obtained by epitaxially growing a SiGe layer.
forming a gate insulating film on the i substrate; forming a metal film or a semiconductor film on the gate insulating film; and etching the metal film or the semiconductor film to form a gate electrode. And a step of forming a pair of second conductivity type diffusion layers using the gate electrode as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7100096A JPH09237896A (en) | 1996-02-29 | 1996-02-29 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7100096A JPH09237896A (en) | 1996-02-29 | 1996-02-29 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09237896A true JPH09237896A (en) | 1997-09-09 |
Family
ID=13447806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7100096A Pending JPH09237896A (en) | 1996-02-29 | 1996-02-29 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09237896A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100705233B1 (en) * | 2001-12-18 | 2007-04-06 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
-
1996
- 1996-02-29 JP JP7100096A patent/JPH09237896A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100705233B1 (en) * | 2001-12-18 | 2007-04-06 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
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