JP2000091566A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce resistance of a diffused layer and to improve the characteristics of an N-channel MOSFET. SOLUTION: Ge (preferably, in 1% or higher of a composition ratio) is made to contain on at least the surface side of an N-type diffused layer provided in an Si substrate 101. After a Ge-containing layer 102 is formed on the surface of the substrate 101, N-type impurities are introduced in the layer 102 to form N-type diffused layers. It is preferable that the above N-type diffused layers are source and drain regions of an N-channel field-effect transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a method for forming a semiconductor device on a silicon semiconductor substrate.
The present invention relates to a semiconductor device in which a type diffusion layer is formed and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art Miniaturization of semiconductor devices, especially MOS-FE
Miniaturization of T has contributed to an improvement in the degree of integration of transistors and an increase in operation speed. The operating speed is determined by the carrier transfer time between the source and the drain, but the operating speed has increased due to the reduction in gate length due to miniaturization.

[0003]

However, when the gate length is reduced to the sub-micron region, the influence of the parasitic resistance of the source and drain regions cannot be ignored, and an improvement in the operating speed can be expected by merely reducing the gate length. Is disappearing. Therefore, in such an ultra-fine MOS-FET, it is important to develop a technique for reducing the resistance of the source and drain regions.

[0004] This resistance reduction is an important technical problem for both PMOS and NMOS. However, in NMOS, the source and drain regions are N-type regions, and therefore a technology for reducing the resistance of the N-type diffusion layer is required.

SUMMARY OF THE INVENTION The present invention reduces the resistance of a diffusion
-To improve the characteristics of semiconductor devices such as FETs.

As a related art of the present invention, Japanese Patent Application Laid-Open No. 4-42575 discloses a semiconductor device in which polysilicon containing high concentration of Ge is provided in a contact hole and a metal wiring is further provided. Kaihei 4-196420
Patent Document discloses a semiconductor device having a Ge film or a layer containing a Ge impurity at a high concentration on a contact hole and further forming a barrier metal and a metal wiring, all of which are intended to reduce contact resistance. It is.

[0007]

Means for Solving the Problems N-type impurities have a strong surface segregation and segregate on the substrate surface or oxide film / substrate interface during heat treatment.
There is a problem that the amount of electrically active impurities inside the substrate crystal is reduced. The present inventors have conducted intensive studies to solve this problem. As a result, when Ge is introduced into Si, preferably at an atomic composition ratio of 1% or more, surface segregation of N-type impurities is effectively suppressed. Was found. In the present invention, by applying this phenomenon to the formation of an N-type diffusion layer, the amount of electrically active impurities in the diffusion layer is increased, and the resistance can be reduced.

That is, the semiconductor device of the present invention is characterized in that Ge is contained on the surface side of the N-type diffusion layer provided on the Si semiconductor substrate.

The method of manufacturing a semiconductor device according to the present invention
After forming a Ge-containing layer on the surface of the i-semiconductor substrate, an N-type impurity is introduced to form an N-type diffusion layer.

The present invention will be described with reference to FIG. As shown in FIG. 1, the Ge-containing Si
After forming the layer 102, an N-type impurity is introduced,
An activation heat treatment is performed to form an N-type diffusion layer. By doing so, it is possible to suppress a phenomenon in which the resistance of the N-type diffusion layer increases due to the surface segregation of the impurities during the heat treatment for activating the N-type impurities or the heat treatment in a later step.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 2, Ge ions are implanted into a Si substrate 201 by an ion implantation method to form a Ge-containing Si layer 202 on the substrate surface. Then, after injecting an N-type impurity such as As, P or Sb into the Si substrate 201,
For example, using a lamp heating furnace, a heat treatment at a temperature of 950 ° C. for a time of 10 seconds is performed to electrically activate the implanted ions,
An N-type diffusion layer is formed on the substrate surface.

FIG. 3 shows the implantation conditions of Ge ions in FIG. Regarding the implantation energy and the implantation dose (area concentration), when the conditions in the shaded region in the figure were used, a remarkable effect of reducing the resistance of the diffusion layer was observed. In FIG. 3, for example, 1E15 indicates 1 × 10 ¹⁵ . 3 to 6, and FIG. FIG.
Indicate the values at the boundaries of the application area. In consideration of productivity and cost, it is preferable that the condition in the vicinity of the boundary of the application region, that is, a small dose be used (a large dose requires a large amount of source ion consumption and time). FIG. 4 shows the effect of the present invention when phosphorus (P) ions are used as the N-type impurities. As a Si substrate, the resistivity is 10 Ωcm, and the plane orientation (10
0), and the condition (for example, 5 k
After injecting Ge under the conditions of eV, 5 × 10 ¹⁵ / cm ² ),
Energy of P ions is 2 keV and dose is 5 × 10 ¹⁴ /
Implantation was performed under the conditions of cm ² to 2 × 10 ¹⁵ / cm ² , and then heat treatment was performed at 950 ° C. for 10 seconds to activate the implanted ions. The sheet resistance of the processed substrate was measured by a four-point probe method. As shown in FIG. 4, the sheet resistance (Ω /
sq) decreases as the implantation dose increases. Comparing with the same dose revealed that the sheet resistance was reduced by using the method of the present invention as compared with the conventional case where Ge was not implanted. In addition, it was also clarified that the effect of reducing the resistance was larger when the implantation dose was low.

Further, P ions are set at an energy of 1 keV, and heat treatment conditions for activating the implanted ions are 95
FIG. 5 shows the relationship between the implantation dose and the sheet resistance when heat treatment is performed at 0 ° C. and 1000 ° C. for 10 seconds.

FIG. 6 also shows the case where another impurity such as As (implantation energy of 7 keV) is used as the N-type impurity.
As shown in the above, the same effect was confirmed. The heat treatment condition for activating the implanted ions is 950 ° C. for 10 seconds. As is clear from FIGS. 5 and 6, even if the implantation energy of the N-type impurity, the heat treatment conditions, and the type of the N-type impurity were changed, the effect of reducing the resistance was obtained.

FIG. 7 is a characteristic diagram showing the relationship between the Ge ion implantation dose and the sheet resistance. Figure 7 is a Ge implantation energy as 5 keV, a dose of 5 × 10 ¹⁴ ~
Ge ions are implanted in a range of 1 × 10 ¹⁶ / cm ² , and then phosphorus (P) ions are used as N-type impurities, P ions are implanted at an energy of 1 keV and a dose of 5 × 10 ¹⁴ / cm ^2.
The sheet resistance (Ω / sq) when phosphorus ions are implanted under the conditions of cm ² and 8 × 10 ¹⁴ / cm ² is shown. The heat treatment conditions for activating the implanted ions are 950 ° C.
10 seconds. As is clear from FIG. 7, when the Ge ion dose is about 5 × 10 ¹⁵ or more (that is, in the application range (shaded area) in FIG. 3), there is a remarkable resistance reduction effect, and the N-type impurity It can be seen that a similar resistance reduction effect can be obtained even if the implantation dose is changed.

Next, a second embodiment of the present invention will be described with reference to FIG. In the present embodiment, an epitaxially grown film is used as a method for forming a Ge-containing Si layer on the surface according to the present invention.

First, after cleaning the surface of the Si substrate 501 using a known technique, the substrate is introduced into a UHV-CVD (Ultra High Vacuum CVD) apparatus, and the substrate is heated to 900 ° C. in a UHV chamber to spontaneously oxidize the surface of the substrate. Remove the film. Next, the substrate temperature was lowered to 600 ° C. and maintained, and Si ₂ H ₆ gas was supplied at 50 sccm.
m, GeH ₄ gas is supplied at ₁ sccm to supply a Si _1-x Ge _x film 502
Is formed to a thickness of 10 nm.

After that, similarly to the first embodiment, N-type impurity ions are implanted, and a heat treatment using, for example, a lamp heating furnace is performed to electrically activate the implanted ions to form an N-type diffusion layer. Form.

Also in the case of this embodiment, the sheet resistance of the diffusion layer was measured when P was used as the N-type impurity.
The same result (the result of FIG. 4) as that of the first example was obtained, and the effect of the present invention was confirmed. Further, even if the flow rate of the GeH ₄ gas was increased (the amount of the N-type impurities was increased), the heat treatment conditions, and the types of the N-type impurities were changed, the effect of reducing the resistance was obtained.

Next, a third embodiment in which the present invention is applied to the manufacture of a MOS-FET will be described with reference to FIGS.

Using a known technique, P-type, resistivity 10Ωc
An element isolation region 602, a gate insulating film 603, and a gate electrode 604 are formed on a Si substrate 601 having a plane orientation of (100) m (FIG. 9).

Thereafter, Ge ions are converted to an energy of, for example, 5%.
Implantation is performed under the conditions of keV and a dose of 5 × 10 ¹⁵ / cm ² , and a Ge ion implanted region (Ge-containing Si region) 605 is formed in a region that will later become a lightly doped drain (LDD) (FIG. 10).

Further, P is implanted under the conditions of an energy of 1 keV and a dose of 5 × 10 ¹⁴ / cm ² to form an LDD region 606 (FIG. 11).

Then, after forming an insulating film side wall on the side wall of the gate electrode by low-temperature CVD, As ions are implanted under the conditions of an energy of 20 keV and a dose of 5 × 10 ¹⁵ / cm ² to form an SD region (source / drain region) 607. To form

The activation of the implanted ions is performed by using a lamp heating furnace and performing a heat treatment at a substrate temperature of 950 ° C. for 10 seconds.

In the subsequent steps, a known technique is used, and a MOS
Form FETs (FIG. 12).

In the conventional method, that is, in the MOS-FET formed by the method without performing the Ge ion implantation shown in FIG.
Since the N-type ions introduced into the D and SD regions precipitate on the surface during a heat treatment in a later step, the amount of N-type ions in these regions decreases and the sheet resistance increases. On the other hand, in the case of the present invention, since the surface segregation of impurities is suppressed, the sheet resistance does not increase, and the resistance of the LDD and SD regions is reduced as compared with the prior art. Therefore, the device characteristics of the FET formed by the present invention are improved. For example, 50% for ON current
Improvement was confirmed.

Further, the formation of the Ge-containing layer before the LDD implantation can be carried out by forming an epitaxial film as in the second embodiment. An embodiment in this case will be described with reference to FIGS.

As in the third embodiment, the P-type substrate 7
01, an element isolation region 702, a gate insulating film 703, and a gate electrode 704 are formed (FIG. 13).

Next, the surface of the gate electrode is oxidized to form a polysilicon oxide film 705. Next, after cleaning the substrate, it is introduced into a UHV-CVD (ultra high vacuum CVD) apparatus,
The substrate is heated to 900 ° C. in a UHV chamber to remove a natural oxide film on the substrate surface. Further, when the substrate temperature is 600
The temperature was lowered to and kept at 50 ° C., and Si ₂ H ₆ gas was supplied at 50 sccm and GeH ₄ gas was supplied at ₁ sccm to form a 10-nm Si _1-x Ge _x film 706 (FIG. 14). At this time, since the growth of the Si _1-x Ge _x film is under a so-called selective growth condition, the Si _1-x Ge _x film grows only in the Si crystal opening.

Thereafter, LDD is performed under the same conditions as in the third embodiment.
Then, an SD region is formed, and a post-process is performed by a known technique to form a MOS-FET (FIG. 15).

Also in the case of the present embodiment, it was confirmed that the performance of the FET was improved as compared with the case where it was formed by the conventional method.

As described in the above embodiments, by forming a Ge-containing Si layer on the substrate surface before introducing the N-type impurity, the resistance of the N-type diffusion layer to be formed can be reduced. In order to exhibit this effect, the Ge concentration is desirably set to a composition ratio of 1% or more. When an epitaxial film is used as a method for forming a Ge-containing layer, growth is performed under such a condition that the composition ratio is maintained. This is important (the above condition is a condition that the Ge composition ratio becomes 1% or more). Further, when the Ge-containing layer is formed by implanting Ge ions, it is desirable to optimize the implantation energy and the dose, and it is more desirable to use the conditions in the hatched region in FIG. In the case of ion implantation, a concentration distribution is provided in the depth direction, but the maximum concentration only needs to exceed 1%, and the maximum concentration exceeds 1% in the shaded region in FIG. In addition, the peak position of the Ge concentration distribution is set to be closer to the surface than the N-type impurity introduction position in order to suppress a decrease in surface segregation during activation heat treatment of the N-type impurity.

It should be noted that although the effect is not as high as that of the embodiment even if the Ge concentration is not set to 1% or more, some effects can be obtained in the vicinity thereof. However, the present invention is not limited to this. For example, also in FIG. 7, if the Ge ion dose exceeds 1 × 10 ¹⁵ / cm ² , the sheet resistance is reduced, so that conditions can be set in this region as needed.

[0036]

As described above, the resistance of the diffusion layer can be reduced, and the characteristics of semiconductor devices such as NMOS-FETs can be improved.

[Brief description of the drawings]

FIG. 1 is a process chart for explaining an embodiment of the present invention.

FIG. 2 is a process chart for explaining a first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing implantation conditions of Ge ions in FIG. 2;

FIG. 4 is a characteristic diagram showing the effect of the present invention when phosphorus (P) ions are used as N-type impurities.

FIG. 5 is a characteristic diagram showing the effect of the present invention when phosphorus (P) ions are used as N-type impurities.

FIG. 6 is a characteristic diagram showing the effect of the present invention when arsenic (As) ions are used as N-type impurities.

FIG. 7 is a characteristic diagram showing a relationship between a Ge ion implantation dose and a sheet resistance.

FIG. 8 is a process chart for explaining a second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step showing an embodiment in which the present invention is applied to the manufacture of a MOS-FET.

FIG. 10 is a cross-sectional view showing a step showing an embodiment in which the present invention is applied to the manufacture of a MOS-FET.

FIG. 11 is a cross-sectional view showing a step showing an embodiment in which the present invention is applied to the manufacture of a MOS-FET.

FIG. 12 is a cross-sectional view showing a step showing an embodiment in which the present invention is applied to the manufacture of a MOS-FET.

FIG. 13 is a cross-sectional view showing a step of another embodiment in which the present invention is applied to the manufacture of a MOS-FET.

FIG. 14 is a cross-sectional view showing a step of another embodiment in which the present invention is applied to the manufacture of a MOS-FET.

FIG. 15 is a sectional view showing a step of another embodiment in which the present invention is applied to the manufacture of a MOS-FET.

[Explanation of symbols]

Reference Signs List 101 semiconductor Si substrate 102 Ge-containing Si layer 201 Si substrate 202 Si layer 501 Si substrate 502 Si _1-x Ge _x film 601 Si substrate 602 element isolation region 603 gate insulating film 604 gate electrode 605 Ge ion implantation region (Ge-containing Si region ) 606 LDD region 607 SD region (source / drain region) 701 P-type substrate 702 Device isolation region 703 Gate insulating film 704 Gate electrode 705 Oxidized polysilicon film 706 Si _1-x Ge _X film

Claims (7)

[Claims] 1. A semiconductor device, comprising Ge at least on a surface side of an N-type diffusion layer provided on a Si semiconductor substrate. 2. The semiconductor device according to claim 1, wherein
The semiconductor device according to claim 1, wherein the N-type diffusion layer is a source / drain region of an N-channel field effect transistor. 3. The semiconductor device according to claim 1, wherein the N-type diffusion layer has a Ge composition ratio of 1% or more. 4. A method for manufacturing a semiconductor device, comprising: forming a Ge-containing layer on a surface of a Si semiconductor substrate; and introducing an N-type impurity to form an N-type diffusion layer. 5. The method of manufacturing a semiconductor device according to claim 4, wherein said Ge-containing layer is formed by Ge ion implantation. 6. The method of manufacturing a semiconductor device according to claim 4, wherein said Ge-containing layer is a Ge deposited film. 7. The method of manufacturing a semiconductor device according to claim 4, wherein said N-type diffusion layer is formed of N-type.
A method for manufacturing a semiconductor device, comprising a source / drain region of a channel field effect transistor.