JPH08288467A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE: To simplify the manufacturing process of a compound semiconductor device which integrates complementary element with a high-speed operation element, flatten the surface and improve integration. CONSTITUTION: On semiconductor substrate 1-5 provided with a channel layer 4, semiconductor cap layer 6 and 8 which have different layer thicknesses in the adjacent area are arranged. When heat treatment is performed, at least a part of the semiconductor cap layers 6 and 8 is removed and the surface of the semiconductor substrate 1-5 is flattened. Then, on the semiconductor substrates 1-5, a compound semiconductor field-effect transistor with different threshold voltage and/or different conductivity type is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for manufacturing a compound semiconductor layer in which a plurality of field effect transistors having different threshold voltages or conductivity types are integrated on a flat substrate. It is about.

[0002]

2. Description of the Related Art In recent years, a compound semiconductor field effect transistor represented by HEMT (High Electron Mobility Transistor) or MESFET (Schottky Barrier Gate Field Effect Transistor) is capable of high-speed operation which has not been possible with silicon devices. It is used as a high-frequency semiconductor device because it can operate with low power consumption, but in order to take full advantage of it, it is necessary to keep power consumption low when the element is not operating.

To this end, it is necessary to develop an integration technology of complementary elements and high-speed operating elements, as is realized in silicon devices. Naturally, in forming complementary elements, n-channel elements and p-channel elements are formed. Both of the channel elements are required, and the threshold voltage of each is generally 0.2 to 0.4V.
And -0.2 to -0.4V must be controlled.

Conventionally, when integrating such compound semiconductor field effect transistors having different conductivity types, FIG.
As shown in, the different structures for the n-channel device and the p-channel device were prepared separately.

Referring to FIG. 9, first, on a semiconductor substrate 29 such as a semi-insulating GaAs substrate,
A buffer layer 30 such as an i-type GaAs layer, a p-doping layer 31 such as a p-type GaAs layer, a channel layer 32 such as an i-type InGaAs layer, a barrier layer 33 such as an i-type AlGaAs layer, and an i-type G
A cap layer 34 such as an aAs layer, an etching stopper layer 35 such as i-type AlGaAs, a buffer layer 36 such as an i-type GaAs layer, an n-doping layer 37 such as an n-type GaAs layer, a channel layer 38 such as an i-type InGaAs layer 38, i Type AlGaAs
A barrier layer 39 such as a layer and a cap layer 40 such as an i-type GaAs layer are sequentially epitaxially grown by MOVPE (metal organic chemical vapor deposition) or the like.

Then, using the photoresist (not shown) as a mask, the cap layer 40 to the etching stopper layer 3 are formed.
5 is selectively removed to expose the cap layer 34, and then WSi is deposited on the entire surface and patterned to provide the p-channel FET gate electrode 41 on the surface of the cap layer 34, and the cap layer 40. The E-mode FET gate electrode 42 is provided on the surface.

Then, the channel layer 32 is formed by ion implantation.
After forming contact regions reaching 38 and 38, that is, source / drain regions (not shown), ohmic electrodes (not shown) are provided on the source / drain regions to complete the complementary compound semiconductor device.

Further, when integrating the complementary element and the high-speed operation element, it is necessary to provide another field effect transistor having a different threshold voltage. Such a p-channel FET and an E mode are used. And D mode n channel FE
A conventional complementary compound semiconductor device in which T is integrated is shown in FIG.
Will be described with reference to.

First, on a semiconductor substrate 29 such as a semi-insulating GaAs substrate, see FIG.
A buffer layer 30 such as an i-type GaAs layer, a p-doping layer 31 such as a p-type GaAs layer, a channel layer 32 such as an i-type InGaAs layer, a barrier layer 33 such as an i-type AlGaAs layer, and an i-type G
A cap layer 34 such as an aAs layer, an etching stopper layer 35 such as i-type AlGaAs, a buffer layer 36 such as an i-type GaAs layer, an n-doping layer 37 such as an n-type GaAs layer, a channel layer 38 such as an i-type InGaAs layer 38, i Type AlGaAs
A barrier layer 39 such as a layer and a cap layer 4 such as an i-type GaAs layer
0, etching stopper layer 4 such as i-type AlGaAs layer
3, and the V _th adjusting layer 44 composed of the i-type GaAs layer and the like are sequentially epitaxially grown by the MOVPE method or the like.

Next, using the photoresist (not shown) as a mask, the V _th adjusting layer 44 and the etching stopper layer 4 are formed.
3 is selectively removed to expose the cap layer 40, and then a part of the exposed cap layer 40 to the etching stopper layer 35 is selectively removed using a new photoresist (not shown) as a mask. Then, the cap layer 34 is exposed, and then WSi is deposited on the entire surface and patterned to form a p-channel FE on the surface of the cap layer 34.
The gate electrode 41 for T, the gate electrode 42 for E-mode FET on the surface of the cap layer 40, and the V _th adjustment layer 44.
A D-mode FET gate electrode 45 is formed on the surface.

Finally, the channel layer 3 is formed by ion implantation.
Source / drain regions reaching 2 and 38 (not shown)
After forming, the ohmic electrodes (not shown) are provided on the source / drain regions to complete the complementary compound semiconductor device in which the complementary element and the high-speed operation element are integrated.

[0012]

However, in the conventional complementary compound semiconductor device, a p-channel FET structure including the p-doping layer 31 to the cap layer 34 and an n-type structure including the etching stopper layer 35 to the cap layer 40 are used.
It is necessary to separately prepare the structure for the channel FET,
Since the manufacturing process such as the epitaxial growth process and the selective etching process is complicated and a step is formed on the wafer surface, it is difficult to improve the degree of integration.

Also in the complementary compound semiconductor device in which the complementary element and the high-speed operation element are integrated, a p-channel FET including the p-doping layer 31 to the cap layer 34 is formed.
Structure, etching stopper layer 35 to cap layer 40
It is necessary to separately prepare an E-mode n-channel FET structure composed of and an D-mode n-channel FET structure composed of the etching stopper layer 35 to the V _th adjusting layer 44, which further complicates the manufacturing process and causes a step difference. Since it has three stages, it was more difficult to improve the degree of integration.

Therefore, according to the present invention, in manufacturing a complementary compound semiconductor device or a complementary compound semiconductor device in which a complementary element and a high-speed operation element are integrated, the manufacturing process is simplified and the surface is flattened. The purpose is to improve the degree of integration.

[0015]

FIG. 1 is an explanatory view of the principle structure of the present invention. Means for solving the problems in the present invention will be described with reference to FIG. 1 (a) and 1 (b) (1) The present invention relates to a method of manufacturing a compound semiconductor device, wherein semiconductor caps having different layer thicknesses in adjacent regions are provided on the semiconductor substrates 1 to 5 provided with the channel layer 4. After the layer 6 (8) is provided on the semiconductor substrates 1-5 and heat-treated, at least a part 8 of the semiconductor cap layer 6 (8) is removed to planarize the surface of the semiconductor substrates 1-5, and then the semiconductor It is characterized in that field effect transistors having different threshold voltages and / or conductivity types are integrated on the substrates 1 to 5.

(2) Further, in the present invention according to the above (1), the semiconductor substrate includes a semiconductor substrate 1, a buffer layer 2, a V _th adjusting doping layer 3, a channel layer 4, and a V _th adjusting doping layer 3 which are sequentially stacked on the semiconductor substrate 1. , The barrier layer 5, and the semiconductor cap layer is composed of the cap layer 6 having a uniform thickness and the annealing cap layer 8 having a predetermined pattern selectively provided thereon, and the annealing cap layer 8 is removed after the heat treatment. It is characterized by doing. In the figure, reference numeral 7 is an etching stopper layer, and reference numerals 9 and 10 are a first gate electrode and a second gate electrode, respectively.

(3) Further, in the present invention, in the method of manufacturing a compound semiconductor device, a semiconductor substrate (11 in FIG. 6) is provided with:
Buffer layer (12 in FIG. 6), V _th adjustment doping layer (13 in FIG. 6), channel layer (14 in FIG. 6), barrier layer (FIG. 6)
15), a cap layer (16 in FIG. 6), a first etching stopper layer (17 in FIG. 6), and a first annealing cap layer (18 in FIG. 6), and a first conductivity type. Removing the first anneal cap layer (18 in FIG. 6) and the first etching stopper layer (17 in FIG. 6) in the field effect transistor formation region having the anneal, and the remaining first anneal cap layer (FIG. 6) and the first etching stopper layer (17 in FIG. 6) are removed, and field effect transistors having different conductivity types are formed in the field effect transistor formation region having the first conductivity type and the other region. And a forming step.

(4) Further, in the present invention according to the above (3), the V _th adjusting doping layer (13 in FIG. 6) is a Si-doped n-type GaAs layer and the channel layer (14 in FIG. 6) is I.
It is an nGaAs layer, and the barrier layer (15 in FIG. 6) is AlGa.
As layer or InGaP layer, which is a cap layer (1 in FIG. 6).
6) and the first anneal cap layer (18 in FIG. 6) is Ga
As layer, which is the first etching stopper layer (1 in FIG. 6).
7) is an AlGaAs layer or an InGaP layer, and the first conductivity type is p-type.

(5) The present invention also provides a method for manufacturing a compound semiconductor device, wherein a semiconductor substrate (11 in FIG. 3) is provided with:
Buffer layer (12 in FIG. 3), V _th adjustment doping layer (13 in FIG. 3), channel layer (14 in FIG. 3), barrier layer (FIG. 3)
15), a cap layer (16 in FIG. 3), a first etching stopper layer (17 in FIG. 3), a first annealing cap layer (18 in FIG. 3), a second etching stopper layer (1 in FIG. 3).
9), and the step of sequentially growing the second anneal cap layer (20 in FIG. 3), the second anneal cap layer (20 in FIG. 3) and the second anneal cap layer in the field effect transistor formation region having the first threshold voltage. Etching stopper layer (1 in FIG. 3)
After removing 9), a step of performing heat treatment and a second step that remains
After removing the annealing cap layer (20 in FIG. 3) and the second etching stopper layer (19 in FIG. 3), the first annealing cap layer (18 in FIG. 3) and the first etching stopper layer (17 in FIG. 3) are removed. And a step of forming field effect transistors having different threshold voltages in the field effect transistor formation region having the first threshold voltage and the other region.

(6) Further, in the present invention according to the above (5), the V _th adjusting doping layer (13 in FIG. 3) is a Si-doped n-type GaAs layer, and the channel layer (14 in FIG. 3) is I.
nGaAs layer, and the barrier layer (15 in FIG. 3) is AlGa
As layer or InGaP layer, which is a cap layer (1 in FIG. 3).
6), the first anneal cap layer (18 in FIG. 3), and
The second annealing cap layer (20 in FIG. 3) is a GaAs layer, and the first and second etching stopper layers (1 in FIG. 3).
7, 19) is an AlGaAs layer or an InGaP layer,
Further, the first threshold voltage is 0 V or higher.

(7) Further, the present invention provides a method for manufacturing a compound semiconductor device, wherein a semiconductor substrate (11 in FIG. 7) is provided with:
Buffer layer (12 in FIG. 7), V _th adjustment doping layer (13 in FIG. 7), channel layer (14 in FIG. 7), barrier layer (FIG. 7)
15), a cap layer (16 in FIG. 7), a first etching stopper layer (17 in FIG. 7), a first annealing cap layer (18 in FIG. 7), a second etching stopper layer (1 in FIG. 7).
9), and a step of sequentially growing the second annealing cap layer (20 in FIG. 7), and a step of forming a field effect transistor forming region having a first conductivity type and a field effect transistor forming region having a first threshold voltage. The step of removing the second annealing cap layer (20 in FIG. 7) and the second etching stopper layer (19 in FIG. 7), and the first annealing cap layer (1 in FIG. 7) in the first conductivity type field effect transistor formation region.
8) and the step of performing heat treatment after removing the first etching stopper layer (17 in FIG. 7) and the remaining second annealing cap layer (20 in FIG. 7) and second etching stopper layer (19 in FIG. 7). After the removal, the first annealing cap layer (18 in FIG. 7) and the first etching stopper layer (FIG. 7).
17), the field effect transistor formation region having the first conductivity type, the field effect transistor formation region having the first threshold voltage, and the other region have different conductivity types or threshold voltages. And a step of forming a field effect transistor.

(8) Further, in the present invention according to the above (7), the V _th adjustment doping layer (13 in FIG. 7) is a Si-doped n-type GaAs layer and the channel layer (14 in FIG. 7) is I.
It is an nGaAs layer and the barrier layer (15 in FIG. 7) is AlGa.
As layer or InGaP layer, and cap layer (1 in FIG. 7).
6), the first anneal cap layer (18 in FIG. 7), and
The second annealing cap layer (20 in FIG. 7) is a GaAs layer, and the first and second etching stopper layers (1 in FIG. 7).
7, 19) is an AlGaAs layer or an InGaP layer,
Further, the first conductivity type is p-type, and the first threshold voltage is 0 V or higher.

(9) In addition, according to the present invention, in the above (5) to (8), a buffer layer (12 in FIGS. 5 and 8) and a V _th adjusting doping layer (13 in FIGS. 5 and 8) are provided. A short channel effect preventing layer (27 in FIGS. 5 and 8) is provided between them.

(10) In the present invention, in the above (9), the short channel effect preventing layer (27 in FIGS. 5 and 8) is C.
It is characterized by being a doped p-type GaAs layer.

[0025]

In the present invention, the semiconductor caps 6 and 8 having different layer thicknesses in the adjacent regions are provided on the semiconductor substrates 1 to 5 provided with the channel layer 4, and the heat treatment is performed. As a result, the conductivity type and the threshold voltage of the field effect transistor can be arbitrarily controlled by the difference in the thickness of the cap layers 6 and 8.

This situation will be described with reference to FIG. See FIG. 2 (a). FIG. 2 (a) shows the layer structure of the sample used in the experiment.
Then, on the semiconductor substrate 1 made of GaAs,
Buffer layer 2 made of i-type GaAs having a thickness of 2 and 10 nm
Electron density is 2 × 10 in thickness¹⁸cm^-3Si-doped n-type G
V consisting of aAs _thAdjusting doping layer 3, 15 nm i
Type InGaAs channel layer 4 and 20 nm
After providing the barrier layer 5 made of i-type AlGaAs,
A cap layer 6 made of i-type GaAs having a thickness of d (nm) is provided.
However, the experiment was performed by changing the thickness of the cap layer.

See FIG. 2B. FIG. 2B shows the results of CV measurement at a threshold voltage (V _th ) after heat-treating the above sample at 700 ° C. for 20 seconds. It is found that the larger the thickness of the cap layer, the smaller the amount of change in the threshold voltage (V _th ). By changing the thickness of the cap layer, the threshold voltage can be arbitrarily changed.

This phenomenon is due to the fact that Si in the V _th adjusting doping layer 3 is diffused and moved to the barrier layer 5 side by heat treatment, and when the thickness of the cap layer 6 is thin and is greatly affected by heat treatment. In this case, the amount of Si diffused increases, and as a result, the threshold voltage increases in the case of an n-channel field effect transistor.

Further, after the heat treatment, the semiconductor cap layers 6 and 8 are formed.
Of the compound semiconductor field effect transistor having at least one of the threshold voltage and the conductivity type different from each other is formed on the semiconductor substrate, so that the gate electrode, the source / drain electrode, or Since the patterning of the ion implantation mask is facilitated, the entire manufacturing process is simplified and the degree of integration is improved.

An energy band discontinuity is formed at the interface between the channel layer 4 and the barrier layer 5 based on the difference in electron affinity, and due to the discontinuity, 2 is formed on the channel layer side.
Dimensional electron gas is formed, and the semiconductor cap layer is
By forming the cap layer 6 having a uniform thickness and the annealing cap layer 8 having a predetermined pattern selectively provided thereon, the cap layers 6 and 8 having different thicknesses can be easily formed.

The buffer layer 1 is formed on the semiconductor substrate 11.
2, V _th adjustment doping layer 13, channel layer 14, barrier layer 15, cap layer 16, first etching stopper layer 1
7 and the step of sequentially growing the first anneal cap layer 18, after removing the first anneal cap layer 18 and the first etching stopper layer 17 in the field effect transistor forming region having the first conductivity type, heat treatment is performed. By performing the process, the threshold voltage can be controlled to be a p-channel type in the region where the first annealing cap layer 18 is removed and an n-channel type in the other regions.

Further, after removing the first anneal cap layer 18 and the first etching stopper layer 17 to flatten the surface, field effect transistors of different conductivity types are formed in the respective regions, so that the whole manufacturing process is performed. Is simplified and the degree of integration is also improved.

Further, the V _th adjustment doping layer 13 is a Si-doped n-type GaAs layer, and the channel layer 14 is InGaA.
s layer, and the barrier layer 15 is an AlGaAs layer or InGaP
As a layer, the cap layer 16 and the first annealing cap layer 1
8 is a GaAs layer and the first etching stopper layer 17 is an AlGaAs layer or an InGaP layer, a complementary field effect transistor can be specifically realized.

The buffer layer 1 is formed on the semiconductor substrate 11.
2, V _th adjustment doping layer 13, channel layer 14, barrier layer 15, cap layer 16, first etching stopper layer 1
7, the first annealing cap layer 18, the second etching stopper layer 19, and the second annealing cap layer 20 are sequentially grown, and then the second annealing cap layer in the field effect transistor formation region having the first threshold voltage. 20
By performing the step of removing the second etching stopper layer 19 and then performing the heat treatment, the region where the second annealing cap layer 20 is removed is set to the E mode, and the other region is set to the D mode.
The mode can be controlled.

Further, the V _th adjusting doping layer 13 is a Si-doped n-type GaAs layer, and the channel layer 14 is InGaA.
s layer, and the barrier layer 15 is an AlGaAs layer or InGaP
As the layers, the cap layer 16 and the first annealing cap layer 1
8 and the second annealing cap layer 20 are GaAs layers, and the first and second etching stopper layers 17 and 19 are A
By using the 1GaAs layer or the InGaP layer, it is possible to specifically integrate high-speed field effect transistors having different threshold voltages.

The buffer layer 1 is formed on the semiconductor substrate 11.
2, V _th adjustment doping layer 13, channel layer 14, barrier layer 15, cap layer 16, first etching stopper layer 1
7, the first annealing cap layer 18, the second etching stopper layer 19, and the second annealing cap layer 20 are sequentially grown, and then the field effect transistor forming region having the first conductivity type and the first threshold voltage are formed. Second annealing cap layer 2 in the field effect transistor formation region having
0 and the second etching stopper layer 19 are removed, and then the first annealing cap layer 18 and the first etching stopper layer 17 in the first conductivity type field effect transistor forming region are removed and then heat treatment is performed. By doing so, the first and second annealing cap layers 18, 2
The region where 0 is removed can be controlled to be a p-channel type, the region where the second annealing cap layer 20 is removed can be controlled to be the E mode, and the other regions can be controlled to be the D mode.

The V _th adjustment doping layer 13 is a Si-doped n-type GaAs layer, and the channel layer 14 is InGaA.
s layer, and the barrier layer 15 is an AlGaAs layer or InGaP
As the layers, the cap layer 16 and the first annealing cap layer 1
8 and the second annealing cap layer 20 are GaAs layers, and the first and second etching stopper layers 17 and 19 are A
By using the 1GaAs layer or the InGaP layer, the complementary piezoelectric field effect transistor and the high-speed D-mode field effect transistor can be specifically integrated.

Since the short channel effect preventing layer 27 is provided between the buffer layer 12 and the V _th adjusting doping layer 13, the space charge limiting current is prevented from flowing to the buffer layer 12 side below the channel layer 14. It is possible to prevent the short channel effect.

Since the short channel effect preventing layer 27 is a C-doped p-type GaAs layer, the diffusion coefficient of C is small, so that p-type Ga is used in the heat treatment step of controlling the threshold voltage.
Since the solid phase diffusion of C from As is almost negligible, the presence of the short channel effect prevention layer 27 does not affect the threshold voltage control.

[0040]

EXAMPLE Referring to FIGS. 3 and 4, an E mode FET and a D
A manufacturing process of the first embodiment of the present invention in which mode FETs are integrated will be described. See FIG. 3A. First, on the semi-insulating GaAs substrate 11, an undoped i-type GaAs layer 12 having a thickness of 500 nm and serving as a buffer layer by the MOVPE method, and having an electron concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of Si-doped n-type GaAs layer 13 for adjusting the threshold voltage of 6 nm, channel layer 15 nm thick undoped i-type InGaAs layer 14, barrier layer thickness 2
Undoped i-type AlGaAs layer 15 having a thickness of 0 nm, undoped i-type GaAs layer 16 having a thickness of 10 nm serving as a cap layer, undoped i-type AlGaAs layer 17 having a thickness of 3 nm serving as an etching stopper layer, and thickness serving as an annealing cap layer. I-type GaAs layer 18 undoped at 20 nm,
An undoped i-type AlGaAs layer 19 having a thickness of 3 nm, which serves as an etching stopper layer, and an undoped i-type GaAs layer 20 having a thickness of 80 nm, which serves as an annealing cap layer, are sequentially epitaxially grown.

Then, the i-type GaAs layer 20 in the E-mode FET formation region is removed by dry etching using CCl ₂ F ₂ as an etching gas, and then the i-type AlGa exposed by the ammonia-based etching solution is used.
After removing the As layer 19, in an N ₂ gas atmosphere, 70
Heat treatment for 20 seconds at a temperature of 0 ° C.

By this heat treatment, as can be seen from FIG. 2 (b), the cap layer in the E-mode FET formation planned region is 30 nm (10 + 20), so the threshold voltage rises by about 0.45 V, and the other regions Then, since the thickness of the cap layer is 110 nm (10 + 20 + 80), the threshold voltage hardly changes.

Next, referring to FIG. 3B, the remaining i-type GaAs layer 20 and i-type AlGa
After removing the As layer 19, the i-type GaAs layer 18 and the i-type GaAs layer 18 are removed.
The type AlGaAs layer 17 is also removed to flatten the surface, and then WSi is deposited on the entire surface by a sputtering method and patterned, whereby the E-mode FET gate electrode 2 is formed.
The gate electrode 22 for 1 and D mode FET is formed.

Next, as shown in FIG. 4 (c), Si is selectively ion-implanted and an activation process is performed at 800 ° C. for 5 seconds to form an i-type Ga that is a channel layer.
The source region 23 and the drain region 2 reaching the As layer 14
4 is formed.

4D. Finally, the source / drain electrodes 25 and 26 are formed by depositing and patterning an ohmic electrode made of Au.Ge/Au, and finally the threshold voltage is 0.2.
An E mode FET of V and a D mode FET having a threshold voltage of -0.2V are obtained.

In the first embodiment, since the threshold voltage of each field effect transistor is controlled by the thickness of the cap layer, it is necessary to provide a dedicated structure for each field effect transistor having a different threshold voltage as in the conventional case. Not again
Since the field effect transistor is formed by removing the cap layer after the heat treatment, the manufacturing process of the compound semiconductor device is facilitated and the degree of integration is improved.

Next, a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, a short channel effect prevention layer is provided between the i-type GaAs layer 12 serving as the buffer layer and the n-type GaAs layer 13 for adjusting the threshold voltage in the first embodiment. The structure and manufacturing process are substantially the same as those of the first embodiment except that the thickness of the n-type GaAs layer 13 is increased.

5 (a). First, on the semi-insulating GaAs substrate 11, an undoped i-type GaAs layer 12 having a thickness of 500 nm to be a buffer layer by MOVPE method, and a hole concentration of 2 × 10 ¹⁸ cm ^−3. -Doped p-type Ga to be a short channel prevention layer with a thickness of 5 nm
As layer 27, electron concentration is 2 × 10 ¹⁸ cm ⁻³ and thickness is 11
Si-doped n-type GaA for adjusting the threshold voltage of nm
s layer 13, channel layer 15 nm thick with undoped i-type InGaAs layer 14, barrier layer thickness 20 nm
Undoped i-type AlGaAs layer 15 and a 10-nm-thick undoped i-type GaAs layer 16 serving as a cap layer,
An undoped i-type AlGaAs layer 17 having a thickness of 3 nm to be an etching stopper layer, an undoped i-type GaAs layer 18 having a thickness of 20 nm to be an annealing cap layer, and an undoped i-type A having a thickness of 3 nm to be an etching stopper layer.
The lGaAs layer 19 and an undoped i-type GaAs layer 20 having a thickness of 80 nm, which will be an annealing cap layer, are sequentially epitaxially grown.

As shown in FIG. 5B, the subsequent steps are the same as in the first embodiment, and the E-mode FET having a threshold voltage of 0.2V and the D-mode FET having a threshold voltage of -0.2V.
A mode FET is obtained. Note that the source / drain regions and the source / drain electrodes are omitted in the figures, and the same applies to the following figures. In this case, p-type G
Since the diffusion coefficient of C (carbon) contained in the aAs layer 27 is small, it hardly diffuses in the heat treatment step for controlling the threshold voltage, and does not substantially affect the threshold voltage control.

Here, the short channel effect will be briefly described. The short-channel effect is a transconductance g as the gate length of a field effect transistor becomes shorter.
This is a phenomenon in which _m decreases. First, the depletion layer under the gate electrode changes from a semi-elliptical shape to a semi-circular shape, and compared with the electric field component in the depth direction that controls the channel current, it is lateral from the gate edge. This phenomenon occurs because the electric field component extending in the direction cannot be ignored.

Secondly, there is a phenomenon caused by the flow of a space charge limiting current in the layer on the substrate side below the channel layer 14, that is, the n-type GaAs layer 13 for adjusting the threshold voltage, due to the shortening of the channel, The second embodiment of the present invention reduces this space charge limiting current.

In the second embodiment, between the i-type GaAs layer 12 serving as a buffer layer and the n-type GaAs layer 13 for adjusting the threshold voltage, a p serving as a short channel prevention layer is provided.
Since the n-type GaAs layer 27 is inserted, the n-type GaAs layer 13 is energetically lifted by the pn junction formed between the n-type GaAs layer 13 and the p-type GaAs layer 27 and acts as an electron barrier. The current does not flow through 13, and the short channel effect can be prevented.

Next, a third embodiment of the present invention, which is a complementary field effect transistor, will be described with reference to FIG. See FIG. 6A. First, on the semi-insulating GaAs substrate 11, an undoped i-type GaAs layer 12 with a thickness of 500 nm to be a buffer layer by the MOVPE method, an electron concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of Si-doped n-type GaAs layer 13 for adjusting the threshold voltage of 6 nm, channel layer 15 nm thick undoped i-type InGaAs layer 14, barrier layer thickness 2
An undoped i-type AlGaAs layer 15 having a thickness of 0 nm, an undoped i-type GaAs layer 16 having a thickness of 10 nm serving as a cap layer, an undoped i-type AlGaAs layer 17 having a thickness of 3 nm serving as an etching stopper layer, and an annealing cap layer. An undoped i-type GaAs layer 18 having a thickness of 20 nm is sequentially epitaxially grown.

Then, the i-type GaAs layer 18 in the p-channel FET formation planned region is removed by dry etching using CCl ₂ F ₂ as an etching gas, and then the i-type AlG exposed by the ammonia-based etching solution is used.
After removing the aAs layer 17, in an N ₂ gas atmosphere,
Heat treatment is performed at a temperature of 00 ° C. for 20 seconds.

By this heat treatment, as can be seen from FIG. 2B, since the cap layer in the p-channel FET formation region is 10 nm, the threshold voltage rises by about 0.85 V,
In addition, the thickness of the cap layer is 30 nm in other regions.
The threshold voltage, which is (10 + 20), increases by about 0.45V.

Next, referring to FIG. 6B, the remaining i-type GaAs layer 18 and i-type AlGa
After removing the As layer 17 and flattening the surface, WSi is deposited on the entire surface by a sputtering method and patterned to form a p-channel FET gate electrode 28 and an n-channel E-mode FET gate electrode 21.

Next, Si is selectively ion-implanted on the n-channel FET side, and M on the p-channel FET side.
After selectively ion-implanting g, an activation treatment is performed at 800 ° C. for 5 seconds to form source / drain regions (not shown) reaching the i-type GaAs layer 14 which is a channel layer, and then an ohmic electrode is deposited. Then, a source / drain electrode (not shown) is formed by patterning and p-channel FET with a threshold voltage of -0.2V finally.
Thus, an E-mode FET having a threshold voltage of 0.2 V can be obtained.

In the third embodiment, since the conductivity type of each field effect transistor is controlled by the thickness of the cap layer, it is necessary to provide a dedicated structure for each field effect transistor having a different conductivity type as in the conventional case. In addition, since the field effect transistor is formed by removing the cap layer after the heat treatment, the manufacturing process of the complementary compound semiconductor device is facilitated and the degree of integration is improved.

Next, a fourth embodiment of the present invention, which is a complementary field effect transistor, will be described with reference to FIG. See FIG. 7A. First, on the semi-insulating GaAs substrate 11, an undoped i-type GaAs layer 12 having a thickness of 500 nm and serving as a buffer layer by the MOVPE method, and having an electron concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of Si-doped n-type GaAs layer 13 for adjusting the threshold voltage of 6 nm, channel layer 15 nm thick undoped i-type InGaAs layer 14, barrier layer thickness 2
Undoped i-type AlGaAs layer 15 having a thickness of 0 nm, undoped i-type GaAs layer 16 having a thickness of 10 nm serving as a cap layer, undoped i-type AlGaAs layer 17 having a thickness of 3 nm serving as an etching stopper layer, and thickness serving as an annealing cap layer. I-type GaAs layer 18 undoped at 20 nm,
An undoped i-type AlGaAs layer 19 having a thickness of 3 nm, which serves as an etching stopper layer, and an undoped i-type GaAs layer 20 having a thickness of 80 nm, which serves as an annealing cap layer, are sequentially epitaxially grown.

Then, the i-type GaAs layer 20 in the p channel FET and E mode FET formation planned region is removed by dry etching using CCl ₂ F ₂ as an etching gas, and then exposed by an ammonia-based etching solution. After removing the type AlGaAs layer 19, the i type GaAs layer 18 in the p-channel FET formation region is removed by dry etching similarly using CCl ₂ F ₂ as an etching gas, and then exposed by an ammonia-based etching solution. After removing the i-type AlGaAs layer 17 which is, in an N ₂ gas atmosphere, 2 at a temperature of 700 ° C.
Heat treatment for 0 seconds.

By this heat treatment, as can be seen from FIG. 2B, the cap layer in the p-channel FET formation region has a thickness of 10 nm, so that the threshold voltage rises by about 0.85 V,
In addition, the thickness of the cap layer is 30 nm in other regions.
(10 + 20) and 110 nm (10 + 20 + 80)
Thus, the threshold voltage rises by about 0.45V in the thickness region of 30 nm, and the threshold voltage hardly changes in the thickness region of 110 nm.

Next, referring to FIG. 7B, the remaining i-type GaAs layer 20 to i-type AlGa
After removing the As layer 17 to planarize the surface, WSi is deposited on the entire surface by a sputtering method and patterned to form a p-channel FET gate electrode 28, an n-type E-mode FET gate electrode 21, and D mode FE
The T gate electrode 22 is formed.

Next, Si is selectively ion-implanted on the n-channel FET side, and M on the p-channel FET side.
After selectively ion-implanting g, an activation treatment is performed at 800 ° C. for 5 seconds to form source / drain regions (not shown) reaching the i-type GaAs layer 14 which is a channel layer, and then an ohmic electrode is deposited. Then, the source / drain electrodes (not shown) are formed by patterning, and finally the p-channel FE having a threshold voltage of -0.2V is formed.
T, an E-mode FET with a threshold voltage of 0.2V, and a D-mode FET with a threshold voltage of -0.2V are obtained.

In the fourth embodiment, the conductivity type and the threshold voltage of each field effect transistor are controlled by the thickness of the cap layer, so that each field effect transistor having a different conductivity type and a different threshold voltage is dedicated as in the conventional case. Since it is not necessary to provide the structure and the field effect transistor is formed by removing the cap layer after the heat treatment, the manufacturing process of the complementary compound semiconductor device is facilitated and the integration degree is improved.

Next, a fifth embodiment of the present invention will be described with reference to FIG. In the fifth embodiment, a short channel effect prevention layer is provided between the i-type GaAs layer 12 serving as the buffer layer and the n-type GaAs layer 13 for adjusting the threshold voltage in the fourth embodiment. The structure and manufacturing process other than increasing the thickness of the n-type GaAs layer 13 are substantially the same as those of the fourth embodiment.

8 (a). First, on the semi-insulating GaAs substrate 11, an undoped i-type GaAs layer 12 having a thickness of 500 nm to be a buffer layer by MOVPE method, and a hole concentration of 2 × 10 ¹⁸ cm ^−3. -Doped p-type Ga to be a short channel prevention layer with a thickness of 5 nm
As layer 27, electron concentration is 2 × 10 ¹⁸ cm ⁻³ and thickness is 11
Si-doped n-type GaA for adjusting the threshold voltage of nm
s layer 13, channel layer 15 nm thick with undoped i-type InGaAs layer 14, barrier layer thickness 20 nm
Undoped i-type AlGaAs layer 15 and a 10-nm-thick undoped i-type GaAs layer 16 serving as a cap layer,
An undoped i-type AlGaAs layer 17 having a thickness of 3 nm to be an etching stopper layer, an undoped i-type GaAs layer 18 having a thickness of 20 nm to be an annealing cap layer, and an undoped i-type A having a thickness of 3 nm to be an etching stopper layer.
The lGaAs layer 19 and an undoped i-type GaAs layer 20 having a thickness of 80 nm, which will be an annealing cap layer, are sequentially epitaxially grown.

As shown in FIG. 8B, the subsequent steps are the same as in the first embodiment, and the threshold voltage is-.
0.2V p-channel FET, E with threshold voltage of 0.2V
A mode FET and a D mode FET having a threshold voltage of -0.2V can be obtained.

In the fifth embodiment, the short channel effect can be prevented as in the second embodiment, and the p-type G
Since the diffusion coefficient of C (carbon) contained in the aAs layer 27 is small, it hardly diffuses in the heat treatment step for controlling the threshold voltage, and does not substantially affect the threshold voltage control.

In each of the above embodiments, the barrier layer 1
5 and the i-type Al as the etching stopper layers 17 and 19
Although GaAs is used, i that is substantially lattice-matched with GaAs
Type InGaP may also be used.

In each of the above embodiments, the InGaAs used as the channel layer 14 has a mixed crystal ratio x of 0 to 0.
0.30 In _x Ga _1-x As (GaA when x = 0)
s), and the thickness is not limited to 15 nm, but is preferably in the range of 10 to 100 nm. Further, AlGaAs used as the barrier layer 15 has a mixed crystal ratio y of 0.2 to 1. Al _y Ga _1-y As of 0, and AlGaAs used as the etching stopper layers 17 and 19 has a mixed crystal ratio z of 0.2 to 0.4 Al _z Ga.
_1-z As. In addition, the overall structure is GaAs /
InGa used with AlGaAs HEMT
An As / InAlAs system structure may be used.

The heat treatment conditions in each of the above examples are 700 ° C. and 20 seconds, but the conditions are not limited to these conditions, and the temperature is preferably in the range of 600 to 850 ° C., for example. The processing time is preferably in the range of 5 to 40 seconds. In this case, when the temperature is high, the amount of change in the threshold voltage is large, and even when the processing time is long, the amount of change in the threshold voltage is large.

Further, in each of the above embodiments, the etching stopper layer 1 is formed in order to accurately etch the annealing cap layers 18 and 20 by a simple etching process.
Although the etching stopper layers 17 and 19 are provided, the etching stopper layers 17 and 19 are not always necessary if highly accurate etching is performed.

Furthermore, in each of the above embodiments, the annealing cap layers 18 and 20 and the etching stopper layer 1 are used.
When patterning 7 and 19, dry etching and wet etching are combined.
It may be performed only by dry etching or wet etching.

[0074]

According to the present invention, since the conductivity type and the threshold voltage of each field effect transistor are controlled by the thickness of the cap layer, a dedicated field effect transistor having a different conductivity type and a different threshold voltage is used as in the prior art. Since it is not necessary to provide a structure and the field effect transistor is formed by removing the cap layer after the heat treatment, the manufacturing process of the compound semiconductor device is facilitated and the degree of integration is improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory view of the operation of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process up to the middle of the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of the manufacturing process after the process of FIG. 3 of the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a manufacturing process according to the second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process according to the third embodiment of the present invention.

FIG. 7 is an explanatory diagram of a manufacturing process according to the fourth embodiment of the present invention.

FIG. 8 is an explanatory diagram of a manufacturing process according to the fifth embodiment of the present invention.

FIG. 9 is a cross-sectional view of essential parts of a conventional complementary compound semiconductor device.

FIG. 10 is a cross-sectional view of essential parts of a complementary compound semiconductor device in which conventional high-speed operation elements are combined.

[Explanation of symbols]

1 semiconductor substrate 2 buffer layer 3 _Vth adjustment doping layer 4 channel layer 5 barrier layer 6 cap layer 7 etching stopper layer 8 annealing cap layer 9 first gate electrode 10 second gate electrode 11 semi-insulating GaAs substrate 12 i-type GaAs layer 13 n-type GaAs layer 14 i-type InGaAs layer 15 i-type AlGaAs layer 16 i-type GaAs layer 17 i-type AlGaAs layer 18 i-type GaAs layer 19 i-type AlGaAs layer 20 i-type GaAs layer 21 E-mode FET gate electrode 22 D-mode FET gate electrode 23 Source region 24 Drain region 25 Source electrode 26 Drain electrode 27 p-type GaAs layer 28 p-channel FET gate electrode 29 Semiconductor substrate 30 Buffer layer 31 p Doping layer 32 Channel layer 33 Barrier layer 34 Cap layer 35 Etch Gusutoppa layer 36 buffer layer 37 n-doped layer 38 channel layer 39 barrier layer 40 cap layer 41 p-channel FET gate electrode 42 E-mode FET gate electrode 43 an etching stopper layer 44 V _th adjustment layer 45 D mode gate electrode FET

Claims (10)

[Claims] 1. A semiconductor cap layer having a channel layer formed thereon, semiconductor cap layers having different layer thicknesses are provided in adjacent regions, heat treatment is performed, and then at least a part of the semiconductor cap layer is removed to remove the semiconductor. A method of manufacturing a compound semiconductor device, comprising: planarizing a surface of a substrate; and then integrating field effect transistors having different threshold voltages and / or conductivity types on the semiconductor substrate. 2. The semiconductor substrate comprises a semiconductor substrate, a buffer layer, a threshold voltage adjusting doping layer, a channel layer, and a barrier layer which are sequentially stacked on the semiconductor substrate, and the semiconductor cap layer comprises: 2. The compound semiconductor according to claim 1, comprising a cap layer having a uniform thickness and an annealing cap layer having a predetermined pattern selectively provided on the cap layer, the annealing cap layer being removed after the heat treatment. Device manufacturing method. 3. A buffer layer, a threshold voltage adjusting doping layer, a channel layer, a barrier layer, a cap layer, and
After sequentially growing the first etching stopper layer and the first annealing cap layer, and after removing the first annealing cap layer and the first etching stopper layer in the field effect transistor formation region having the first conductivity type. A step of performing a heat treatment, a step of removing the remaining first annealing cap layer and the first etching stopper layer, and a field effect transistor forming region having the first conductivity type and a region other than the field effect transistor forming region having the conductivity type. And a step of forming field effect transistors different from each other. 4. The threshold voltage adjusting doping layer is a Si-doped n-type GaAs layer, and the channel layer is InGa.
It is an As layer and the barrier layer is an AlGaAs layer or InG.
an aP layer, the cap layer and the first annealing cap layer are GaAs layers, the first etching stopper layer is an AlGaAs layer or an InGaP layer, and the first conductivity type is p-type 4. The method for manufacturing a compound semiconductor device according to claim 3, wherein. 5. A buffer layer, a threshold voltage adjusting doping layer, a channel layer, a barrier layer, a cap layer, and
A first etching stopper layer, a first annealing cap layer,
After sequentially growing a second etching stopper layer and a second annealing cap layer, and after removing the second annealing cap layer and the second etching stopper layer in the field effect transistor forming region having the first threshold voltage. A step of performing a heat treatment, a step of removing the remaining second annealing cap layer and the second etching stopper layer and then removing the first annealing cap layer and the first etching stopper layer, and the first threshold voltage And a step of forming field effect transistors having different threshold voltages in a field effect transistor formation region having the above and other regions. 6. The threshold voltage adjusting doping layer is a Si-doped n-type GaAs layer, and the channel layer is InGa.
It is an As layer and the barrier layer is an AlGaAs layer or InG.
aP layer, the cap layer, the first annealing cap layer and the second annealing cap layer are GaAs layers, and the first and second etching stopper layers are AlG.
6. The method for manufacturing a compound semiconductor device according to claim 5, wherein the compound semiconductor device is an aAs layer or an InGaP layer, and the first threshold voltage is 0 V or higher. 7. A buffer layer, a threshold voltage adjusting doping layer, a channel layer, a barrier layer, a cap layer, on a semiconductor substrate,
A first etching stopper layer, a first annealing cap layer,
A step of sequentially growing a second etching stopper layer and a second annealing cap layer, and the second annealing of a field effect transistor forming region having a first conductivity type and a field effect transistor forming region having a first threshold voltage A step of removing the cap layer and the second etching stopper layer; a step of removing the first annealing cap layer and the first etching stopper layer in the first conductivity type field effect transistor forming region and then performing a heat treatment. A step of removing the remaining second annealing cap layer and the second etching stopper layer and then removing the first annealing cap layer and the first etching stopper layer; and a field effect transistor having the first conductivity type. A forming region, a field effect transistor forming region having the first threshold voltage, and Compounds method of manufacturing a semiconductor device which comprises a step of forming a different field effect transistor conductivity types or the threshold voltage from each other in a region other than. 8. The threshold voltage adjusting doping layer is a Si-doped n-type GaAs layer, and the channel layer is InGa.
It is an As layer and the barrier layer is an AlGaAs layer or InG.
an aP layer, and the cap layer, the first annealing cap layer, and the second annealing cap layer are GaAs.
And the first and second etching stopper layers are A
8. The compound semiconductor device manufacturing method according to claim 7, wherein the compound semiconductor device is an InGaAs layer or an InGaAs layer, the first conductivity type is p-type, and the first threshold voltage is 0 V or more. Method. 9. The compound semiconductor device according to claim 5, further comprising a short channel effect preventing layer provided between the buffer layer and the threshold voltage adjusting doping layer. Production method. 10. The method for manufacturing a compound semiconductor device according to claim 9, wherein the short channel effect preventing layer is a C-doped p-type GaAs layer.