CN102664166B - CMOS (complementary metal-oxide-semiconductor) device and manufacturing method thereof - Google Patents
CMOS (complementary metal-oxide-semiconductor) device and manufacturing method thereof Download PDFInfo
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- CN102664166B CN102664166B CN2012101751193A CN201210175119A CN102664166B CN 102664166 B CN102664166 B CN 102664166B CN 2012101751193 A CN2012101751193 A CN 2012101751193A CN 201210175119 A CN201210175119 A CN 201210175119A CN 102664166 B CN102664166 B CN 102664166B
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Abstract
The invention provides a CMOS (complementary metal-oxide-semiconductor) device and a manufacturing method thereof. The manufacturing method for the CMOS device includes the following steps: respectively forming a first groove and a second groove in a Si (silicon) substrate with a SiO2 (silicon dioxide) layer, wherein the first groove is in a first depth, the second groove is in a second depth which is larger than the first depth; respectively forming a Ge (germanium) layer, an etch stop layer and a III-V family semiconductor layer in the first groove and the second groove; etching the above formed structure till the Ge layer in the first groove via optional corrosion technology, and enabling the Ge layer, the SiO2 layer and the III-V family semiconductor layer to be located in the same surface; manufacturing a PMOS (p-channel metal oxide semiconductor) device on the Ge layer and an NMOS (n-channel metal oxide semiconductor) device on the III-V family semiconductor layer to complete manufacturing of the CMOS device. The substrate with mixture of grooves of Ge layer and III-V family semiconductor layer can be obtained via the optional corrosion technology and polishing technology after epitaxy. The manufacturing method for the CMOS device is simple in technology and beneficial to lower cost. Manufacturing the CMOS device on the substrate is high in speed and beneficial to improvement of performances of the CMOS device.
Description
Technical field
The invention belongs to semiconductor applications, particularly relate to a kind of cmos device and preparation method thereof.
Background technology
Metal oxide semiconductor field-effect (MOS) transistor can be divided into N raceway groove and the large class of P raceway groove two, P channel silicon MOS field-effect transistor has Liang Ge P+ district on the N-type silicon substrate, be called respectively source electrode and drain electrode, admittance not between the two poles of the earth, while on grid, being added with enough negative voltages (source ground), N-type silicon face under grid presents P type inversion layer, becomes the raceway groove that connects source electrode and drain electrode.Change grid voltage and can change the electron density in raceway groove, thereby change the resistance of raceway groove.This MOS field-effect transistor is called the P-channel enhancement type field-effect transistor.If the N-type surface of silicon does not add grid voltage, just there do not is P type inversion-layer channel, add suitable bias voltage, can make the resistance of raceway groove increase or reduce.Such MOS field-effect transistor is called P channel depletion type field-effect transistor.Be referred to as the PMOS transistor.
The hole mobility of P channel MOS transistor is low, thereby in the situation that the physical dimension of MOS transistor and operating voltage absolute value are equal, the transistorized mutual conductance of PMOS is less than the N-channel MOS transistor.In addition, the absolute value of P channel MOS transistor threshold voltage is generally higher, requires to have higher operating voltage.The voltage swing of its power supply and polarity, with bipolar transistor---transistor-transistor logic circuit is incompatible.PMOS is large because of logic swing, and the charging and discharging process is long, and the device mutual conductance is little in addition, so operating rate is lower, after nmos circuit (seeing N channel metal-oxide-semiconductor integrated circuit) occurred, majority was replaced by nmos circuit.Just, because the PMOS circuit technology is simple, low price, in some, scale and small-scale digital control circuit still adopt the PMOS circuit engineering.
CMOS consists of jointly PMOS pipe and NMOS pipe, and its feature is low-power consumption.The gate circuit formed due to a pair of MOS in CMOS moment PMOS conducting NMOS conducting otherwise all by, more much higher than linear triode (BJT) efficiency, so power consumption is very low.Therefore, CMOS has application very widely at semiconductor applications, is also one of most important basic building block of current semiconductor device.
Nineteen sixty-five, Gordon Moore makes the prophesy of " transistor size on chip is along with time index increases, and the transistor on unit are doubled in every 18 months ".Along with constantly dwindling of field effect transistor characteristic size, its device performance is more and more higher, and operating rate is also more and more faster, but its characteristic size is near the limit of Si material.Must take new technology to improve performance (new material, new construction, new technology).Wherein, introducing new channel material is main innovation way.Research shows that Ge has higher hole mobility, III-V family semi-conducting material has higher electron mobility, therefore by above-mentioned channel material and the integrated important technology approach that obtains the high-performance CMOS device that become of current semiconductor Si technique.
Therefore provide that a kind of technique is simple, low-cost, the preparation method of high performance composite material raceway groove and cmos device is real belongs to necessary.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of cmos device and preparation method thereof, a kind of technique is simple, low-cost to provide, preparation method and a kind of high performance cmos device of high performance composite material raceway groove and cmos device.
Reach for achieving the above object other relevant purposes, the invention provides a kind of manufacture method of cmos device, described manufacture method comprises step at least: 1) a Si substrate is provided, and forms the SiO with first thickness on described Si substrate
2Layer; 2) the described SiO of etching
2Layer and Si substrate, form the first groove that at least one reaches first degree of depth; And the described SiO of etching
2Layer and Si substrate, form the second groove that at least one reaches second degree of depth, and described second degree of depth is greater than described first degree of depth; 3) in described the first groove and the second groove, form the Ge layer, and make the upper surface of the upper surface of the Ge layer in described the first groove higher than described Si substrate, the upper surface of the Ge layer in described the second groove is lower than the upper surface of described Si substrate; 4) in described Ge layer surface, form and only carve layer; 5) in described stopping, carve a layer surface formation III-V family semiconductor layer, and make the upper surface of the upper surface of the interior III of described the second groove-V family semiconductor layer higher than the Ge layer in described the first groove; 6) surface of the above-mentioned resulting structures of etching is until expose the Ge layer in described the first groove, and makes described Ge layer, SiO
2The upper surface of layer and III-V family semiconductor layer is in same plane; 7) in described Ge layer, prepare the PMOS device, prepare nmos device in described III-V family semiconductor layer.
In the manufacture method of cmos device of the present invention, adopt the selective epitaxial technology to form described Ge layer, stop and carve layer and III-V family semiconductor layer.
In the manufacture method of cmos device of the present invention, the material of described III-V family semiconductor layer is the combination in any of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb or above-mentioned material.
In the manufacture method of cmos device of the present invention, be Si described only quarter layer
xGe
yC
zSn
(1-x-y-z)Layer, component are different from the III of SiGe layer, B or the P doping of the second III of described III-V family semiconductor layer-V family semiconductor layer, B or P doping-V family semiconductor layer.
In the manufacture method of cmos device of the present invention, in described step 6), first adopt the surface of the above-mentioned resulting structures of selective corrosion technology etching to the interior layer at only quarter of described the first groove, then continue etching until expose the Ge layer in described the first groove, and make described Ge layer, SiO
2The surface of layer and III-V family semiconductor layer is in same plane.
As a preferred version of the manufacture method of cmos device of the present invention, described step 6) also comprises and adopts the chemical mechanical polishing method to described Ge layer, SiO
2Layer and the step that III-V family semiconductor layer surface is carried out polishing.
In the manufacture method of cmos device of the present invention, described step 7) comprises step at least: 7-1) described Ge layer is carried out to the N-type conductive type ion and inject formation N trap, described III-V family semiconductor layer is carried out to P-type conduction type Implantation and form the P trap; 7-2) in described Ge layer surface and III-V family semiconductor layer surface makes the grid region structure; 7-3) described Ge layer is carried out to P-type conduction type Implantation in structure both sides, described grid region, to form source region and the drain region of PMOS pipe; 7-4) described III-V family semiconductor layer is carried out to the injection of N-type conductive type ion in structure both sides, described grid region, to form source region and the drain region of NMOS pipe; 7-5) prepare source electrode and the drain electrode of PMOS pipe and NMOS pipe.
The present invention also provides the cmos device of the manufacture method made of the described cmos device of the above-mentioned any one of a kind of foundation.
As mentioned above, cmos device of the present invention and preparation method thereof has following beneficial effect: in having SiO
2In the Si substrate of layer, form respectively the first groove of first degree of depth and be greater than the second groove of second degree of depth of described first degree of depth, in described the first groove and the second groove, form respectively the Ge layer, stop and carve layer and III-V family semiconductor layer, then adopt selective corrosion technology etching said structure to the interior Ge layer of described the first groove, and make described Ge layer, SiO
2Layer and III-V family semiconductor layer are in same plane, finally on described Ge layer, make the PMOS device, on described III-V family semiconductor layer, make nmos device to complete the making of described cmos device.The present invention only need delay outside by selective corrosion technique and glossing can obtain the substrate with Ge layer and III-V family semiconductor layer composite material raceway groove, and technique is simple, is conducive to reduce costs; On this substrate, prepare cmos device, have higher operating rate, be conducive to improve the performance of device.
The accompanying drawing explanation
Fig. 1 ~ 2 are shown as the structural representation that the manufacture method step 1) of of the present invention kind of cmos device presents.
Fig. 3 ~ 4 are shown as the manufacture method step 2 of of the present invention kind of cmos device) structural representation that presents.
Fig. 5 is shown as the structural representation that the manufacture method step 3) of of the present invention kind of cmos device presents.
Fig. 6 is shown as the structural representation that the manufacture method step 4) of of the present invention kind of cmos device presents.
Fig. 7 is shown as the structural representation that the manufacture method step 5) of of the present invention kind of cmos device presents.
Fig. 8 ~ 9 are shown as the structural representation that the manufacture method step 6) of of the present invention kind of cmos device presents.
Figure 10 is shown as the structural representation that the manufacture method step 7) of of the present invention kind of cmos device presents.
Structural representation that cmos cell presents after the manufacture method step 7) that Figure 11 is shown as of the present invention kind of cmos device completes.
The element numbers explanation
101 Si substrates
102 SiO
2Layer
103 first grooves
104 second grooves
105 Ge layers
106 only carve layer
107 III-V family semiconductor layer
108 nmos devices
109 PMOS devices
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to Fig. 1 ~ Figure 11.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy in graphic only show with the present invention in relevant assembly but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
As shown in Fig. 1 ~ 11, the invention provides a kind of manufacture method of cmos device, described manufacture method comprises step at least:
As shown in Figure 1 and 2, at first carry out step 1), a Si substrate 101 is provided, and form the SiO with first thickness on described Si substrate 101
2Layer 102.Described SiO
2102 can prepare by thermal oxidation process by layer, also can be prepared by chemical vapour deposition technique etc.In the present embodiment, described SiO
2Layer 102 is prepared by thermal oxidation process.Described the first thickness can be selected according to different demands, and its thickness range is 10 ~ 9000nm.
As shown in Fig. 3 ~ 4, then carry out step 2), the described SiO of etching
2Layer 102 and Si substrate 101, form the first groove 103 that at least one reaches first degree of depth; And the described SiO of etching
2Layer 102 and Si substrate 101, form the second groove 104 that at least one reaches second degree of depth, and described second degree of depth is greater than described first degree of depth.
In the present embodiment, first make litho pattern, then to described SiO
2 Layer 102 and Si substrate 101 carry out etching, form the first groove 103 that at least one reaches first degree of depth; And then making litho pattern the described SiO of etching
2Layer 102 and Si substrate 101, form the second groove 104 that at least one reaches second degree of depth, and described second degree of depth is greater than described first degree of depth.Certainly, in other embodiments, also can first etch the groove that the degree of depth is larger, and then the less groove of etching depth.
As shown in Figure 5, then carry out step 3), in described the first groove 103 and the interior formation of the second groove 104 Ge layer 105, and make the upper surface of the upper surface of the Ge layer 105 in described the first groove 103 higher than described Si substrate 101, the upper surface of the Ge layer 105 in described the second groove 104 is lower than the upper surface of described Si substrate 101.
In the present embodiment, adopt the pure Ge of chemical vapour deposition technique deposition, due to pure Ge at SiO
2Layer is difficult to nucleating growth on 102, and can be on the Si surface can nucleating growth, thereby outer time delay, Ge optionally Si substrate 101 superficial growths in the first groove 103 and the second groove 104.Certainly, also can in deposition Ge, pass into appropriate HCl to reduce Ge at SiO
2Nucleation rate and the speed of growth on layer 102, select effect to reach better extension.
The upper surface of the Ge layer 105 in described the first groove 103 is higher than the upper surface of described Si substrate 101, and the upper surface of the Ge layer 105 in described the second groove 104 is lower than the upper surface of described Si substrate 101.As shown in Figure 5, the upper surface of the upper surface of the Ge layer 105 in described the first groove 103 and described Si substrate 101 have one on the occasion of difference in height h
1, and the upper surface of the Ge layer 105 in the upper surface of described Si substrate 101 and described the second groove 104 also have one on the occasion of difference in height h
2, wherein, h
1, h
2Concrete numerical value determine according to the actual requirements.
As shown in Figure 6, then carry out step 4), form and only carve layer 106 in described Ge layer 105 surface.In this enforcement, concentrate, adopt the selective epitaxial method to form the described layer 106 of only carving.
As shown in Figure 7, then carry out step 5), carve layer 106 a surface formation III-V family semiconductor layer 107 in described stopping, and make the upper surface of the upper surface of the interior III of described the second groove 104-V family semiconductor layer 107 higher than the Ge layer 105 in described the first groove 103.In the present embodiment, adopt the selective epitaxial method to form III-V family semiconductor layer 107 in described layer 106 surface of only carving.
The material of described III-V family semiconductor layer 107 is the combination in any of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb or above-mentioned material.In the present embodiment, the material of described III-V family semiconductor layer 107 is GaAs.The upper surface of the III in described the second groove 104-V family semiconductor layer 107 is higher than the upper surface of the Ge layer 105 in described the first groove 103, as shown in Figure 7, the upper surface of the Ge layer 105 in the upper surface of described III-V family semiconductor layer 107 and described the first groove 103 have one on the occasion of difference in height h
3.
It is described that only to carve layer 106 be Si
xGe
yC
zSn
(1-x-y-z)Layer, component are different from the III of SiGe layer 105, B or the P doping of the second III of described III-V family semiconductor layer 107-V family semiconductor layer 107, B or P doping-V family semiconductor layer 107.It is in the present embodiment, described that only to carve layer 106 be Si
0.6Ge
0.1C
0.2Sn
0.1Layer.
As shown in Fig. 8 ~ 9, then carry out step 6), the surface of the above-mentioned resulting structures of etching is until expose the Ge layer 105 in described the first groove 103, and makes described Ge layer 105, SiO
2The upper surface of layer 102 and III-V family semiconductor layer 107 is in same plane.
In the present embodiment, first adopt surface to interior the stopping of described the first groove 103 of the above-mentioned resulting structures of selective corrosion technology etching to carve layer 106, then continue etching until expose the Ge layer 105 in described the first groove 103, and make described Ge layer 105, SiO
2The surface of layer 102 and III-V family semiconductor layer 107 is in same plane.After above-mentioned steps completes, also comprise and adopt the chemical mechanical polishing method to described Ge layer 105, SiO
2Layer 102 and step that III-polishing is carried out on V family semiconductor layer 107 surfaces, so that described Ge layer 105, SiO
2The surfacing of layer 102 and III-V family semiconductor layer 107 is in order to the carrying out of subsequent technique.The present invention only need can obtain Ge layer 105 and III-V family semiconductor layer 107 raceway groove as device by selective corrosion and polishing, and technique is simple, can save widely fabrication cycle and the cost of manufacture of device.
As shown in Figure 10 ~ 11, finally carry out step 7), in described Ge layer 105 preparation PMOS device 109, prepare nmos device 108 in described III-V family semiconductor layer 107.
In the present embodiment, described step 7) comprises step at least:
7-1) described Ge layer 105 is carried out to the N-type conductive type ion and inject formation N trap, described III-V family semiconductor layer 107 is carried out to P-type conduction type Implantation and form the P trap;
7-2) in described Ge layer 105 surface and III-V family semiconductor layer 107 surfaces make the grid region structures; In the present embodiment, described grid region structure comprises the grid oxide layer that is incorporated into Ge layer 105 or III-V family semiconductor layer 107, is incorporated into the polysilicon gate of described grid oxide layer, and the protection sidewall structure that is made in described grid oxide layer and polysilicon gate sidewall.
7-3) described Ge layer 105 is carried out to P-type conduction type Implantation in structure both sides, described grid region, to form source region and the drain region of PMOS pipe; In the present embodiment, make mask plate and shelter from III-V family semiconductor layer 107 zones, then adopt self-registered technology to carry out P-type conduction type Implantation in structure both sides, described grid region, to form source region and the drain region of PMOS pipe to described Ge layer 105.
7-4) described III-V family semiconductor layer 107 is carried out to the injection of N-type conductive type ion with source region and drain region at the two-layer formation of described grid region structure NMOS pipe; In the present embodiment, make mask plate and shelter from Ge layer 105 zone, then adopt self-registered technology to carry out the injection of N-type conductive type ion in structure both sides, described grid region, to form source region and the drain region of NMOS pipe to described III-V family semiconductor layer 107.
7-5) prepare source electrode and the drain electrode of PMOS pipe and NMOS pipe, completed the making of described cmos device.
Refer to Figure 10 and Figure 11, the present invention also provides the cmos device of the manufacture method made of the above-mentioned cmos device of a kind of foundation, described cmos device is included at least the NMOS that III-V family semiconductor layer 107 is made and manages and manage at the PMOS of Ge layer 105 making, as shown in figure 10, its local structure of amplifying as shown in figure 11 for its structure.Because III-semi-conductive electron transfer rate of V family is higher, and the hole mobility of Ge is higher, the present invention manages at the PMOS that the NMOS that III-V family semiconductor layer 107 is made manages and makes at Ge layer 105, thereby cmos device of the present invention has operating rate faster.
In sum, cmos device of the present invention and preparation method thereof, in having SiO
2In layer 102 Si substrate 101, form respectively the first groove 103 of first degree of depth and be greater than the second groove 104 of second degree of depth of described first degree of depth, in described the first groove 103 and the second groove 104, interiorly form respectively Ge layer 105, only carve layer 106 and III-V family semiconductor layer 107, then adopt selective corrosion technology etching said structure to the interior Ge layer 105 of described the first groove 103, and make described Ge layer 105, SiO
2 Layer 102 and III-V family semiconductor layer 107 are in same plane, finally on described Ge layer 105, make PMOS device 109, on described III-V family semiconductor layer 107, make nmos device 108 to complete the making of described cmos device.The present invention only need delay outside by selective corrosion technique and glossing can obtain the substrate with Ge layer 105 and III-V family semiconductor layer 107 composite material raceway grooves, and technique is simple, is conducive to reduce costs; On this substrate, prepare cmos device, have higher operating rate, be conducive to improve the performance of device.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not be used to limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and know that usually the knowledgeable, not breaking away from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (8)
1. the manufacture method of a cmos device, is characterized in that, described manufacture method comprises step at least:
1) provide a Si substrate, and form the SiO with first thickness on described Si substrate
2Layer;
2) the described SiO of etching
2Layer and Si substrate, form the first groove that at least one reaches first degree of depth; And the described SiO of etching
2Layer and Si substrate, form the second groove that at least one reaches second degree of depth, and described second degree of depth is greater than described first degree of depth;
3) in described the first groove and the second groove, form the Ge layer, and make the upper surface of the upper surface of the Ge layer in described the first groove higher than described Si substrate, the upper surface of the Ge layer in described the second groove is lower than the upper surface of described Si substrate;
4) in described Ge layer surface, form and only carve layer;
5) in described stopping, carve a layer surface formation III-V family semiconductor layer, and make the upper surface of the upper surface of the interior III of described the second groove-V family semiconductor layer higher than the Ge layer in described the first groove;
6) surface of the above-mentioned resulting structures of etching is until expose the Ge layer in described the first groove, and makes Ge layer, SiO in described the first groove
2The upper surface of the III in layer and the second groove-V family semiconductor layer is in same plane;
7) the Ge layer in described the first groove prepares the PMOS device, and the III in described the second groove-V family semiconductor layer prepares nmos device.
2. the manufacture method of cmos device according to claim 1, is characterized in that: adopt the selective epitaxial technology to form described Ge layer, stop and carve layer and III-V family semiconductor layer.
3. the manufacture method of cmos device according to claim 1, it is characterized in that: the material of described III-V family semiconductor layer is the combination in any of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb or above-mentioned material.
4. the manufacture method of cmos device according to claim 3, is characterized in that: be Si described only quarter layer
xGe
yC
zSn
(1-x-y-z)Layer, component are different from the SiGe layer of the second III of described III-V family semiconductor layer-V family semiconductor layer, B or P doping or the III of B or P doping-V family semiconductor layer.
5. the manufacture method of cmos device according to claim 1, it is characterized in that: in described step 6), first adopt the surface of the above-mentioned resulting structures of selective corrosion technology etching to the interior layer at only quarter of described the first groove, then continue etching until expose the Ge layer in described the first groove, and make Ge layer, SiO in described the first groove
2The surface of the III in layer and the second groove-V family semiconductor layer is in same plane.
6. the manufacture method of cmos device according to claim 1 is characterized in that: described step 6) also comprises and adopts the chemical mechanical polishing method to Ge layer, SiO in described the first groove
2The step that III-V family semiconductor layer surface is carried out polishing in layer and the second groove.
7. the manufacture method of cmos device according to claim 1, it is characterized in that: described step 7) comprises step at least:
7-1) described Ge layer is carried out to the N-type conductive type ion and inject formation N trap, the III in described the second groove-V family semiconductor layer is carried out to P-type conduction type Implantation and form the P trap;
7-2) III in the surface of the Ge layer in described the first groove and the second groove-V family semiconductor layer surface is made the grid region structure;
7-3) the Ge layer in described the first groove is carried out to P-type conduction type Implantation in structure both sides, described grid region, to form source region and the drain region of PMOS pipe;
7-4) III in described the second groove-V family semiconductor layer is carried out to the injection of N-type conductive type ion in structure both sides, described grid region, to form source region and the drain region of NMOS pipe;
7-5) prepare source electrode and the drain electrode of PMOS pipe and NMOS pipe.
8. cmos device according to the manufacture method made of the described cmos device of claim 1～7 any one.
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| US9123569B1 (en) | 2014-03-06 | 2015-09-01 | International Business Machines Corporation | Complementary metal-oxide-semiconductor structure with III-V and silicon germanium transistors on insulator |
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