CN102598257A - 微电子封装及其制造方法 - Google Patents

微电子封装及其制造方法 Download PDF

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Publication number
CN102598257A
CN102598257A CN2010800506719A CN201080050671A CN102598257A CN 102598257 A CN102598257 A CN 102598257A CN 2010800506719 A CN2010800506719 A CN 2010800506719A CN 201080050671 A CN201080050671 A CN 201080050671A CN 102598257 A CN102598257 A CN 102598257A
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China
Prior art keywords
layer
welding disk
conductive
conductive welding
spacing
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CN102598257B (zh
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R·K·纳拉
J·A·梅斯
M·J·马努沙罗
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Intel Corp
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Intel Corp
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Abstract

微电子封装包括裸芯片(210)，裸芯片(210)附连有第一多个导电焊盘(211)。微电子封装还包括第一层(220)和第二层(130)。第一层具有电连接到第一多个导电焊盘之一的第一多个导电通孔(121)。第二层包括位于第二层的周边(135)周围的第二多个导电焊盘(131)和电连接到第一多个导电通孔之一和第二多个导电焊盘之一的多个导电迹线(132)。微电子封装也包括多个接合线(240)，其中每一个接合线都电连接到第二多个导电焊盘之一。

Description

微电子封装及其制造方法
技术领域
一般而言，本发明公开的实施例涉及微电子装置，并且更具体地说，涉及这种装置的封装方法和设计。
背景技术
计算机微处理器、芯片集和其它微电子装置经常被放在微电子封装内，以便提供以免损坏的保护、与计算机系统中其它组件的连接以及其它优点。对于诸如智能电话等多个市场部分中的应用，堆叠的微电子封装在今天是司空见惯的。在堆叠的(或其它)封装内，传统上用引线接合或用受控塌陷芯片连接(C4)凸块形成进行裸芯片(die)到衬底的连接。
附图说明
从对(结合图中的附图进行的)如下详细描述的阅读中，将更好地理解所公开的实施例，其中：
图1是根据本发明实施例的微电子封装的平面图；
图2是根据本发明实施例的图1的微电子封装的截面图；
图3是示出根据本发明实施例制造微电子封装的方法的流程图；
图4-9是根据本发明实施例图1和图2的微电子封装在其制造过程中各个具体点处的截面图；
图10描绘了根据本发明实施例的堆叠的裸芯片封装；
图11描绘了根据本发明实施例在附连到具有POP配置的基础封装(underlying package)的BBUL封装焊剂上包括堆叠的裸芯片的微电子封装；以及
图12描绘了根据本发明实施例在附连到具有PIP配置的基础封装的BBUL封装焊剂上包括堆叠的裸芯片的微电子封装。
为了示出的简化和清晰，附图示出了构造的一般方式，并省略了众所周知特征和技术的描述和细节，以避免不必要地模糊了对本发明描述的实施例的论述。此外，附图中的单元不一定按比例绘制。例如，附图中的一些单元的尺寸可能相对于其它单元放大了，以帮助改进对本发明实施例的理解。不同附图中相同附图标记表示相同单元，而类似的附图标记可能表示类似单元，但不一定表示类似单元。
说明书和权利要求书中的术语“第一”、“第二”、“第三”、“第四”等如果有的话则用于区分类似单元，并不一定用于描述具体顺序或时间上的次序。要理解，如此使用的术语在适当情境下可互换，使得本文描述的本发明实施例例如能够按不同于本文示出或以其它方式描述的顺序操作。类似地，如果一种方法在本文被描述为包括一系列步骤，则本文所呈现的这种步骤的次序不一定是可执行这种步骤的唯一次序，并且某些陈述的步骤有可能可被省略，和/或本文中未描述的某些其它步骤有可能可被加到方法中。而且，术语“包括”、“包含”、“具有”及其任何变形打算包含非排他性包含，使得包括单元列表的过程、方法、制品或设备不一定限于那些单元，而是可包含未明确列出的或是这种过程、方法、制品或设备固有的其它单元。
说明书和权利要求书中的术语“左”、“右”、“前”、“后”、“上面”、“下面”、“之上”、“之下”等如果有的话则用于描述性目的，并不一定用于描述永久的相对位置。要理解，如此使用的术语在适当情境下可互换，使得本文描述的本发明实施例例如能够在不同于本文示出或以其它方式描述的其它方位操作。本文所使用的术语“耦合”被定义为以电方式或非电方式直接地或间接地连接。本文描述为彼此“相邻”的对象在对于使用该短语的上下文是适当时可彼此物理接触，彼此紧密靠近，或在与彼此相同的总的地区或区域中。在本文中出现短语“在一个实施例中”不一定全都是指同一实施例。
具体实施方式
在本发明的一个实施例中，微电子封装包括附连有第一多个导电焊盘的裸芯片。这些焊盘具有不大于100微米的间距。微电子封装还包括第一层和位于第一层之上的第二层。第一层在其中具有第一多个导电通孔，其中每一个导电通孔都电连接到第一多个导电焊盘之一。第二层包括位于第二层的周边周围的第二多个导电焊盘，并且还包括多个导电迹线，其中每一个导电迹线都电连接到第一多个导电通孔之一和第二多个导电焊盘之一。微电子封装也包括多个接合线，其中每一个接合线都电连接到第二多个导电焊盘之一。
上文所提到的堆叠的封装在若干市场部分中是常见的。这种封装在未来将很可能变得更加广泛使用，这是因为计算机系统沿朝更大计算能力和更小大小的道路继续。然而，在这些更小封装中将使用的互连技术是必须解决的问题。虽然引线接合是非常牢固地建立的技术，但是其关键缺点之一是，它经常由于需要在裸芯片的周边周围设置焊盘以及可引线接合的焊盘行数量受限的事实而导致裸芯片大小的增大。这个缺点经常通过使用替代的C4技术得到解决，这是因为C4技术的特征在于产生更高数量接合处(bond)(例如以阵列图案分布)的能力。然而，C4技术由于凸块形成和组装工艺限制也面临间距缩放限制。
本发明的实施例通过使用所谓的无凸块增层(BBUL)技术来创建包封裸芯片的封装解决了这些问题。裸芯片内的间距尺寸被缩小以考虑裸芯片大小的减小。BBUL技术然后用于将裸芯片凸块“分布”在封装上的焊盘的周边行中。这些焊盘然后可在为了形成堆叠的封装而需要时引线接合到其它封装或其它硅裸芯片。例如，本发明的实施例使堆叠的封装中能够使用间距非常精细的裸芯片。如果期望的话，则这些焊盘中的一些可用于实现封装上封装(POP)和封装中封装(PIP)架构。
现在参考附图，图1是根据本发明实施例的微电子封装100的平面图，并且图2是其截面图。图2是沿图1的线2-2得到的，而图1示出了图2的由箭头1-1指示的层。图2中示出的接合线(在下文介绍和描述)从图1中省略了，以便增强图的清晰度。类似地，并且出于相同原因，图1中示出的导电迹线(在下文介绍和描述)从图2中省略了。
如图1和2中所示出的，微电子封装100包括附连有多个导电焊盘211的裸芯片210，多个导电焊盘211的间距212不超过100微米(本文也称为“百万分之一米”或“μm”)。(以更大间距，现有技术更有可能是充分的。)在示出的实施例中，裸芯片210至少部分地密封在模塑配混物250中。除了其它原因之外，这样做还为了提供在其上构建封装的其余部分的基座，并且也有助于翘曲控制、热耗散、机械强化等。此外，在示出的实施例中，微电子封装100是无凸块增层(BBUL)封装。BBUL技术取消了裸芯片附连工艺，并因此除了其它的之外还具有避免衬底翘曲问题并以非常精细的C4间距开发组装工艺的优点。
微电子封装100的层220含有多个导电通孔121，其中每一个导电通孔121都电连接到导电焊盘211之一。在示出的实施例中，导电通孔121在层220设置成10×10阵列。层220可由适当的晶圆介电材料组成。
微电子封装100还包括层130，层130位于层220之上并且其中形成有位于层130的周边135周围的多个导电焊盘131，并且其中还形成有多个导电迹线132，其中每一个导电迹线132都电连接到导电通孔121之一和导电焊盘131之一。层130可由光阻材料(诸如阻焊剂、干膜抗蚀剂等)组成。另外，微电子封装100包括多个接合线240，其中每一个接合线都电连接到导电焊盘131之一。
迹线132尽管显示为被限定到单层(层130)，但在其它实施例中可位于多层中。换句话说，可行的是，可使用多层对迹线布线，从通孔121延续到焊盘131(即C4到外部焊盘)。更具体地说，可使用由类似于所示那些层的层构成的层堆叠，以便将迹线从C4区域向外布线到更大间距焊盘(诸如焊盘131)。通孔可被直接加在通孔121上，通孔121然后可延伸通过层130，在此可对布线的第二层形成图案。作为示例，可直接在层130上对这个布线形成图案。一旦图案形成完成，就会在这个辅助布线层的上面对另一抗蚀层形成图案。可对于所需数量的层，重复这个过程。
在示出的实施例中，层130的周边135由层130的位于裸芯片210投射在层130上的占用面积(footprint)外部的部分构成。在图1中，那个占用面积一般由通过导电通孔121的10×10阵列形成的正方形表示。在一些实施例中，导电焊盘131设置在周边135内的多个同心环中。在示出的实施例中，示出了两个此类环。
如图中所示，导电焊盘131的间距112大于导电焊盘211的间距212。作为示例，间距112可近似为100μm。图案设计成将L0焊盘分布到将实现引线接合的L1焊盘的周边环。L1焊盘中的一些可以更大间距分布以实现POP(封装上封装)能力或PIP(封装中封装)能力。在那个方面，所示出的实施例包括具有间距112的第一组导电焊盘131和具有大于间距112的间距113的第二组(有可能在层130的角落处，如所示，但不一定位于那儿)导电焊盘131。模塑配混物250可以POP或类似架构，在其中含有将容纳POP焊剂凸块等的导电通孔。在图2中，这些导电通孔填充有POP焊剂凸块260，并且由此是不可见的。
图3是示出根据本发明实施例制造微电子封装的方法300的流程图。作为示例，方法300可引起类似于首先在图1中示出的微电子封装100的微电子封装的形成。
方法300的步骤310是要提供其上形成有导电焊盘的裸芯片。这里(并且在以下段落中的各个点)仅提到单个导电焊盘以便简化讨论；应该理解，裸芯片能够并且有可能会在其上形成有多个导电焊盘，并且所描述的单个焊盘是所有此类焊盘的代表。作为示例，裸芯片和导电焊盘可分别类似于图2中示出的裸芯片210和导电焊盘211。
在一个实施例中，方法300的前一步骤包括在将充当“重新分布的”BBUL晶圆的载体的安装板上配送适当的粘合剂，或步骤310还包括在将充当“重新分布的”BBUL晶圆的载体的安装板上配送适当的粘合剂，之后将单个的裸芯片放在粘合层上，其中有源侧向上。裸芯片可具有非常小的凸块(L0焊盘)，其中具有非常精细的凸块间距212。为了举一个示例，裸芯片可能以25μm间距具有15μm的凸块直径。
图4-9是根据本发明实施例微电子封装100在其制造过程中的各个具体点处的截面图。如图4所示出的，使用粘合剂420将裸芯片210安装在安装板410上。
方法300的步骤320将至少部分裸芯片密封在模塑配混物中，使得导电焊盘得以暴露。作为示例，该模塑配混物可类似于图2中示出的模塑配混物250。在一个实施例中，步骤320(或另一步骤)包括磨掉或者以其他方式移除部分的模塑配混物(最初被配送以完全覆盖裸芯片和焊盘)以便暴露导电焊盘。图5描绘了密封裸芯片210但暴露导电焊盘211的模塑配混物250。
方法300的步骤330是在导电焊盘之上配送(dispense)或以其他方式形成第一层。从而，在一个实施例中，步骤330包括形成介电层。作为示例，第一层可类似于图2中示出的层220。
方法300的步骤340是要在第一层中形成导电通孔，使得导电通孔连接到导电焊盘。作为示例，导电通孔可类似于图1中示出的导电通孔121。这些通孔将L0和L1彼此相连(并由此可称为L0-L1通孔)。图6描绘了模塑配混物250、裸芯片210和导电焊盘211之上的层220，并且还示出了导电通孔121已经在层220中在L0焊盘(即，导电焊盘211)上面向上开口(open up)。如上文所提到的，层220可由适当的晶圆介电材料构成。在一个实施例中，导电通孔121可具有5μm的直径，其中具有加或减5μm的校准。
图6中也描绘了已经旋涂(或以其它方式施加)在L0-L1电介质(即层220)上面并形成图案的干膜抗蚀剂或其它光阻材料610。图案用于使L0-L1通孔和这些通孔上面的L1焊盘向上开口(见图7)，以便在L1层(即层130)上布线。在示范性实施例中，可能以2/2μm L/S(线/间距，line/space)的尺寸形成L1布线(即迹线132-见图1)。如上所述，图案设计成将L0焊盘分布到将实现引线接合的L1焊盘的周边环。光阻材料610中的开口611随后将容纳L1焊盘之一。正如也已经描述的那样，可以更大间距分布其中一些L1焊盘以实现POP能力。图7描绘了制造过程中已经沉积或以其他方式施加了铜(或其它导电的)镀层(plating)以便形成上述图案的点。导电焊盘131(即L1焊盘)由此在层220上面是可见的。已经使用任何适当工艺移除了光阻材料610。
方法300的步骤350是要在第一层之上形成第二层，第二层在第二层的周边含有第二导电焊盘，其中第二导电焊盘电连接到导电通孔和第一导电焊盘。作为示例，第二层可类似于首先在图1中示出的层130。从而，在一个实施例中，步骤350包括形成光阻层。作为另一示例，第二层的周边可类似于也在图1中示出的周边135。从而，在一个实施例中，第二层的周边由第二层的位于裸芯片投射在第二层上的占用面积外部的部分构成。
在具体实施例中，第二导电焊盘是多个导电焊盘之一，并且步骤350包括将第二多个导电焊盘设置在第二层周边内的多个同心环中。在同一实施例中或另一实施例中，步骤350包括将第二多个导电焊盘设置成使得它们具有大于第一间距的第二间距。在一些实施例中，步骤350包括将第二多个导电焊盘设置成具有第二间距的第一组和具有第三间距的第二组，第三间距大于第二间距。
图8描绘了已经被配送并形成图案以形成开口810用于在随后步骤中形成的接合线的层130(例如由阻焊剂、干膜抗蚀剂等构成)。如果BBUL封装需要作为POP封装的一部分，则通孔是激光钻通模塑配混物(或以其他方式形成在模塑配混物中)的以便暴露L1POP焊盘。图9描绘了在移除(使用任何适当工艺)安装板410和粘合剂420之后并将通孔910形成在模塑配混物250中之后的微电子封装100。然后可镀上或以其他方式形成接合线和POP焊盘可能需要的任何表面抛光。
方法300的步骤360将接合线附连到第二导电焊盘。作为示例，接合线可类似于图2中示出的接合线240。如果期望的话，步骤360或另一步骤可包含用于POP封装的焊剂凸块形成。执行步骤360之后，微电子封装100可看起来如图1和2中所描绘的那样。
也可以创建除了上文描述的那些之外例如还包含有源侧向下的裸芯片放置、堆叠的裸芯片、PIP和其它封装架构的本发明的其它表现或实施例；这些中的一些在图10-12中示出了。图10描绘了根据本发明实施例的堆叠的裸芯片封装1000。图11描绘了根据本发明实施例在附连到具有POP配置的基础封装的BBUL封装焊剂上包括堆叠的裸芯片的微电子封装1100。图12描绘了根据本发明实施例在附连到具有PIP配置的基础封装的BBUL封装焊剂上包括堆叠的裸芯片的微电子封装1200。
尽管已经相对于特定实施例对本发明进行了描述，但本领域技术人员将理解，在不脱离本发明的精神或范围的情况下可进行各种改变。从而，本发明实施例的公开打算是本发明范围的说明，并不打算进行限制。意图是，本发明的范围应仅限于由所附权利要求书要求的程度。例如，对于本领域普通技术人员，将容易明白的是，本文论述的微电子封装以及相关结构和方法可实现在各种各样的实施例中，并且对这些实施例中的某些实施例的上述论述不一定表示所有可能实施例的完整描述。
此外，已经相对于特定实施例描述了益处、其它优点和问题的解决方案。然而，益处、优点、问题的解决方案以及可引起任何益处、优点或解决方案发生或变得更突显的任何要素都不视为任何或所有权利要求的关键的、所需的或必不可少的特征或要素。
而且，如果实施例和/或限制(1)未在权利要求书中明确要求权利，并且(2)在等效方案的教义下是或者可能是权利要求书中明确要素和/或限制的等效方案，则本文公开的实施例和限制在专用教义下不专用于公众。

Claims (20)

1.一种微电子封装，包括：
裸芯片，附连有第一多个导电焊盘，所述第一多个导电焊盘具有不超过100微米的第一间距；
第一层，其中形成有第一多个导电通孔，其中每一个导电通孔都电连接到所述第一多个导电焊盘之一；
第二层，位于所述第一层之上并且其中形成有位于所述第二层的周边周围的第二多个导电焊盘，并且其中还形成有多个导电迹线，其中每一个导电迹线都电连接到所述第一多个导电通孔之一和所述第二多个导电焊盘之一；以及
多个接合线，其中每一个接合线都电连接到所述第二多个导电焊盘之一。
2.如权利要求1所述的微电子封装，其中：
所述第二层的所述周边由所述第二层的位于所述裸芯片投射在所述第二层上的占用面积外部的部分构成。
3.如权利要求2所述的微电子封装，其中：
所述第二多个导电焊盘设置在多个同心环中。
4.如权利要求1所述的微电子封装，其中：
所述第一层由介电材料组成。
5.如权利要求1所述的微电子封装，其中：
所述第二层由光阻材料组成。
6.如权利要求1所述的微电子封装，其中：
所述第二多个导电焊盘具有大于所述第一间距的第二间距。
7.如权利要求6所述的微电子封装，其中：
所述第二多个导电焊盘中的第一组具有所述第二间距；以及
所述第二多个导电焊盘中的第二组具有大于第二间距的第三间距。
8.如权利要求1所述的微电子封装，其中：
所述微电子封装是无凸块增层封装。
9.一种无凸块增层封装，包括：
裸芯片，所述裸芯片至少部分地密封在模塑配混物中并附连有第一多个导电焊盘，所述第一多个导电焊盘具有不超过100微米的第一间距；
第一层，其中形成有第一多个导电通孔，其中每一个导电通孔都电连接到所述第一多个导电焊盘之一；
第二层，位于所述第一层之上并且其中形成有位于所述第二层的周边周围的第二多个导电焊盘，并且其中还形成有多个导电迹线，其中每一个导电迹线都电连接到所述第一多个导电通孔之一和所述第二多个导电焊盘之一；以及
多个接合线，其中每一个接合线都电连接到所述第二多个导电焊盘之一。
10.如权利要求9所述的无凸块增层封装，其中：
所述模塑配混物在其中含有第二多个导电通孔。
11.如权利要求9所述的无凸块增层封装，其中：
所述第二层的所述周边由所述第二层的位于所述裸芯片投射在所述第二层上的占用面积外部的部分构成。
12.如权利要求11所述的无凸块增层封装，其中：
所述第二多个导电焊盘设置在多个同心环中。
13.如权利要求9所述的无凸块增层封装，其中：
所述第一层由介电材料组成；以及
所述第二层由光阻材料组成。
14.如权利要求9所述的无凸块增层封装，其中：
所述第二多个导电焊盘具有大于所述第一间距的第二间距。
15.如权利要求14所述的无凸块增层封装，其中：
所述第二多个导电焊盘中的第一组具有所述第二间距；以及
所述第二多个导电焊盘中的第二组具有大于所述第二间距的第三间距。
16.一种制造微电子封装的方法，所述方法包括：
提供其上形成有第一导电焊盘的裸芯片；
将至少部分所述裸芯片密封在模塑配混物中，使得所述第一导电焊盘得以暴露；
在所述第一导电焊盘之上形成第一层；
在所述第一层中形成导电通孔，使得所述导电通孔连接到所述第一导电焊盘；
在所述第一层之上形成第二层，所述第二层在所述第二层的周边含有第二导电焊盘，其中所述第二导电焊盘电连接到所述导电通孔和所述第一导电焊盘；以及
将接合线附连到所述第二导电焊盘。
17.如权利要求16所述的方法，其中：
形成所述第一层包括形成介电层；以及
形成所述第二层包括形成光阻层。
18.如权利要求16所述的方法，其中：
所述第二层的所述周边由所述第二层的位于所述裸芯片投射在所述第二层上的占用面积外部的部分构成；
所述第一导电焊盘是第一多个导电焊盘之一；
所述第二导电焊盘是第二多个导电焊盘之一；以及
形成所述第二层包括将所述第二多个导电焊盘设置在所述第二层的所述周边内的多个同心环中。
19.如权利要求18所述的方法，其中：
所述第一多个导电焊盘具有第一间距；并且
形成所述第二层包括设置所述第二多个导电焊盘使得它们具有大于所述第一间距的第二间距。
20.如权利要求19所述的方法，其中：
形成所述第二层包括将所述第二多个导电焊盘设置成具有所述第二间距的第一组以及具有第三间距的第二组，所述第三间距大于所述第二间距。
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