CN102543920A - 芯片尺寸封装方法及封装结构 - Google Patents

芯片尺寸封装方法及封装结构 Download PDF

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CN102543920A
CN102543920A CN2010105992128A CN201010599212A CN102543920A CN 102543920 A CN102543920 A CN 102543920A CN 2010105992128 A CN2010105992128 A CN 2010105992128A CN 201010599212 A CN201010599212 A CN 201010599212A CN 102543920 A CN102543920 A CN 102543920A
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contact pad
point
area
salient point
semiconductor substrate
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CN102543920B (zh
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王津洲
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Semiconductor Manufacturing International Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

一种芯片尺寸封装方法及封装结构，其中芯片尺寸封装结构，包括：半导体衬底，所述半导体衬底上设置有接触焊盘，所述接触焊盘与半导体器件电连接；分别附着于各接触焊盘上的凸点；所述半导体衬底根据离中心点的不同距离分为若干区域，其中离中心点最近的区域内的接触焊盘及凸点尺寸最小，离中心点最远区域内的接触焊盘及凸点尺寸最大。本发明有效改善了芯片边缘凸点易脱落的情况；另外，避免了凸点间产生桥接而导致短路的现象。

Description

芯片尺寸封装方法及封装结构
技术领域
本发明涉及半导体器件的制造领域，尤其涉及芯片尺寸封装方法及封装结构。
背景技术
随着集成电路技术的不断发展，电子产品越来越向小型化、智能化、高性能以及高可靠性方向发展。而集成电路封装不仅直接影响着集成电路、电子模块乃至整机的性能，而且还制约着整个电子系统的小型化、低成本和可靠性。在集成电路晶片尺寸逐步缩小，集成度不断提高的情况下，电子工业对集成电路封装技术提出了越来越高的要求。
在集成电路晶片尺寸逐步缩小，集成度不断提高的情况下，电子工业对集成电路封装技术提出了越来越高的要求。因此，会使得集成电路制作微细化，造成芯片内包含的逻辑线路增加，而进一步使得芯片I/O(input/output)脚数增加，而为配合这些需求，产生了许多不同的封装方式，例如，球栅阵列封装(Ball grid array，BGA)、芯片尺寸封装(Chip Scale Package，CSP)、多芯片模块封装(Multi Chip Module package，MCM package)、倒装式封装(Flip ChipPackage)、卷带式封装(Tape Carrier Package，TCP)及晶片级封装(Wafer LevelPackage，WLP)等。
不论以何种形式的封装方法，大部分的封装方法都是将晶圆分离成独立的芯片后再完成封装的程序，即芯片尺寸封装(CSP)；芯片尺寸封装通过在芯片表面形成的焊球，使芯片翻转与底板形成连接，从而减小封装尺寸，满足电子产品的高性能(如高速、高频、更小的引脚)、小外形的要求，使产品具有很好的电学性能和传热性能。
凸点(bump)制作技术是芯片尺寸封装中的一个关键技术，通常CSP的失效大都是由于和凸点失效所引起，因此凸点可靠性问题是发展CSP技术需解决的关键问题。现有技术中的凸点是焊料通过一定工艺沉积在芯片金属垫层上，经过一定温度回流形成的金属焊球。申请号为200510025198.X的中国专利申请文件提供了一种凸点的形成方法。
随着半导体器件集成度越来越高，凸点与凸点之间的距离愈来愈小，在芯片的边缘区域，由于离中心点距离远，在周期性温度变化的状况下，所受应力远比离中心点距离较小处的应力要大，因此边缘处的凸点最容易脱落；而如果为了保持凸点的力学强度，则需要增大凸点的体积，而在有限的面积内，增加所有凸点的体积，会由于金属互熔的物理性质，凸点会变大横向扩展，可能造成凸点间发生桥接现象，进而导致短路的发生，影响半导体器件的电性能。
发明内容
本发明解决的问题是提供一种芯片尺寸封装方法及封装结构，防止凸点脱落或凸点间发生桥接现象。
为解决上述问题，本发明一种芯片尺寸封装结构，包括：半导体衬底，所述半导体衬底上设置有接触焊盘，所述接触焊盘与半导体器件电连接；分别附着于各接触焊盘上的凸点；所述半导体衬底根据离中心点的不同距离分为若干区域，其中离中心点最近的区域内的接触焊盘及凸点尺寸最小，离中心点最远区域内的接触焊盘及凸点尺寸最大。
本发明还提供一种芯片尺寸封装方法，包括下列步骤：提供半导体衬底，所述半导体衬底上形成有半导体器件，所述半导体衬底根据离中心点的不同距离分为若干区域；在所述半导体衬底上形成与半导体器件电连接的接触焊盘，所述接触焊盘之间具有间隔，所述离中心点最近的区域内的接触焊盘关键尺寸最小，离中心点最远区域内的接触焊盘关键尺寸最大；在接触焊盘上形成凸点，离中心点最近的区域内的凸点尺寸最小，离中心点最远区域内的凸点尺寸最大。
与现有技术相比，本发明具有以下优点：在半导体衬底上根据离中心点的距离不同，将芯片分为若干个区域，在离中心点最近的区域内形成接触焊盘关键尺寸及凸点的直径为最小，而随着离中心点距离不断的增大，接触焊盘关键尺寸及凸点的直径也相应增大。在芯片的边缘区域凸点的直径最大，使凸点与边缘接触焊盘的粘附力增强，有效改善了边缘凸点易脱落的情况。另外，半导体衬底的中心区域器件较为集中，而凸点直径为最小，因此凸点间不会产生桥接而导致短路的现象；在边缘区域，由于器件相对稀疏，凸点数量相应会减少，增加凸点的直径，不会产生桥接现象。
附图说明
图1是本发明形成芯片尺寸封装结构的具体实施方式流程图；
图2是本发明于芯片上进行区域划分的示意图；
图3至图4是本发明进行芯片尺寸封装的第一实施例示意图；
图5至图6是本发明进行芯片尺寸封装的第二实施例示意图。
具体实施方式
芯片尺寸封装技术作为集成电路封装技术之一，使得半导体器件的集成度更高、性能更好。CSP封装技术是通过在半导体衬底表面形成的凸点焊球，使芯片与引线框架形成连接，从而减小封装尺寸，满足电子产品的高性能(如高速、高频、更小的引脚)、小外形的要求，使产品具有很好的电学性能和传热性能。
然而发明人发现随着半导体器件集成度不断提高，凸点与凸点之间的距离愈来愈小，在芯片的边缘区域，由于离中心点距离远，在周期性温度变化的状况下，所受应力远比离中心点距离较小处的应力要大，因此边缘处的凸点最容易脱落；而如果为了保持凸点的力学强度，则需要增大凸点的体积，而在有限的面积内，增加所有凸点的体积，会由于金属互熔的物理性质，凸点会变大横向扩展，可能造成凸点间发生桥接现象，进而导致短路的发生，影响半导体器件的电性能。
发明人针对上述技术问题，发明人经过研究试验，发现在半导体衬底上根据离中心点的距离不同，将芯片分为若干个区域，在离中心点最近的区域内形成的凸点直径为最小，而随着离中心点距离不断的增大，凸点的直径也相应增大。在芯片的边缘区域凸点的直径最大，使凸点与边缘接触焊盘的粘附力增强，有效改善了边缘凸点易脱落的情况。另外，芯片的中心区域器件较为集中，而凸点直径为最小，因此凸点间不会产生桥接而导致短路的现象；在边缘区域，由于器件相对稀疏，凸点数量相应会减少，增加凸点的直径，不会产生桥接现象。
本发明形成芯片尺寸封装结构的方法如图1所示，具体流程如下：
步骤S11，提供半导体衬底，所述半导体衬底上形成有半导体器件，所述半导体衬底根据离中心点的不同距离分为若干区域。
本实施例中，半导体衬底的表面形成有半导体器件。
本实施例中，根据离中心点的距离先划分区域，作为第一实例，如图2所示，当芯片的尺寸为8mm时，以中心点10为圆心，半径为0mm～4mm的圆形作为第一区域100，所述第一区域100内器件密集度最高；继续以中心点10为圆心，半径在4mm～6mm的范围内的圆环作为第二区域102，在所述第二区域102内半导体器件的密集度较第一区域100变稀疏；将第二区域102以外至基板边缘的区域作为第三区域104，所述第三区域104离中心点的距离为6mm～8mm，作为边缘区域半导体器件密集度最低。
作为第二实例，当芯片的尺寸为16mm时，以中心点10为圆心，半径为0mm～8mm的圆形作为第一区域100，所述第一区域100内器件密集度最高；继续以中心点10为圆心，半径在8mm～12mm的范围内的圆环作为第二区域102，在所述第二区域102内半导体器件的密集度较第一区域100变稀疏；再以中心点10为圆心，半径在12mm～16mm的范围内的圆环作为第三区域104，在所述第三区域104内半导体器件的密集度较第二区域102变稀疏，作为边缘区域半导体器件密集度最低。
除上述两实例外，对芯片区域的划分主要根据器件密集度及芯片的面积来决定。
步骤S12，在所述半导体衬底上形成与半导体器件电连接的接触焊盘，所述接触焊盘之间具有间隔，所述离中心点最近的区域内的接触焊盘关键尺寸最小，离中心点最远区域内的接触焊盘关键尺寸最大。
在第一实例图2所示的芯片上，由于所述第一区域100内器件密集度高，相应焊盘的关键尺寸可以做到最小，为90μm～100μm，优选96μm；在所述第二区域102内半导体器件的密集度较第一区域100变稀疏，因此第二区域102内的接触焊盘关键尺寸相应增大，为110μm～115μm，优选112μm；第三区域104作为边缘区域，半导体器件密集度最低，并且由于边缘效应，凸点容易脱落，因此将所述第三区域104的接触焊盘关键尺寸增大至足够大且又能避免发生桥接，第三区域104的接触焊盘关键尺寸为125μm～130μm，优选128μm。
在第二实例图2所示的芯片上，当芯片的尺寸为16mm时，所述第一区域100内器件密集度高，相应接触焊盘关键尺寸为140μm～150μm，优选144μm；而位于第一区域100外围的环形第二区域102半导体器件的密集度较第一区域100变稀疏，因此第二区域102内的接触焊盘关键尺寸相应增大，为160μm～170μm，优选168μm；而在第二区域102外圈的环形第三区域104，作为边缘区域，半导体器件密集度最低，并且由于边缘效应，凸点容易脱落，因此将所述第三区域104的接触焊盘关键尺寸增大至足够大且又能避免发生桥接，第三区域104内的接触焊盘关键尺寸为190μm～195μm，优选192μm。
步骤S13，在接触焊盘上形成凸点，离中心点最近的区域内的凸点尺寸最小，离中心点最远区域内的凸点尺寸最大。
作为第一实例，如图2所示，当芯片的尺寸为8mm时，按半导体器件密集度的不同，将芯片以中心点10为圆心，向边缘递进分成了第一区域100、第二区域102和第三区域103；所述第一区域100、第二区域102和第三区域103内的接触焊盘大小也相应变化，而形成与接触焊盘上的凸点尺寸也会随之变化。其中，所述各区域内凸点的高度均一致，为92μm～108μm，优选为100μm；而凸点直径则不同，第一区域100内于焊盘上形成的凸点直径为120μm～125μm，优选123μm；第二区域102内的凸点直径为128μm～135μm，优选131μm；第三区域104内的凸点直径为138μm～145μm，优选141μm。
作为第二实例，如图2所示，当芯片的尺寸为16mm时，按半导体器件密集度的不同，将芯片以中心点10为圆心，向边缘递进分成了第一区域100、第二区域102和第三区域103；所述第一区域100、第二区域102、第三区域103内的接触焊盘大小也相应变化，而形成与接触焊盘上的凸点尺寸也会随之变化。其中，所述各区域内凸点的高度均一致，为140μm～160μm，优选为150μm；而凸点直径则不同，第一区域100内的凸点直径为180μm～190μm，优选185μm；第二区域102内的凸点直径为195μm～200μm，优选197μm；第三区域104内凸点直径为205μm～215μm，优选211μm。
基于上述实施例形成的芯片尺寸封装结构，包括：半导体衬底，所述半导体衬底上设置有接触焊盘，所述接触焊盘与半导体器件电连接；分别附着于各接触焊盘上的凸点；所述半导体衬底根据离中心点的不同距离分为若干区域，其中离中心点最近的区域内的接触焊盘及凸点尺寸最小，离中心点最远区域内的接触焊盘及凸点尺寸最大。
下面结合附图对本发明的具体实施方式做详细的说明。
图3至图4是本发明进行芯片尺寸封装的第一实施例示意图。如图3所示，提供芯片，所述芯片的半导体衬底300为带有半导体器件的半导体衬底，为了简化示图，此处仅以空白半导体衬底示意。根据半导体衬底300的大小及器件密集度的不同，以半导体衬底300中心点为圆心，向半导体衬底300边缘依次划分为第一区域I、第二区域II和第三区域III。在半导体衬底300上形成接触焊盘306a、306b、306c和钝化层302，所述接触焊盘306a、306b、306c之间由钝化层302间隔。
具体形成接触焊盘306a、306b、306c和钝化层302的工艺如下：首先在半导体衬底300上形成金属层，所述金属层的材料为铜或锡或铅或铜合金或铅锡合金等，所述金属层的厚度范围为18μm～35μm，所述金属层为采用物理气相沉积(PVD)方法制备，然后采用现有光刻技术图形化金属层，采用蚀刻技术刻蚀金属层，形成接触焊盘306a、306b、306c。其中，第一区域I内的接触焊盘306a的关键尺寸最小，第二区域II内的接触焊盘306b的关键尺寸比第一区域I内的接触焊盘306a的尺寸大，第三区域III内的接触焊盘306c的关键尺寸最大。
接着在半导体衬底300和接触焊盘306a、306b、306c上形成钝化层302，所述钝化层302可以为氧化硅、氮化硅或苯并环丁烯(BCB)、聚四氟乙烯、聚酰亚胺等高分子聚合物；然后采用化学机械研磨工艺平坦化所述钝化层302至露出接触焊盘306a、306b、306c表面，所述接触焊盘306a的面积最小，接触焊盘306b的面积大于接触焊盘306a，接触焊盘306c的面积最大。
参考图4，在接触焊盘306a、306b、306c分别形成凸点308a、308b、308c。其中，第一区域I内的凸点308a的直径最小，第二区域II内的凸点308b直径比第一区域I内的凸点308a大，第三区域III内的凸点308c最大。
本实施例中，所述凸点308a、308b、308c的材料为共溶锡铅合金、高铅锡铅合金，锡银合金或锡银铜合金。
形成凸点308a、308b、308c的方法可以是金属线焊接法(wire bonding)或印刷板方法。如果采用金属线焊接法的话，为了形成不同大小的凸点，在第一区域I的接触焊盘306a上打上一个含锡金属导线，而于第二区域II的接触焊盘306b上打上两个含锡金属导线，于第三区域III的接触焊盘306c上打上三个含锡金属导线，具体数量根据含锡金属导线的厚度、后续形成的凸点的大小及凸点间的间距决定。以直径为30微米的含锡金属导线为例，金属线焊接法形成含锡金属导线的直径约为60μm～75μm，高度为50μm～60μm。两个含锡金属导线的体积则增加一倍。三个含锡金属导线叠加，体积则变成三倍。
在含锡金属导线上涂布助焊剂；然后，将半导体衬底300放入回流炉内，对半导体衬底300上的含锡金属导线进行保温回流，形成高度一致，直径不同的凸点308a、308b、308c，其中凸点308a的直径最小，凸点308b的直径比308a大，而凸点308c的直径最大。
基于上述实施例形成的芯片尺寸封装结构，包括：半导体衬底300，所述半导体衬底300上形成有半导体器件，所述半导体衬底300根据大小及器件密集度的不同，以半导体衬底300中心点为圆心，向半导体衬底300边缘依次划分为第一区域I、第二区域II和第三区域III。钝化层302，位于半导体衬底300上。接触焊盘306a、306b、306c，位于半导体衬底300上，以钝化层302作为间隔，且与钝化层302表面齐平；接触焊盘306a、306b、306c与所与半导体器件电连接；其中接触焊盘306a位于第一区域I，面积最小；接触焊盘306b位于第二区域II，面积比第一区域I内的接触焊盘306a大；接触焊盘306c位于第三区域III，面积最大。凸点308a、308b、308c，分别附着于接触焊盘306a、306b、306c上，所述接触焊盘306a上的凸点308a直径最小，接触焊盘306c上的凸点308c直径最大，所述接触焊盘306b上的凸点308直径居中。
图5至图6是本发明进行芯片尺寸封装的第二实施例示意图。如图6所示，提供半导体衬底400，所述半导体衬底400上形成有半导体器件，根据半导体衬底400的大小及器件密集度的不同，以半导体衬底400中心点为圆心，向半导体衬底400边缘依次划分为第一区域I、第二区域II和第三区域III。在半导体衬底400上形成钝化层402和接触焊盘406a、406b、406c，所述接触焊盘406a、406b、406c镶嵌于钝化层402中，所述钝化层402中形成有开口，接触焊盘406a、406b、406c通过介电层402的开口暴露出来。
所述形成钝化层402和接触焊盘406a、406b、406c工艺为本领域技术人员公知技术，作为本发明的一个实施方式，首先在半导体衬底400上形成金属层，所述金属层为铜或锡或铅或铜合金或铅锡合金等，所述金属层为采用物理气相沉积(PVD)方法制备，然后采用现有光刻和蚀刻技术图形化金属层，形成接触焊盘406a、406b、406c。
接着，在半导体衬底400和接触焊盘406a、406b、406c上形成钝化层402，所述钝化层402可以为氧化硅、氮化硅或苯并环丁烯(BCB)、聚四氟乙烯、聚酰亚胺等高分子聚合物；然后采用现有的光刻和显影技术，在钝化层402上形成开口，所述开口暴露出接触焊盘406a、406b、406c，所述接触焊盘406a的面积最小，接触焊盘406b的面积大于接触焊盘406a，接触焊盘406c的面积最大。
参考图6，在接触焊盘406a、406b、406c分别形成凸点408a、408b、408c。其中，第一区域I内的凸点408a的直径最小，第二区域II内的凸点408b直径比第一区域I内的凸点408a大，第三区域III内的凸点408c最大。
所述形成凸点408a、408b、408c的方法同上述第一实施例，在此不再进行赘述。
本实施例中，所述凸点408a、408b、408c的材料为共溶锡铅合金、高铅锡铅合金，锡银合金或锡银铜合金。
基于上述实施例形成的芯片尺寸封装结构，包括：半导体衬底400，所述半导体衬底400上形成有半导体器件，所述半导体衬底400根据大小及器件密集度的不同，以半导体衬底400中心点为圆心，向半导体衬底400边缘依次划分为第一区域I、第二区域II和第三区域III。钝化层402，位于半导体衬底400的第二表面上。接触焊盘406a、406b、406c，镶嵌于钝化层402中，且通过钝化层402上的开口暴露出接触焊盘406a、406b、406c；接触焊盘406a、406b、406c与所述芯片通过半导体衬底400内的导电插塞电连接；其中接触焊盘406a位于第一区域I，面积最小；接触焊盘406b位于第二区域II，面积比第一区域I内的接触焊盘406a大；接触焊盘406c位于第三区域III，面积最大。凸点408a、408b、408c，分别附着于接触焊盘406a、406b、406c上，所述接触焊盘406a上的凸点408a直径最小，接触焊盘406c上的凸点408c直径最大，所述接触焊盘406b上的凸点408直径居中。
虽然本发明已以较佳实施例披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (15)

1.一种芯片尺寸封装结构，包括：
半导体衬底，所述半导体衬底上设置有接触焊盘，所述接触焊盘与半导体器件电连接；分别附着于各接触焊盘上的凸点；其特征在于，所述半导体衬底根据离中心点的不同距离分为若干区域，其中离中心点最近的区域内的接触焊盘及凸点尺寸最小，离中心点最远区域内的接触焊盘及凸点尺寸最大。
2.根据权利要求1所述芯片尺寸封装结构，其特征在于，所述各区域的凸点的高度一致，直径随着区域离中心点越远而越大。
3.根据权利要求2所述芯片尺寸封装结构，其特征在于，所述凸点的材料为共溶锡铅合金、高铅锡铅合金，锡银合金或锡银铜合金。
4.根据权利要求1所述芯片尺寸封装结构，其特征在于，芯片的尺寸为8mm时，所述离中心点的距离范围为0mm～4mm为第一区域，离中心点的距离为4mm～6mm为第二区域，离中心点的距离为6mm～8mm为第三区域。
5.根据权利要求1至4任一项所述芯片尺寸封装结构，其特征在于，所述凸点的高度为92μm～108μm。
6.根据权利要求5所述芯片尺寸封装结构，其特征在于，所述第一区域的接触焊盘关键尺寸为90μm～100μm，凸点直径为120μm～125μm；所述第二区域的接触焊盘关键尺寸为110μm～115μm，凸点直径为128μm～135μm；所述第三区域的接触焊盘关键尺寸为125μm～130μm，凸点直径为138μm～145μm。
7.根据权利要求1所述芯片尺寸封装结构，其特征在于，芯片的尺寸为16mm时，所述离中心点的距离范围为0mm～8mm为第一区域，离中心点的距离为8mm～12mm为第二区域，离中心点的距离为12mm～16mm为第三区域。
8.根据权利要求1或2所述芯片尺寸封装结构，其特征在于，所述凸点的高度为140μm～160μm。
9.根据权利要求8所述芯片尺寸封装结构，其特征在于，所述第一区域的接触焊盘关键尺寸为140μm～150μm，凸点直径为180μm～190μm；所述第二区域的接触焊盘关键尺寸为160μm～170μm，凸点直径为195μm～200μm；所述第三区域的接触焊盘关键尺寸为190μm～195μm，凸点直径为205μm～215μm。
10.根据权利要求1所述芯片尺寸封装结构，其特征在于，所述接触焊盘之间由钝化层隔离。
11.根据权利要求10所述芯片尺寸封装结构，其特征在于，所述接触焊盘材料为铜或锡或铅或铜合金或铅锡合金。
12.根据权利要求10所述芯片尺寸封装结构，其特征在于，所述钝化层材料为氧化硅或氮化硅或氮氧化物或苯并环丁烯或聚四氟乙烯。
13.一种形成权利要求1所述芯片尺寸封装结构的方法，其特征在于，包括下列步骤：
提供半导体衬底，所述半导体衬底上形成有半导体器件，所述半导体衬底根据离中心点的不同距离分为若干区域；
在所述半导体衬底上形成与半导体器件电连接的接触焊盘，所述接触焊盘之间具有间隔，所述离中心点最近的区域内的接触焊盘关键尺寸最小，离中心点最远区域内的接触焊盘关键尺寸最大；
在接触焊盘上形成凸点，离中心点最近的区域内的凸点尺寸最小，离中心点最远区域内的凸点尺寸最大。
14.根据权利要求13所述芯片尺寸封装方法，其特征在于，所述凸点的形成方法为金属线焊接法或印刷板方法。
15.根据权利要求13所述芯片尺寸封装方法，其特征在于，所述接触焊盘之间通过钝化层间隔。
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