CN102468246A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN102468246A
CN102468246A CN2011101399053A CN201110139905A CN102468246A CN 102468246 A CN102468246 A CN 102468246A CN 2011101399053 A CN2011101399053 A CN 2011101399053A CN 201110139905 A CN201110139905 A CN 201110139905A CN 102468246 A CN102468246 A CN 102468246A
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CN102468246B (zh
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陈宪伟
杨宗颖
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明一实施例提供一种半导体元件及其制作方法，该半导体元件包括一基板，具有一密封环区与一电路区；至少一角落凸块，配置于电路区中；一密封环结构，配置于密封环区中；以及一连接结构，电性连接密封环结构的一金属层与至少一角落凸块，至少一角落凸块耦接一信号接地。本发明有助于在使密封环结构接地时避免产生面积损失与额外的制作成本。

Description

半导体元件及其制作方法
技术领域
本发明涉及电子元件，尤其涉及半导体元件及其制作方法。
背景技术
在设计与封装半导体集成电路时，需要考虑几个方面。需避免湿气进入线路中，因为：(1)氧化物会捕捉(trap)湿气而导致氧化物的介电常数增加；(2)在互补式金属氧化物半导体晶体管中，湿气会在栅氧化物中产生被捕捉的电荷中心(trapped charge center)，而导致临界电压(thresholdvoltage)偏移；(3)湿气会在硅与栅氧化物的界面产生界面状态(interfacestate)而增加热电子敏感性，以致于晶体管的使用寿命缩短；(4)湿气会使金属内连线被腐蚀并降低集成电路的可靠度；以及(5)当湿气被捕捉于硅与氧化物的界面时，湿气会降低氧化物的机械强度，且氧化物会变得更容易因拉应力而破裂。离子污染物也可损害集成电路，因为离子污染物可在硅氧化物中快速扩散。举例来说，离子污染物会导致互补式金属氧化物半导体晶体管的临界电压不稳定并且改变在离子污染物附近的硅表面的表面电位(surface potential)。用以分离相邻的集成电路芯片的的切割工艺也可能对集成电路产生潜在的损害。
业界已使用密封环来保护集成电路免于受到湿气劣化、离子污染、以及切割工艺的影响，但仍需要再加以改进。特别是，若是密封环没有适当的接地，则密封环会导致信号干扰(signal interference)。再者，当将密封环接地时，必须考虑设计法则(design rule)与电路面积的问题。因此，急需半导体元件的制作方法的改良及其所制得的元件。
发明内容
为克服上述现有技术的缺陷，本发明一实施例提供一种半导体元件，包括一基板，具有一密封环区与一电路区；至少一角落凸块，配置于电路区中；一密封环结构，配置于密封环区中；以及一连接结构，电性连接密封环结构的一金属层与至少一角落凸块，至少一角落凸块耦接一信号接地。
本发明另一实施例提供一种半导体元件，包括一基板，具有一密封环区与一电路区；多个角落凸块，配置于一三角形角落凸块区中，三角形角落凸块区位于电路区的各角落；一密封环结构，配置于密封环区中；以及多个连接结构，各连接结构电性连接密封环结构的一金属层至一对应的角落凸块，各角落凸块耦接一信号接地。
本发明又一实施例提供一种半导体元件的制作方法，包括提供一基板，基板具有一密封环区与一电路区；提供至少一角落凸块于电路区的一三角形角落凸块区中；提供一密封环结构于密封环区中；电性连接密封环结构的一金属层至至少一角落凸块；以及电性连接至少一角落凸块至一信号接地。
本发明有助于在使密封环结构接地时避免产生面积损失与额外的制作成本。
附图说明
图1绘出本发明一实施例的一具有密封环结构的半导体元件的制作流程图，该密封环结构电性连接一角落凸块。
图2绘出本发明一实施例的一具有接地密封环结构的集成电路芯片的俯视图。
图3绘出图2的密封环沿I-I’线段的剖面图。
图4绘出本发明一实施例的一电性连接角落凸块的密封环结构的剖面图。
图5A至图5B绘出本发明多个实施例的集成电路芯片的各种不同的三角形角落凸块区的俯视图，且图5C绘出本发明一实施例的一角落凸块的示意图。
其中，附图标记说明如下：
100～制作方法；
102、104、106、108、110～步骤；
200～半导体元件；
201～密封环区；
202～集成电路芯片；
204～组件隔离区；
210～密封环结构；
212～导电层；
214～导孔层；
216～介电层；
220～元件部；
222～金属连接结构、连接结构；
224～角落凸块；
225～基座；
302～半导体基板、基板；
304～P型井；
306～中间层；
308～隔离结构；
308a、308b～浅沟槽隔离结构；
310～掺杂有源区；
312～接触条；
402～信号接地；
502a、502b～集成电路区；
524～角落凸块；
532、532a、532b～三角形角落凸块区。
具体实施方式
为使本发明的上述目的、特征和优点能更明显易懂，下文特举一优选实施例，并配合所附图式，作详细说明如下。
可以了解的是，下述内容提供许多不同的实施例，或是例子，以实施本发明的不同特征。为简洁起见，以下将以特定构件与排列举例说明。当然，在此仅用以作为范例，并非用以限定本发明。再者，当以下述及一第一元件形成于一第二元件之上或上时，可包括第一元件与第二元件是直接接触地形成的实施例、以及间隔有其他元件于第一元件与第二元件之间的实施例，如此则第一元件可不与第二元件直接接触。为简化与清楚说明起见，可以任意地以不同的尺寸绘出各种结构。
请参照图1，图1绘出本发明一实施例的一种制作一具有密封环结构的半导体元件的制作方法100的流程图，且密封环结构电性连接一角落凸块，以使密封环结构接地。图2绘出本发明一实施例的一元件200的俯视图，元件200包括一集成电路芯片202、一围绕集成电路芯片202的密封环结构210、以及一位于其间的组件隔离区(assembly isolation region)204。图3绘出本发明一实施例的密封环结构210的剖面图。图4绘出本发明一实施例的一电性连一角落凸块224的密封环结构210的剖面图。图5A与图5B绘出本发明多个实施例的集成电路芯片的不同的三角形角落凸块区532的俯视图，且图5C绘出本发明一实施例的一角落凸块524的示意图。
值得注意的是，为简化与清楚起见，相似的结构会标以相似的标号。更加值得注意的是，可以一互补式金属氧化物半导体工艺制作部分的半导体元件200。因此，可以了解的是，可以在图1的制作方法100进行之前、之时、与之后加入另外的工艺，且在此可以仅是简单描述一些其他的工艺。可以一后栅极工艺(gate last process)制作半导体元件200，后栅极工艺也可称为一多晶硅栅极置换工艺(replacement poly gate process，RPG)。在后栅极工艺中，可先在一用以形成密封环的区域与一用以形成电路的区域中形成一闲置栅极结构(dummy gate structure，例如由多晶硅构成)，之后，进行一标准的互补式金属氧化物半导体工艺直到沉积一层间介电层为止。之后，可移除位于电路区的闲置多晶硅栅极结构，并以一高介电常数的栅极介电结构/金属栅极结构取代之。
请参照图1，制作方法100的步骤102为提供一半导体基板，其具有一密封环区与一电路区。在一实施例中，密封环区围绕电路区，密封环区用以形成一密封环结构于其上，电路区至少用以形成一晶体管元件于其中。制作方法100的步骤104为在电路区上形成一角落凸块，步骤106为在密封环区上形成一密封环结构，且密封环结构围绕电路区。制作方法100的步骤108为使密封环结构的一金属层电性连接形成于电路区上的角落凸块，步骤110为使角落凸块电性连接一信号接地(signal ground)。由于密封环结构经由角落凸块接地，因此，可有助于在使密封环结构接地时避免产生面积损失(area penalty)与额外的制作成本。
请参照图2，集成电路芯片202包括多个角落凸块224，其借由多个金属连接结构222电性连接密封环结构210。图3绘出密封环区与组件隔离区沿着I-I’线段的剖面图。图4绘出在元件部220中，一角落凸块借由一金属连接结构电性连接密封环结构的剖面图。
请参照图2与图3，图3绘出以图1的制作方法100所制得的半导体元件200的一实施例的剖面图。半导体元件200可包括一半导体基板302，半导体基板302具有一密封环区201以及组件隔离区204，组件隔离区204围绕集成电路芯片202，半导体基板302例如为硅基板(例如p型掺杂基板)。在一实施例中，密封环区201围绕着电路区形成，密封环区用以形成一密封环结构于其上，电路区用以形成至少一晶体管元件于其中。基板302可包括硅锗(silicon germanium)、砷化镓(gallium arsenic)、或其他适合的半导体材料。基板302可还包括掺杂区，例如P型井(P-well)304、N型井、和/或掺杂有源区310，在本实施例中，掺杂有源区310为一P+型掺杂有源区。在一实施例中，掺杂有源区可配置于其他区域中，例如P+型掺杂有源区310至少部分或全部位于P型井304中。基板302可还包括其他结构，例如一内埋层(buried layer)、和/或一外延层。再者，基板302可为一绝缘层上半导体(semiconductor on insulator)，例如一绝缘层上硅(silicon on insulator，SOI)。在另一实施例中，半导体基板302可包括一掺杂的外延层、一梯度半导体层(gradient semiconductor layer)、和/或还包括一半导体层位于另一不同类型的半导体层上，例如一硅层位于一硅锗层上。在另一实施例中，一化合物半导体基板(compound semiconductor substrate)可包括一多层硅结构、或者是一硅基板可包括一多层化合物半导体结构。有源区可作为一N型金属氧化物半导体元件(例如n型场效应晶体管，nFET)或一P型金属氧化物半导体元件(例如p型场效应晶体管，pFET)。半导体基板302可还包括在工艺步骤之前或是在后续工艺步骤中形成的多层下层(underlying layer)、多个元件、多个接面(junction)、以及其他结构(未绘出)。
元件200还包括多个形成于基板302中的隔离结构308以隔离有源区310与基板302的其它区域，隔离结构308例如为浅沟槽隔离(shallow trenchisolation，STI)结构308a、308b、或是区域硅氧化结构(LOCOS feature)。在一实施例中，有源区310可作为一N型金属氧化物半导体元件(例如n型场效应晶体管)或一P型金属氧化物半导体元件(例如p型场效应晶体管)。
元件200还包括一中间层(interlayer)306配置于基板上，基板包括浅沟槽隔离结构308a、308b、以及有源区310。在一实施例中，可借由高深宽比工艺(high aspect ratio process，HARP)和/或一高密度等离子体浆(highdensity plasma，HDP)化学气相沉积工艺沉积中间层306。在一实施中，中间层306包括介电材料(其为氧化物)。
元件200还包括多个形成于中间层306中的接触条(contact bar)312，以电性连接有源区310以及随后形成的密封环结构210。值得注意的是，可在密封环区中形成其它层，以于密封环结构上形成各种结构，例如保护层(passivation layer)、氮化物层、以及聚酰亚胺层，其沉积方法包括化学气相沉积、旋涂技术(spin-on technique)、及其相似的沉积方法。
元件200可还包括位于基板302上的闲置栅极和/或栅极结构(未绘出)，其可由各种材料层构成，并借由在元件200的各种区域上进行各种蚀刻/图案化工艺而形成。在一实施例中，半导体元件200可包括一形成于基板上的闲置绝缘层(未绘出)。或者是，可在基板302上形成一绝缘层，其包括一界面层、一高介电常数的介电层和/或一阻挡层(barrier layer)，且绝缘层可留在最终的元件中。绝缘层可为一形成在基板302上的闲置介电层。在一实施例中，闲置介电层可包括氧化物，例如以热或化学氧化法形成的氧化物。半导体元件200可还包括一闲置层，其以适当的沉积工艺形成在基板上。在一实施例中，闲置栅极可包括多晶硅，且就本实施例的闲置多晶硅栅极而言，可使用硅烷(silane，SiH4)、乙硅烷(di-silane，Si2H6)、或二氯硅烷(di-clorosilane，SiCl2H2)作为化学气相沉积工艺中的化学气体，以形成多晶硅闲置层。之后，利用一般的微影、图案化与蚀刻技术来图案化与蚀刻闲置层，以形成多个闲置栅极(例如在密封环区和/或电路区上)。
在一实施例中，光致抗蚀剂层和/或硬掩模层(未绘出)可形成于基板302与闲置层(例如包括多晶硅)上。硬掩模层可包括氧化硅、氮化硅、氮氧化硅、碳化硅、和/或其它适合的介电材料，以及例如以化学气相沉积法或物理气相沉积法制得。再者，可利用一抗反射镀层或一底抗反射镀层(bottomantireflective coating，BARC，未绘出)来帮助微影工艺图案化一光致抗蚀剂层。举例来说，图案化光致抗蚀剂层可形成于硬掩模层上，硬掩模层包括栅极图案。然后，可利用栅极图案以干式蚀刻或是湿式蚀刻工艺来图案化硬掩模层。然后，可利用图案化的硬掩模以干式蚀刻法、湿式蚀刻法或前述的组合来形成栅极结构。因此，栅极结构可包括一绝缘层(未绘出)以及闲置栅极。图案化光致抗蚀剂层的形成方法包括光微影、浸润式微影(immersionlithography)、离子束写入(ion-beam writing)、或是其它适合的方法。举例来说，光微影工艺可包括旋转涂布、软烤、曝光、后烘烤(post-baking)、显影、清洗(rinsing)、烘干(drying)、以及其他适合的工艺。
或者是，在一反闲置工艺(reverse dummy process)中，在元件的某些区域中闲置栅极可包括介电栅极结构，而非多晶栅极结构与中间层306，然后，可以多晶硅取代介电质。
之后，可在中间层306(层间介电层或是多晶层)上进行化学机械研磨工艺，以使中间层306平坦化。在平坦化中间层306之后，可对元件200进行另外的工艺(例如互补式金属氧化物半导体工艺)以使元件200可还包括形成于密封环区201上的密封环结构210、高介电常数的栅极介电结构/金属栅极结构、以及各种其它结构，其中高介电常数的栅极介电结构/金属栅极结构于后栅极工艺或是多晶硅栅极置换工艺中移除位于电路区中的闲置多晶栅极结构之后位于电路区中。
在一实施例中，后栅极工艺或是多晶硅栅极置换工艺可包括于密封环区中形成一光致抗蚀剂层以保护密封环区中的闲置栅极，然后，以干式蚀刻法、湿式蚀刻法或前述的组合移除电路区中的闲置栅极，以形成多个沟槽。举例来说，湿式蚀刻工艺可包括暴露于含氢氧化物的溶液(例如氢氧化铵)、去离子水、和/或其它适合的蚀刻剂溶液(etchant solution)中。可在单一步骤的蚀刻工艺或是多个步骤的蚀刻工艺中移除位于电路区中的闲置多晶栅极(和/或闲置介电层)。举例来说，可利用一第一湿式蚀刻工艺移除闲置多晶栅极，以一第二湿式蚀刻工艺移除闲置介电层。第二湿式蚀刻工艺可包括暴露于一缓冲的氢氟酸溶液(buffered HF solution)或是一缓冲的氧化物蚀刻剂(buffered oxide etchant，BOE)中。可以了解的是，可使用其它的蚀刻化学药品选择性地移除闲置多晶栅极和/或闲置介电层。然后，形成一高介电常数栅极膜以及一金属栅极层以大体上填入电路区中的沟槽。高介电常数层可包括一界面层、一高介电常数介电层、和/或一阻挡层。再者，可沉积一填料金属(fill metal)以填入沟槽中。在一实施例中，可沉积一钛层以作为后续铝填充工艺的一润湿层(wetting layer)。可以物理气相沉积或是其它适合的工艺形成钛层。可形成一金属层(例如铝)以填入沟槽中。铝层的形成方法包括以化学气相沉积法形成一第一铝层，然后，以物理气相沉积法形成一第二铝层。或者是，填料金属可选择性地包括钨、铜、或其他适合的金属材料。接着，可在电路区中的金属栅极结构上进行一化学机械研磨工艺以移除多余的金属，化学机械研磨工艺可具有高度的选择性以于栅极结构上形成大体平坦的表面，并包括移除密封环区中的光致抗蚀剂层。
在一实施例中，密封环结构210可包括多种堆叠的导电层212与导孔层(via layer)214，其中导孔层214贯穿介电层216，密封环结构210的宽度约介于5微米与15微米之间。
可以了解的是，可对半导体元件200的电路区进行其它工艺以形成各种结构，例如接点(contact)/导孔(via)、内连线金属层(interconnect metal layer)、层间介电层、保护层等，以形成本领域所知的半导体电路。
请参照图2与图4，在一实施例中，密封环结构210可借由一连接结构222电性连接一角落凸块224。连接结构222可以其第一端电性连接密封环结构210的一金属层(例如一顶金属层)并以连接结构222的第二端电性连接角落凸块224(直接连接或经由一基座225)。在一实施例中，连接结构222可电性连接密封环结构210的一角落应力消除部(corner stress reliefportion)。在另一实施例中，连接结构222可包括一导电材料与一单层(singlelayer)，或者是连接结构222可包括各种导电材料和/或多个导电层。在一实施例中，连接结构222的材质可包括银、铅、锡、铜、其它金属、或前述的合金。角落凸块224可包括银焊料、铅锡、铜、或其他材料。在一实施例中，角落凸块224可包括多种截面形状，例如圆形、八角形、或六角形。角落凸块224用以电性连接一信号接地402，以使密封环结构210接地。除了连接信号接地以外，角落凸块224在电路中没有其他积极的用途。
请参照图5A至图5C，图5A与图5B绘出本发明多个实施例的集成电路芯片的不同的三角形角落凸块区532的俯视图，且图5C绘出本发明一实施例的一角落凸块524位于一三角形的角落凸块区532中的示意图。在一实施例中，一集成电路芯片可具有四个三角形角落凸块区532。在图5A中，一三角形角落凸块区532a包括一单一角落凸块524配置于一集成电路区502a中，其中密封环区201与组件隔离区204围绕集成电路区502a。在一实施例中，三角形角落凸块区532a为一等腰三角形，其具有相同的或是共通的边长1.7C，其中C为角落凸块524的直径(如图5C所示)。在图5B中，一三角形角落凸块区532b包括三个角落凸块524配置于集成电路区502b中，密封环区201与组件隔离区204围绕集成电路区502b。在本实施例中，三角形角落凸块区532b为一等腰三角形，其具有共通的边长(1.7C+P)，其中C为角落凸块524的直径，P为相邻的角落凸块524的中心的间距。依据整个集成电路区的面积大小，一角落凸块区可涵盖较多或较少的角落凸块，以电性连接密封环结构与电性接地。没有有源凸块(active bump)位于角落凸块区532中，换句话说，有源凸块被排除在角落凸块区532之外。
在一实施例中，下表1列出依据整个集成电路区的面积，位于一三角形角落凸块区中的一最小角落凸块数，角落凸块用以电性连接密封环结构以使密封环结构接地。如上述，C为角落凸块的直径，P为相邻的角落凸块的中心的间距。
表1
Figure BSA00000505611500091
请参照表1，当整个集成电路区面积小于或等于约100平方毫米时，三角形角落凸块区的共通边长为1.7C，且一单一角落凸块位于三角形角落凸块区中并电性连接密封环结构与接地。当整个集成电路区面积约介于100平方毫米与225平方毫米之间时，三角形角落凸块区的共通边长为1.7C至1.7C+P，且一至三个角落凸块位于三角形角落凸块区中并电性连接密封环结构与接地。当整个集成电路区面积大于约225平方毫米时，三角形角落凸块区的共通边长为1.7C+P，且多于三个的角落凸块位于三角形角落凸块区中并电性连接密封环结构与接地。
本说明书提供许多不同的实施例。本发明的多种形式之一是关于一半导体元件。半导体元件包括一基板，具有一密封环区与一电路区；至少一角落凸块，配置于电路区中；一密封环结构，配置于密封环区中；以及一连接结构，电性连接密封环结构的一金属层与至少一角落凸块，至少一角落凸块耦接一信号接地。
本发明是关于一半导体元件，包括一基板，具有一密封环区与一电路区；多个角落凸块，配置于一三角形角落凸块区中，三角形角落凸块区位于电路区的各角落；一密封环结构，配置于密封环区中；以及多个连接结构，各连接结构电性连接密封环结构的一金属层至一对应的角落凸块，各角落凸块耦接一信号接地。
本发明另关于一半导体元件的制作方法。半导体元件的制作方法包括提供一基板，基板具有一密封环区与一电路区；提供至少一角落凸块于电路区的一三角形角落凸块区中；提供一密封环结构于密封环区中；电性连接密封环结构的一金属层至至少一角落凸块；以及电性连接至少一角落凸块至一信号接地。
本发明虽以优选实施例揭示如上，然而其并非用以限定本发明的范围，任何本领域技术人员，在不脱离本发明的精神和范围内，当可做些许的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (10)

1.一种半导体元件，包括：
一基板，具有一密封环区与一电路区；
至少一角落凸块，配置于该电路区中；
一密封环结构，配置于该密封环区中；以及
一连接结构，电性连接该密封环结构的一金属层与该至少一角落凸块，该至少一角落凸块耦接一信号接地。
2.如权利要求1所述的半导体元件，其中该密封环结构包括一围绕该电路区的金属叠层。
3.如权利要求1所述的半导体元件，其中该至少一角落凸块位于该电路区的一三角形角落凸块区中，该三角形角落凸块区具有相同的边长1.7C，其中C为该至少一角落凸块的直径。
4.如权利要求1所述的半导体元件，其中该至少一角落凸块位于该电路区的一三角形角落凸块区中，该三角形角落凸块区具有相同的边长1.7C至1.7C+P，其中C为该至少一角落凸块的直径，P为相邻的角落凸块的中心的间距。
5.如权利要求1所述的半导体元件，还包括：
多个角落凸块，配置于该电路区中，其中各该角落凸块电性连接该密封环结构的该金属层。
6.如权利要求1所述的半导体元件，其中三个角落凸块配置于该电路区的一三角形角落凸块区中，该三角形角落凸块区具有相同的边长1.7C+P，其中C为该至少一角落凸块的直径，P为相邻的角落凸块的中心的间距。
7.如权利要求1所述的半导体元件，其中三个角落凸块各电性连接该密封环结构的该金属层，且该电路区的面积约大于225毫米平方。
8.一种半导体元件的制作方法，包括：
提供一基板，该基板具有一密封环区与一电路区；
提供至少一角落凸块于该电路区的一三角形角落凸块区中；
提供一密封环结构于该密封环区中；
电性连接该密封环结构的一金属层至该至少一角落凸块；以及
电性连接该至少一角落凸块至一信号接地。
9.如权利要求8所述的半导体元件的制作方法，还包括：
电性连接该密封环结构的该金属层至一单一角落凸块，该单一角落凸块位于该三角形角落凸块区中，其中该电路区的面积约小于或等于100毫米平方。
10.如权利要求8所述的半导体元件的制作方法，还包括：
电性连接该密封环结构的该金属层至至少一角落凸块，该至少一角落凸块位于该三角形角落凸块区中，其中该电路区的面积约介于100毫米平方与225毫米平方之间。
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