CN110391185B - 制作半导体元件的方法 - Google Patents

制作半导体元件的方法 Download PDF

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CN110391185B
CN110391185B CN201810341858.2A CN201810341858A CN110391185B CN 110391185 B CN110391185 B CN 110391185B CN 201810341858 A CN201810341858 A CN 201810341858A CN 110391185 B CN110391185 B CN 110391185B
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layer
silicon nitride
metal
silicon
forming
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CN110391185A (zh
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林佶民
陈意维
郑存闵
陈品宏
刘志建
邱钧杰
陈姿洁
蔡志杰
黄怡安
张凯钧
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种制作半导体元件的方法，其主要先形成一硅层于一基底上，然后形成一金属氮化硅层于硅层上，形成一应力层于金属氮化硅层上，进行一热处理制作工艺，去除该应力层，形成一导电层于金属氮化硅层上，再图案化导电层、金属氮化硅层以及硅层以形成一栅极结构。

Description

制作半导体元件的方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作动态随机存取存储器(Dynamic Random Access Memory, DRAM)元件的位线结构的方法。
背景技术
随着各种电子产品朝小型化发展的趋势，动态随机存取存储器(DRAM)单元的设计也必须符合高集成度及高密度的要求。对于一具备凹入式栅极结构的DRAM单元而言，由于其可以在相同的半导体基底内获得更长的载流子通道长度，以减少电容结构的漏电情形产生，因此在目前主流发展趋势下，其已逐渐取代仅具备平面栅极结构的DRAM单元。
一般来说，具备凹入式栅极结构的DRAM单元会包含一晶体管元件与一电荷贮存装置，以接收来自于位线及字符线的电压信号。然而，受限于制作工艺技术之故，现有具备凹入式栅极结构的DRAM单元仍存在有许多缺陷，还待进一步改良并有效提升相关存储器元件的效能及可靠度。
发明内容
本发明一实施例揭露一种制作半导体元件的方法，其主要先形成一硅层于一基底上，然后形成一金属氮化硅层于硅层上，形成一应力层于金属氮化硅层上，进行一热处理制作工艺，去除该应力层，形成一导电层于金属氮化硅层上，再图案化导电层、金属氮化硅层以及硅层以形成一栅极结构。
依据本发明一实施例，又包含进行该热处理制作工艺以形成一金属硅化物于硅层以及金属氮化硅层之间。
依据本发明一实施例，硅层包含非晶硅，应力层包含一拉伸应力层，应力层包含氮化硅，且应力层的拉伸应力大于2 GPa。
依据本发明一实施例，另包含于摄氏400度至700度之间形成该应力层。
依据本发明一实施例，另包含于摄氏800度至900度之间进行该热处理制作工艺。
依据本发明一实施例，金属氮化硅层包含氮化钛硅(TiSiN)，导电层包含钨，且栅极结构包含一栅极绝缘层于基底上。
附图说明
图1为本发明一实施例的动态随机存取存储器元件的上视图；
图2至图6为图1中沿着切线A-A’方向制作动态随机存取存储器元件的位线结构的方法示意图；
图7为本发明一实施例于周边区所制备的一半导体元件的结构示意图。
主要元件符号说明
10 动态随机存取存储器元件 12 位线结构
14 字符线 16 基底
18 主动区 20 存储单元区
22 栅极 24 浅沟绝缘
26 位线结构 28 位线结构
30 栅极绝缘层 32 硅层
34 金属氮化硅层 36 应力层
38 热处理制作工艺 40 金属硅化物
42 导电层 44 金属硅化物
46 栅极结构 48 遮盖层
50 栅极结构 52 源极/漏极区域
具体实施方式
请参照图1至图6，图1至图6为本发明一实施例制作一动态随机存取存储器元件的方法示意图，其中图1为本发明制作一动态随机存取存储器元件的上视图，图2至图6则显示图1中沿着切线AA’方向制作动态随机存取存储器元件的位线的方法示意图。本实施例是提供一存储器元件，例如是具备凹入式栅极的动态随机存取存储器元件10，其包含有至少一晶体管元件(图未示)以及至少一电容结构(图未示)，以作为DRAM阵列中的最小组成单元并接收来自于位线或位线结构12、26、28及字符线14的电压信号。
如图1所示，动态随机存取存储器元件10包含一基底16，例如一由硅所构成的半导体基底，然后于基底16内形成有至少一浅沟绝缘24，以于基底16上定义出多个主动区(active area, AA)18。此外，基底16上还定义有一存储单元区20以及一周边区(图未示)。其中，动态随机存取存储器元件10的多个字符线(word line, WL)14与多个位线(bitline, BL)结构12、26、28较佳形成于存储单元区20的基底16上而其他的主动元件等(未绘示)则可形成在周边区。需注意的是，为简化说明，本发明的图1仅绘示出位于存储单元区20的元件上视图并省略了位于周边区的元件。
在本实施例中，各主动区18例如是相互平行地朝向一第一方向延伸，而字符线14或多条栅极22是形成在基底16内并穿越各主动区18及浅沟绝缘24。具体来说，各栅极22是沿着不同于第一方向的一第二方向，例如Y方向延伸，且第二方向与第一方向相交并小于90度。
另一方面，位线结构12、26、28是相互平行地形成在基底16上沿着一第三方向，例如X方向延伸，并同样横跨各主动区18及浅沟绝缘24。其中，第三方向同样是不同于第一方向，并且较佳是与第二方向垂直。也就是说，第一方向、第二方向及第三方向彼此都不同，且第一方向与第二方向及第三方向都不垂直。此外，字符线14两侧的主动区18内较佳于后续制作工艺中形成接触插塞，例如包括位线接触插塞(bit line contact, BLC)(图未示)来电连接至各晶体管元件的源极/漏极区域(图未示)以及存储节点(storage node)接触插塞(图未示)来电连接一电容。
以下针对形成浅沟绝缘24以及字符线14(或又称埋入式字符线)后的制作进行说明。首先如图2所示，先形成一浅沟绝缘24于基底16内由此定义出主动区18并于部分浅沟绝缘24以及基底16内形成字符线(图未示)，然后形成一绝缘层或更具体而言一栅极绝缘层30于浅沟绝缘24以及基底16表面，其中栅极绝缘层30实际上仅于周边区作为栅极绝缘层但在此区域内严格来说较佳作为一掩模层。接着可利用图案化掩模(图未示)去除部分浅沟绝缘24间的栅极绝缘层30以及部分基底16形成凹槽(图未示)，再形成一半导体层或更具体而言一硅层32填入凹槽内并位于栅极绝缘层30表面上，其中接触基底16的部分硅层32较佳于后续图案化之后作为一位线接触。接着可选择性进行一预清洗制作工艺去除硅层上的不纯物，再进行一原子层沉积(atomic layer deposition, ALD)制作工艺以于硅层32表面形成一金属氮化硅层34。
在本实施例中，栅极绝缘层30较佳由氧化硅所构成的单层结构，但不局限于此，依据本发明其他实施例栅极绝缘层30又可依据制作工艺需求包含一多层结构，例如可细部包含一氧化硅层、一氮化硅层以及另一氧化硅层，此变化型也属本发明所涵盖的范围。另外设于栅极绝缘层30上的硅层32较佳包含非晶硅，而金属氮化硅层34则较佳包含氮化钛硅(TiSiN)，但均不局限于此。
如图3所示，接着进行一等离子体辅助化学气相沉积(plasma enhanced chemicalvapor deposition, PECVD)制作工艺以形成一应力层36于金属氮化硅层34表面。在本实施例中，形成应力层36的温度较佳介于摄氏400度至700度之间，此外应力层36较佳包含一拉伸应力层，且应力层36较佳由氮化硅所构成。
随后如图4所示，进行一热处理制作工艺38，利用介于摄氏800度至900度之间的高温对应力层36进行加热。值得注意的是，本实施例经由热处理制作工艺38对应力层36加热的同时较佳于硅层32以及金属氮化硅层34之间形成一金属硅化物40，其中金属硅化物40较佳包含硅化钛(titanium silicide)。在本实施例中，经由热处理制作工艺38的加热应力层36的拉伸应力可提升至大于2 GPa，而此拉伸应力的提升即可促使硅层32以及金属氮化硅层34之间金属硅化物40的形成更为顺利。
然后如图5所示，进行一蚀刻制作工艺完全去除应力层36并暴露出下面的金属氮化硅层34，随后再形成一导电层42以及一遮盖层48于金属氮化硅层34表面。在本实施例中，导电层42包含钨而遮盖层48较佳包含氮化硅，另外需注意的是，本实施例于形成导电层42时又可选择性搭配另一热处理制作工艺，利用高温同时于金属氮化硅层以及导电层42之间形成另一金属硅化物44，其中此金属硅化物44较佳包含硅化钨(tungsten silicide)。
接着如图6所示，图案化遮盖层48、导电层42、金属硅化物44、金属氮化硅层34、金属硅化物40、硅层32以及栅极绝缘层30以形成一栅极结构46于基底16上。更具体而言，本阶段所形成的栅极结构46较佳作为一动态随机存取存储器元件的位线结构12而接触基底16的部分硅层32则较佳作为一位线接触。之后可依据制作工艺需求于位线结构12两侧形成存储节点接触电连接源极/漏极区域以及后续所制作的电容。由于存储结点接触以及电容的制作均为本领域所熟知技术，在此不另加赘述。
请继续参照图7，图7为本发明一实施例的一半导体元件的结构示意图。如图7所示，本发明又可依据前述图2至图6制作工艺于存储单元区20形成位线结构12的同时于周边区形成另一栅极结构50于基底16上，其中栅极结构50较佳包含一硅层32设于基底16上、一栅极绝缘层30设于硅层32以及基底16之间、一金属氮化硅层34设于硅层32上、一金属硅化物40设于硅层32以及金属氮化硅层34之间、一导电层42设于金属氮化硅层34上、一金属硅化物44设于金属氮化硅层34以及导电层42之间以及一遮盖层48设于导电层42上。相较于图6所揭露的栅极结构46两侧为浅沟隔离24，本实施例于周边区所制作的栅极结构50两侧较佳包含一源极/漏极区域52设于基底16内，其中源极/漏极区域52可依据所制备的晶体管型态包含例如N型或P型掺质。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (10)

1.一种制作半导体元件的方法，其特征在于，包含：
形成一硅层于一基底上；
形成一金属氮化硅层于该硅层上；
形成一拉伸应力层于该金属氮化硅层上；
进行一热处理制作工艺，以形成一金属硅化物于该硅层以及该金属氮化硅层之间；
去除该拉伸应力层；
形成一导电层于该金属氮化硅层上；以及
图案化该导电层、该金属氮化硅层、该金属硅化物以及该硅层以形成一栅极结构。
2.如权利要求1所述的方法，还包含进行另一热处理制作工艺以形成另一金属硅化物于该金属氮化硅层以及该导电层之间。
3.如权利要求1所述的方法，其中该硅层包含非晶硅。
4.如权利要求1所述的方法，另包含于摄氏400度至700度之间形成该拉伸应力层。
5.如权利要求1所述的方法，其中该拉伸应力层包含氮化硅。
6.如权利要求1所述的方法，其中该拉伸应力层的拉伸应力大于2 GPa。
7.如权利要求1所述的方法，另包含于摄氏800度至900度之间进行该热处理制作工艺。
8.如权利要求1所述的方法，其中该金属氮化硅层包含氮化钛硅(TiSiN)。
9.如权利要求1所述的方法，其中该导电层包含钨。
10.如权利要求1所述的方法，其中该栅极结构包含栅极绝缘层，设于该基底上。
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