CN102437060A - 一种u型沟道的隧穿场效应晶体管的制造方法 - Google Patents
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Abstract
本发明属于半导体器件制造技术领域,具体为一种U型沟道的隧穿场效应晶体管的制造方法。U型沟道结构能够有效地延长晶体管的沟道长度,抑制晶体管中漏电流的产生,降低芯片功耗。本发明所提出的U型沟道的隧穿场效应晶体管的制造方法能够实现极窄的U型沟道,并克服由光刻引入的对准偏差,提高芯片的集成度。
Description
技术领域
本发明属于半导体器件制造技术领域,具体涉及一种隧穿场效应晶体管的制造方法,特别涉及一种U型沟道结构的隧穿场效应晶体管的制造方法。
背景技术
近年来,以硅集成电路为核心的微电子技术得到了迅速的发展,集成电路芯片的发展基本上遵循摩尔定律,即半导体芯片的集成度以每18个月翻一番的速度增长。可是随着半导体芯片集成度的不断增加,MOS晶体管的沟道长度也在不断的缩短,当MOS晶体管的沟道长度变得非常短时,短沟道效应会使半导体芯片性能劣化,甚至无法正常工作。
隧穿场效应晶体管是一种漏电流非常小的晶体管,可以进一步缩小电路的尺寸、降低电压,大大降低芯片的功耗。而采用U型沟道结构的隧穿场效应晶体管可以有效地延长晶体管的沟道长度,从而可以进一步抑制晶体管中漏电流的产生,因此,U型沟道结构的隧穿场效应晶体管得到了广泛的应用。传统的U型沟道隧穿场效应晶体管如图1所示,该隧穿晶体管10包括一个源区12、一个漏区13、一个衬底区11和一个由栅介质层14和栅极导电层15组成的栅叠层区。栅叠层区的边墙16是绝缘体如Si3N4材料,它将栅区导体层与所述器件的其它导体层绝缘。衬底11的杂质浓度为轻掺杂,源区12与漏区13为重掺杂且源区12的掺杂类型与漏区13的掺杂类型相反。绝缘层17是该器件的钝化层,它们将所述器件与其它器件隔开,并对所述器件保护不受外界环境的影响。导体层18是金属材料,作为该器件的电极。
目前,隧穿场效应晶体管的U型沟道结构通常是在提供的衬底上先形成一层氧化硅薄膜,然后在氧化硅薄膜上形成一层带有图形的光刻胶,然后再刻蚀氧化硅薄膜和半导体衬底形成器件的U型沟道。如上所述,在制造器件的U型沟道时,会形成一层带有图形的光刻胶,这样就会引入图形的对准失配(misalignment),从而使产品的制造良率降低,同时,目前窄U型沟道的制造也是一个难点。
发明内容
本发明的目的在于提出一种U型沟道的隧穿场效应晶体管的制造方法,在提高产品制造良率的同时还能够实现窄U型沟道的制造。
本发明提出了U型沟道隧穿晶体管的制造方法,具体包括如下步骤:
提供一个半导体衬底;
在所述半导体衬底内形成第一个具有第一种掺杂类型的掺杂区;
在所述半导体衬底上形成第一种绝缘薄膜;
刻蚀所述第一种绝缘薄膜与所述半导体衬底形成图形;
淀积形成第二种绝缘薄膜并刻蚀所述第二种绝缘薄膜形成侧墙;
在露出的衬底表面氧化形成第三种绝缘薄膜;
剥除所述的第二种绝缘薄膜;
沿着所述的第一种、第二种绝缘薄膜的边墙刻蚀衬底形成凹槽;
覆盖所述凹槽,形成第四种绝缘薄膜;
覆盖所述第四种绝缘薄膜,形成第一种导电薄膜;
刻蚀所述第一种导电薄膜形成器件的栅极导电层;
覆盖所述栅极导电层,形成栅极保护层;
刻蚀所述第四种、第三种绝缘薄膜露出衬底;
刻蚀露出的衬底形成用于后续生长材料的区域;
在所述半导体衬底内形成第二个具有第一种掺杂类型的掺杂区;
覆盖所述第二个具有第一种掺杂类型的掺杂区形成第五种绝缘薄膜;
覆盖所述第五种绝缘薄膜形成具有第二种掺杂类型的源区;
刻蚀所述栅极保护层形成栅极侧墙;
淀积第六种绝缘薄膜形成器件的钝化层并刻蚀所述钝化层形成接触孔;
淀积第二种导电薄膜并刻蚀所述第二种导电薄膜形成电极。
进一步地,所述的半导体衬底为硅或者为绝缘体上的硅(SOI)。所述的第一种、第三种、第六种绝缘薄膜为氧化硅。所述的第四种、第五种绝缘薄膜为氧化硅或者为HfO2等高介电常数材料。所述的第二种绝缘薄膜与栅极保护层由氮化硅材料形成。
所述的第一种导电薄膜为掺杂的多晶硅,其掺杂类型为n型掺杂或者为p型掺杂。所述的第二种导电薄膜为金属铝、金属钨或者为其它金属导电材料。
更进一步地,所述的第一种掺杂类型为n型,所述的第二种掺杂类型为p型;或者所述的第一种掺杂类型为p型,所述的第二种掺杂类型为n型。
U型沟道结构能够有效地延长晶体管的沟道长度,抑制晶体管中漏电流的产生,降低芯片功耗。本发明所提出的U型沟道的隧穿场效应晶体管的制造方法能够实现极窄的U型沟道,并克服由光刻引入的的对准偏差,提高芯片的集成度。
附图说明
图1为传统的的U型沟道结构的隧穿场效应晶体管的剖面图。
图2至图12为本发明所提出的U型沟道结构的隧穿场效应晶体管的制造方法的一个实施例的工艺流程图。
具体实施方式
下面将参照附图对本发明的示例性实施方式作详细说明。在图中,为了方便说明,放大了层和区域的厚度,所示大小并不代表实际尺寸。尽管这些图并不能完全准确地反映出实际的尺寸,它们还是完整的反映了区域和组成元件之间的相互位置,特别是组成元件之间的上下和相邻关系。
参考图是本发明的理想化实施例的示意图,本发明所示的实施例不应该被认为仅限于图中所示区域的特定形状,而是包括所得到的形状,比如制造引起的偏差。例如刻蚀得到的曲线通常具有弯曲或圆润的特点,但在本发明实施例中,均以矩形表示,图中的表示是示意性的,但这不应该被认为是限制本发明的范围。
首先,在提供的硅衬底201上淀积一层光刻胶301,然后掩膜、曝光、显影形成图形,再通过离子注入的方法在硅衬底201内形成n型掺杂区202,如图2所示,其中所示501表示粒子束。
剥除光刻胶301后,采用旋涂或者氧化的方法在硅衬底201上形成一层氧化硅薄膜203,接着在氧化硅薄膜203上形成一层带有图形的光刻胶302,然后刻蚀氧化硅薄膜203与硅衬底201形成图形,如图3所示。
剥除光刻胶302后,淀积一层氮化硅薄膜,并刻蚀氮化硅薄膜形成侧墙204,如图4所示。然后采用湿氧氧化的方法在露出的衬底表面氧化生长一层氧化硅薄膜205,如图5所示。
接下来,剥除氮化硅侧墙204,然后沿着氧化硅薄膜203、205的边墙刻蚀硅衬底201形成凹槽401,如图6所示。
凹槽401形成后,淀积一层高介电常数材料206,比如为HfO2,然后淀积一层掺杂的多晶硅薄膜207,其掺杂类型可以为n型也可以为p型,然后刻蚀多晶硅薄膜207形成器件的栅极导电层,如图7所示。
接下来,淀积一层氮化硅薄膜,并刻蚀氮化硅薄膜形成栅极保护层208,然后沿着氮化硅保护层的边墙刻蚀HfO2材料层206与氧化硅薄膜205露出衬底,并继续刻蚀衬底201形成图形,如图8所示。
接下来,采用倾斜的离子注入的方法在衬底201内形成n型掺杂区209,如图9所示,其中所示502为粒子束。
接下来,在n型掺杂区209之上形成一层绝缘薄膜210,绝缘薄膜210可以为氧化铝、氧化硅、或者为HfO2等高介电常数介质。然后在绝缘薄膜210上形成一层掺杂类型为p型的半导体层211,半导体层211比如为多晶硅,如图10所示。
接下来,刻蚀氮化硅保护层208形成栅极侧墙,并沿着栅极侧墙的边墙刻蚀掉露出的HfO2薄膜,如图11所示。
最后,淀积一层氧化硅薄膜212,并通过光刻、刻蚀的方法形成接触孔。接着再淀积一层金属,可以为铝,或为钨,然后刻蚀形成金属电极213。当器件处于开启状态时,器件中的电流将如线条600所示由源区211经绝缘层210、n型掺杂区209、衬底区201流向漏区202,如图12所示。
如上所述,在不偏离本发明精神和范围的情况下,还可以构成许多有很大差别的实施例。应当理解,除了如所附的权利要求所限定的,本发明不限于在说明书中所述的具体实例。
Claims (8)
1.一种U型沟道隧穿晶体管的制造方法,其特征在于具体步骤为:
提供一个半导体衬底;
在所述半导体衬底内形成第一个具有第一种掺杂类型的掺杂区;
在所述半导体衬底上形成第一种绝缘薄膜;
刻蚀所述第一种绝缘薄膜与所述半导体衬底形成图形;
淀积第二种绝缘薄膜并刻蚀所述第二种绝缘薄膜形成侧墙;
在露出的衬底表面氧化形成第三种绝缘薄膜;
剥除所述的第二种绝缘薄膜;
沿着所述的第一种、第二种绝缘薄膜的边墙刻蚀衬底形成凹槽;
覆盖所述凹槽形成第四种绝缘薄膜;
覆盖所述第四种绝缘薄膜形成第一种导电薄膜;
刻蚀所述第一种导电薄膜形成器件的栅极导电层;
覆盖所述栅极导电层形成栅极保护层;
刻蚀所述第四种、第三种绝缘薄膜露出衬底;
刻蚀露出的衬底形成用于后续生长材料的区域;
在所述半导体衬底内形成第二个具有第一种掺杂类型的掺杂区;
覆盖所述第二个具有第一种掺杂类型的掺杂区形成第五种绝缘薄膜;
覆盖所述第五种绝缘薄膜形成具有第二种掺杂类型的源区;
刻蚀所述栅极保护层形成栅极侧墙;
淀积第六种绝缘薄膜形成器件的钝化层;
刻蚀所述第六种绝缘薄膜形成接触孔;
淀积第二种导电薄膜并刻蚀所述第二种导电薄膜形成电极。
2.根据权利要求1所述的U型沟道隧穿晶体管的制造方法,其特征在于,所述的半导体衬底为硅或者为绝缘体上的硅。
3.根据权利要求1所述的U型沟道隧穿晶体管的制造方法,其特征在于,所述的第一种、第三种、第六种绝缘薄膜为氧化硅。
4.根据权利要求1所述的U型沟道隧穿晶体管的制造方法,其特征在于,所述的第四种、第五种绝缘薄膜为氧化硅或者为HfO2高介电常数材料。
5.根据权利要求1所述的U型沟道隧穿晶体管的制造方法,其特征在于,所述的第二种绝缘薄膜与栅极保护层由氮化硅材料形成。
6.根据权利要求1所述的U型沟道隧穿晶体管的制造方法,其特征在于,所述的第一种掺杂类型为n型,所述的第二种掺杂类型为p型;或者所述的第一种掺杂类型为p型,所述的第二种掺杂类型为n型。
7.根据权利要求1所述的U型沟道隧穿晶体管的制造方法,其特征在于,所述的第一种导电薄膜为掺杂的多晶硅,其掺杂类型为n型掺杂或者为p型掺杂。
8.根据权利要求1所述的U型沟道隧穿晶体管的制造方法,其特征在于,所述的第二种导电薄膜为金属铝或金属钨。
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CN104409486A (zh) * | 2014-12-08 | 2015-03-11 | 沈阳工业大学 | 低亚阈值摆幅高耐压绝缘栅隧穿晶体管及其制造方法 |
CN104465737A (zh) * | 2014-12-08 | 2015-03-25 | 沈阳工业大学 | 体硅双栅绝缘隧穿基极双极晶体管及其制造方法 |
CN105118779A (zh) * | 2015-07-22 | 2015-12-02 | 上海华力微电子有限公司 | 一种y型结构的半浮栅器件的制造方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104425388B (zh) * | 2013-09-06 | 2017-04-05 | 苏州东微半导体有限公司 | 一种半浮栅器件的制造方法及器件 |
CN104465736B (zh) * | 2014-12-08 | 2017-07-21 | 沈阳工业大学 | 内嵌折叠栅马鞍形绝缘隧穿增强晶体管及其制造方法 |
US9627378B2 (en) | 2015-06-30 | 2017-04-18 | International Business Machines Corporation | Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5386131A (en) * | 1991-09-13 | 1995-01-31 | Nec Corporation | Semiconductor memory device |
CN101118868A (zh) * | 2006-08-02 | 2008-02-06 | 力晶半导体股份有限公司 | 隔离结构的制造方法 |
WO2008022487A1 (fr) * | 2006-08-18 | 2008-02-28 | He Jian Technology(Suzhou)Co.Ltd. | Procédé permettant de fabriquer une isolation par tranchée peu profonde au moyen d'un masque à si3n4 autoaligné |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4932088B2 (ja) * | 2001-02-19 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型半導体装置の製造方法 |
JP2008166528A (ja) * | 2006-12-28 | 2008-07-17 | Spansion Llc | 半導体装置およびその製造方法 |
KR100843711B1 (ko) * | 2007-02-23 | 2008-07-04 | 삼성전자주식회사 | 리세스 채널 영역을 갖는 트랜지스터를 채택하는반도체소자 및 그 제조방법 |
TWI340458B (en) * | 2007-05-10 | 2011-04-11 | Nanya Technology Corp | Dram structure |
US8247296B2 (en) * | 2009-12-09 | 2012-08-21 | Semiconductor Components Industries, Llc | Method of forming an insulated gate field effect transistor device having a shield electrode structure |
US20120261744A1 (en) * | 2009-12-24 | 2012-10-18 | Fudan University | Microelectronic device structure and manufacturing method thereof |
US20130224919A1 (en) * | 2012-02-28 | 2013-08-29 | Yongping Ding | Method for making gate-oxide with step-graded thickness in trenched dmos device for reduced gate-to-drain capacitance |
US8778764B2 (en) * | 2012-07-16 | 2014-07-15 | Semiconductor Components Industries, Llc | Method of making an insulated gate semiconductor device having a shield electrode structure and structure therefor |
-
2011
- 2011-12-12 CN CN201110410865.1A patent/CN102437060B/zh not_active Expired - Fee Related
-
2012
- 2012-06-29 US US13/537,956 patent/US8748267B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5386131A (en) * | 1991-09-13 | 1995-01-31 | Nec Corporation | Semiconductor memory device |
CN101118868A (zh) * | 2006-08-02 | 2008-02-06 | 力晶半导体股份有限公司 | 隔离结构的制造方法 |
WO2008022487A1 (fr) * | 2006-08-18 | 2008-02-28 | He Jian Technology(Suzhou)Co.Ltd. | Procédé permettant de fabriquer une isolation par tranchée peu profonde au moyen d'un masque à si3n4 autoaligné |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104409486A (zh) * | 2014-12-08 | 2015-03-11 | 沈阳工业大学 | 低亚阈值摆幅高耐压绝缘栅隧穿晶体管及其制造方法 |
CN104465737A (zh) * | 2014-12-08 | 2015-03-25 | 沈阳工业大学 | 体硅双栅绝缘隧穿基极双极晶体管及其制造方法 |
CN104409486B (zh) * | 2014-12-08 | 2017-05-24 | 沈阳工业大学 | 低亚阈值摆幅高耐压绝缘栅隧穿晶体管及其制造方法 |
CN104465737B (zh) * | 2014-12-08 | 2017-07-21 | 沈阳工业大学 | 体硅双栅绝缘隧穿基极双极晶体管及其制造方法 |
CN105118779A (zh) * | 2015-07-22 | 2015-12-02 | 上海华力微电子有限公司 | 一种y型结构的半浮栅器件的制造方法 |
CN105118779B (zh) * | 2015-07-22 | 2018-05-11 | 上海华力集成电路制造有限公司 | 一种y型结构的半浮栅器件的制造方法 |
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