CN102403233B - 垂直沟道的隧穿晶体管的制造方法 - Google Patents
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Abstract
本发明属于半导体器件技术领域，具体涉及一种垂直沟道的隧穿晶体管的制造方法。围栅型的栅极结构增强了栅极的控制能力，窄禁带宽度材料的源极使得器件的驱动电流得到提升。采用本发明所提出的垂直沟道的型隧穿晶体管的制造方法，可以精确地控制沟道的长度，工艺过程简单，易于控制，降低了生产成本。
Description
技术领域
本发明属于半导体器件技术领域，具体涉及一种隧穿场效应晶体管的制造方法，特别涉及一种源极采用窄禁带宽度材料的垂直沟道的隧穿晶体管的制造方法。
背景技术
近年来，以硅集成电路为核心的微电子技术得到了迅速的发展，集成电路芯片的发展基本上遵循摩尔定律，即半导体芯片的集成度以每18个月翻一番的速度增长。可是随着半导体芯片集成度的不断增加，MOS晶体管的沟道长度也在不断的缩短，当MOS晶体管的沟道长度变得非常短时，短沟道效应会使半导体芯片性能劣化，甚至无法正常工作。
垂直沟道的隧穿晶体管是一种漏电流非常小的晶体管，可以进一步缩小电路的尺寸、降低电压，大大降低芯片的功耗。垂直沟道的隧穿晶体管的沟道长度通常由硅台刻蚀、离子注入或者外延工艺来决定，而不像传统的平面沟道的MOS晶体管那样是通过光刻来定义，因而无需借助复杂的光刻手段就可以很容易的实现短沟道器件的制作，其工艺和平面沟道的MOS晶体管技术也完全兼容。常见的硅台工艺中，通常是先采用刻蚀技术形成硅台，然后采用注入的方式形成沟道，由于注入的结深不容易控制，因而会使得沟道的长度也难以控制。
发明内容
本发明的目的在于提出一种垂直沟道的隧穿晶体管的制造方法，以便能够更好地控制器件的沟道长度。
本发明提出的垂直沟道的隧穿晶体管的制造方法，包括如下步骤：
提供一个半导体衬底；
在所述半导体衬底上形成第一种绝缘薄膜；
刻蚀所述第一种绝缘薄膜形成图形；
在所述半导体衬底内形成具有第一种掺杂类型的掺杂区；
刻蚀所述半导体衬底形成凹槽；
覆盖所述凹槽与第一种绝缘薄膜，形成第二种绝缘薄膜；
覆盖所述第二种绝缘薄膜，形成第一种导电薄膜；
刻蚀所述第一种导电薄膜、第二种绝缘薄膜形成器件的栅极结构；
在上述结构上淀积氮化硅薄膜，并刻蚀所述氮化硅薄膜形成栅极保护层；
沿着氮化硅薄膜的边墙刻蚀所述第一种绝缘薄膜露出衬底；
刻蚀露出的衬底形成用于后续生长材料的区域；
在上述结构上选择性生长窄禁带宽度材料；
通过离子注入对所述窄禁带宽度材料进行第二种掺杂类型的掺杂；
刻蚀所述氮化硅薄膜形成栅极侧墙；
淀积第三种绝缘薄膜形成器件的钝化层；
刻蚀所述第三种绝缘薄膜形成接触孔；
淀积第二种导电薄膜并刻蚀所述第二种导电薄膜形成电极。
进一步地，所述的半导体衬底为硅或者为绝缘体上的硅（SOI）。所述的第一种、第三种绝缘薄膜为氧化硅或者氮化硅。所述的第二种绝缘薄膜为氧化硅或者为HfO2等高介电常数材。
所述的第一种导电薄膜为掺杂的多晶硅，其掺杂类型为n型掺杂或者为p型掺杂。所述的第二种导电薄膜为金属铝、金属钨或者为其它金属导电材料。
所述的第一种掺杂类型为n型，所述的第二种掺杂类型为p型。
所述的窄禁带宽度材料为SiGe。
采用本发明所提出的垂直沟道的型隧穿晶体管的制造方法，可以精确地控制沟道的长度，工艺过程简单，易于控制，降低了生产成本。
附图说明
图1-11为本发明所提出的垂直沟道的隧穿晶体管的制造方法的一个实施例的工艺流程图。其中，图3、图5、图11分别为图2、图4、图10所示结构的A向视图。
具体实施方式
下面将参照附图对本发明的示例性实施方式作详细说明。在图中，为了方便说明，放大了层和区域的厚度，所示大小并不代表实际尺寸。尽管这些图并不能完全准确地反映出实际的尺寸，它们还是完整的反映了区域和组成元件之间的相互位置，特别是组成元件之间的上下和相邻关系。
参考图是本发明的理想化实施例的示意图，本发明所示的实施例不应该被认为仅限于图中所示区域的特定形状，而是包括所得到的形状，比如制造引起的偏差。例如刻蚀得到的曲线通常具有弯曲或圆润的特点，但在本发明实施例中，均以矩形表示，图中的表示是示意性的，但这不应该被认为是限制本发明的范围。同时在下面的描述中，所使用的术语晶片和衬底可以理解为包括正在工艺加工中的半导体晶片，可能包括在其上所制备的其它薄膜层。
首先，在提供的硅衬底201上采用旋涂或者氧化的方法生长一层二氧化硅薄膜202，接着在二氧化硅薄膜202上淀积一层光刻胶302，并掩膜、曝光、显影形成图形，然后刻蚀氧化硅薄膜202形成图形，并进行高能量的离子注入在衬底201内形成n型掺杂区203，如图1所示。
接下来，沿着二氧化硅薄膜202的边墙刻蚀硅衬底201形成凹槽，如图2所示。其中图3为图2所示结构剥除光刻胶后的A向视图。
剥除光刻胶301后，淀积一层高介电常数材料层204，比如为HfO2，然后继续淀积一层掺杂的多晶硅205，接着通过光刻、刻蚀工艺形成器件栅极结构，如图4所示，图5为图4所示结构的A向视图。
接下来，淀积一层氮化硅薄膜，并刻蚀氮化硅薄膜形成栅极保护层206，如图6所示。接着，沿着氮化硅保护层206的边墙刻蚀二氧化硅薄膜202露出衬底201，并继续刻蚀衬底201形成后续需要生长材料的区域。如7所示。
接下来，选择性地生长SiGe材料，并进行p型离子注入形成器件的源区207，如图8所示。然后刻蚀氮化硅保护层206形成栅极侧墙结构，如图9所示。
最后，淀积一层绝缘材料208，绝缘材料可以为氧化硅或者氮化硅。再淀积一层光刻胶，然后通过掩膜、曝光、刻蚀的方法形成通孔。接着再淀积一层金属，可以为铝，或为钨，然后刻蚀所淀积的金属形成器件的源极电极210、漏极电极211和栅极电极212，如图10所示，图11为图10所示结构的A向视图。
如上所述，在不偏离本发明精神和范围的情况下，还可以构成许多有很大差别的实施例。应当理解，除了如所附的权利要求所限定的，本发明不限于在说明书中所述的具体实例。
Claims (9)
1.一种垂直沟道的隧穿晶体管的制造方法，其特征在于具体步骤为：
提供一个半导体衬底；
在所述半导体衬底上形成第一种绝缘薄膜；
刻蚀所述第一种绝缘薄膜形成图形；
在所述半导体衬底内形成具有第一种掺杂类型的掺杂区；
刻蚀所述半导体衬底形成了从衬底表面到掺杂区的高度的凹槽；
覆盖所述凹槽与第一种绝缘薄膜，形成第二种绝缘薄膜；
覆盖所述第二种绝缘薄膜，形成第一种导电薄膜；
刻蚀所述第一种导电薄膜、第二种绝缘薄膜形成器件的栅极结构；
覆盖所述栅极结构形成栅极保护层；
刻蚀所述第一种绝缘薄膜露出衬底；
刻蚀露出的衬底形成用于后续生长材料的区域；
选择性生长窄禁带宽度材料；
通过离子注入对所述窄禁带宽度材料进行第二种掺杂类型的掺杂；
刻蚀所述栅极保护层形成栅极侧墙；
淀积第三种绝缘薄膜形成器件的钝化层；
刻蚀所述第三种绝缘薄膜形成接触孔；
淀积第二种导电薄膜；
刻蚀所述第二种导电薄膜形成电极。
2.根据权利要求1所述的隧穿晶体管的制造方法，其特征在于，所述的半导体衬底为硅或者为绝缘体上的硅。
3.根据权利要求1所述的隧穿晶体管的制造方法，其特征在于，所述的第一种、第三种绝缘薄膜为氧化硅或者氮化硅。
4.根据权利要求1所述的隧穿晶体管的制造方法，其特征在于，所述的第二种绝缘薄膜为氧化硅或者为HfO2高介电常数材料。
5.根据权利要求1所述的隧穿晶体管的制造方法，其特征在于，所述的栅极保护层由氮化硅材料形成。
6.根据权利要求1所述的隧穿晶体管的制造方法，其特征在于，所述的第一种掺杂类型为n型，所述的第二种掺杂类型为p型。
7.根据权利要求1所述的隧穿晶体管的制造方法，其特征在于，所述的第一种导电薄膜为掺杂的多晶硅，其掺杂类型为n型掺杂或者为p型掺杂。
8.根据权利要求1所述的隧穿晶体管的制造方法，其特征在于，所述的第二种导电薄膜为金属铝或金属钨。
9.根据权利要求1所述的隧穿晶体管的制造方法，其特征在于，所述的窄禁带宽度材料为SiGe。
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| KR100607785B1 (ko) * | 2004-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | 스플릿 게이트 플래시 이이피롬의 제조방법 |
| KR100699860B1 (ko) * | 2005-08-12 | 2007-03-27 | 삼성전자주식회사 | 웰 구조 형성 과정에서 정렬 키를 형성하는 방법 및 이를이용한 소자 분리 형성 방법 |
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2011
- 2011-12-12 CN CN201110410898.6A patent/CN102403233B/zh not_active Expired - Fee Related
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2012
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| CN1357926A (zh) * | 2000-12-12 | 2002-07-10 | 国际商业机器公司 | 横向多晶硅pin二极管及其制造方法 |
| US7465978B2 (en) * | 2003-09-23 | 2008-12-16 | Samsung Electronics Co., Ltd. | Field effect transistor with a high breakdown voltage and method of manufacturing the same |
| US7812370B2 (en) * | 2007-07-25 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling |
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| CN102403233A (zh) | 2012-04-04 |
| US20130149848A1 (en) | 2013-06-13 |
| US8586432B2 (en) | 2013-11-19 |
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