CN102437052B - 形成硅化物的方法 - Google Patents

形成硅化物的方法 Download PDF

Info

Publication number
CN102437052B
CN102437052B CN2011103667583A CN201110366758A CN102437052B CN 102437052 B CN102437052 B CN 102437052B CN 2011103667583 A CN2011103667583 A CN 2011103667583A CN 201110366758 A CN201110366758 A CN 201110366758A CN 102437052 B CN102437052 B CN 102437052B
Authority
CN
China
Prior art keywords
silicide
dielectric layer
opening
zone
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2011103667583A
Other languages
English (en)
Other versions
CN102437052A (zh
Inventor
肖胜安
遇寒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CN2011103667583A priority Critical patent/CN102437052B/zh
Publication of CN102437052A publication Critical patent/CN102437052A/zh
Priority to US13/678,752 priority patent/US20130130486A1/en
Application granted granted Critical
Publication of CN102437052B publication Critical patent/CN102437052B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66659Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/4175Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H01L29/66507Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种形成硅化物的方法,包括如下步骤:第1步,在硅片上淀积一层介质层;第2步,采用光刻和刻蚀工艺在所述介质层上将需要形成硅化物的区域暴露出来;当需要形成硅化物的区域低于所述介质层时,在所述介质层上刻蚀出开口,每个开口底部为需要形成硅化物的区域;当需要形成硅化物的区域高于所述介质层时,刻蚀所述介质层以使需要形成硅化物的区域的上表面凸出于所述介质层之上;第3步,淀积金属并进行高温退火,从而在介质层的每个开口中和凸出部位上形成硅化物;第4步,去除未形成硅化物的金属。本发明可用于在同一硅片上一次性地形成不同厚度的硅化物。

Description

形成硅化物的方法
技术领域
本发明涉及一种半导体集成电路领域制造硅化物的方法。
背景技术
难熔金属与硅在一起发生反应,熔合时形成金属硅化物(silicide)。如果难熔金属和多晶硅反应,那么它被称为多晶硅化物(polycide)。金属硅化物和多晶硅化物统称为硅化物。硅化物是一种具有热稳定性的金属化合物,并且具有低的电阻率。常见的用于形成硅化物的难熔金属包括钴(Co)、钼(Mo)、铂(Pt)、钽(Ta)、钛(Ti)、钨(W)、镍(Ni)等。
硅化物工艺用于源漏区和栅极时,通常用于获得低电阻;用于接触孔电极(例如钨塞)时,通常用于取得良好的欧姆接触以及低电阻。在硅化物形成过程中,需要消耗相应区域的硅或多晶硅。形成的硅化物越厚,硅或多晶硅的消耗量越大,但相应区域的方块电阻也就越小。
目前在同一硅片上、尤其是同一芯片中,各区域所形成的硅化物的厚度是一致的。以MOS晶体管为例,多晶硅栅极需要很低的多晶栅电阻,例如低于2欧姆/方块,这就需要在多晶硅栅极的上方形成厚度将近
Figure GDA00003047343700011
的多晶硅化物。而源极、漏极也会形成有相应厚度的金属硅化物,这会造成源漏区中的硅消耗太多,并导致器件源漏区的漏电。事实上源漏区的金属硅化物并不需要这么大的厚度,如果能在多晶硅栅极上形成较厚的多晶硅化物,同时在源漏区形成较薄的金属硅化物,就能满足两方面的要求。
再如,在集成有高压和低压两种器件的硅片中,高压器件可以采用比低压器件更深的源漏结,这样就可以在高压器件的源漏区形成相对厚的金属硅化物,得到更低的方块电阻,而不引起额外的漏电。因此在硅片上不同区域形成不同厚度的硅化物有着实际的需要。
目前在同一硅片上形成不同厚度的硅化物的方法是,在硅片上需要不同厚度的硅化物的区域分多次淀积金属并高温退火,每次在硅片的某一个或多个区域形成一种厚度的硅化物。但这样会造成制造时间长、工艺成本高的缺点。
发明内容
本发明所要解决的技术问题是提供一种形成硅化物的方法,该方法可以在同一硅片上一次性地形成不同厚度的硅化物。
为解决上述技术问题,本发明形成硅化物的方法包括如下步骤:
第1步,在硅片上淀积一层介质层;
第2步,采用光刻和刻蚀工艺在所述介质层将需要形成硅化物的区域暴露出来;
当需要形成硅化物的区域低于所述介质层时,在所述介质层上刻蚀出开口,每个开口底部为需要形成硅化物的区域;
当需要形成硅化物的区域高于除该需要形成硅化物的区域以外区域的所述介质层时,刻蚀该需要形成硅化物的区域上方的介质层以使该需要形成硅化物的区域的上表面凸出于所述介质层之上;
第3步,淀积金属并进行高温退火,从而在介质层的每个开口中、和凸出于介质层之上的需要形成硅化物的区域的上表面形成硅化物;
开口的宽高比或宽度越大,在该开口中形成的硅化物就越厚;反之亦然;
第4步,去除未形成硅化物的金属。
进一步地,所述方法第2步所形成的最大宽高比的开口的宽高比是最小宽高比的开口的宽高比两倍以上。
本发明形成硅化物的方法,主要利用金属淀积对不同宽高比的开口(通孔或沟槽)在底部有不同厚度的原理,在这些不同宽高比的开口底部形成不同厚度的硅化物。同时对于特定金属如钛、钴等,当其在小于特定宽度如的开口底部形成硅化物时,硅化物的厚度明显更薄,这进一步增加了硅化物厚度的可调整性。
附图说明
图1a~图1f是本发明的第一实施例的各步骤示意图;
图2a~图2d是本发明的第二实施例的各步骤示意图;
图3a~图3f是本发明的第三实施例的各步骤示意图;
图4是应用了本发明所述方法的射频LDMOS器件的示意图。
图中附图标记说明:
1为衬底;2为介质层;3为光刻胶;4为金属层;5为硅化物;6为栅氧化层;7为多晶硅栅极;8为BARC层;9为金属电极。
具体实施方式
图1a~图1f展示了本发明的第一实施例。
第1步,请参阅图1a,在半导体衬底(通常为硅衬底)1上淀积一层介质2,介质2例如为氧化硅,厚度为0.5~1μm。
第2步,请参阅图1b,在介质层2上旋涂光刻胶3,采用光刻工艺在需要形成硅化物的区域去除光刻胶3。假设需要在A1区域形成较厚的硅化物,在A2和A3区域形成较薄的硅化物。则光刻胶3所形成的光刻图形为:在A1区域曝光、显影形成较宽的开口,如开口宽度≥0.5μm;在A2和A3区域曝光、显影形成较窄的开口,如开口宽度≤0.2μm。所述开口可以是通孔或沟槽,开口贯穿光刻胶3,即开口底部为介质层2的上表面。
第3步,请参阅图1c,根据光刻图形对介质层2进行刻蚀,刻蚀终点为衬底1的上表面。
第4步,请参阅图1d,去除光刻胶3,此时介质层2的图形为:在A1区域具有一个宽度为s1的开口;在A2区域具有多个宽度为s2的开口,这些开口之间的间距为L2;在A3区域具有一个宽度为s3的开口。这些开口可以是通孔或沟槽,开口贯穿介质层2,即开口底部为衬底1的上表面。
第5步,请参阅图1e,在整个硅片淀积一层金属4,例如采用溅射工艺,金属4优选为钛(Ti)。金属4淀积在介质层2的上表面、以及介质层2的各个开口中的衬底1的上表面。
当介质层2上的金属层4的厚度为时,假设
Figure GDA00003047343700042
则A1区域宽度为s1的开口中的金属层4的厚度为
Figure GDA00003047343700043
假设
Figure GDA00003047343700044
则A2、A3区域宽度为s2、s3的开口中的金属层4的厚度
第6步,请参阅图1f,采用高温退火使金属层4与硅衬底1接触的区域形成金属硅化物5,例如采用快速热退火(RTA)工艺,这样便在介质层2的各个开口中形成了硅化物5。再将介质层2之上的金属4和没有形成金属硅化物5的金属4去除掉,例如采用湿法腐蚀工艺。
当A1区域的宽度为s1的开口中的金属层4的厚度为
Figure GDA00003047343700051
时,此时形成厚度约为
Figure GDA00003047343700052
的金属硅化物5。当A2、A3区域的宽度为s2、s3的开口中的金属层4的厚度为
Figure GDA00003047343700053
时,此时形成厚度
Figure GDA00003047343700054
的金属硅化物5。
所述方法第6步中,当s2或s3<0.2μm,则A2、A3区域的开口中所形成的金属硅化物5的厚度会更进一步的减小。例如s2=s3=0.15μm,则A2、A3区域的宽度为s2、s3的开口中的金属硅化物5的厚度将
Figure GDA00003047343700055
上述第一实施例在同一硅片上一次性地形成了不同厚度的硅化物,这主要是利用金属淀积对不同宽高比的开口(通孔或沟槽)图形在底部有不同覆盖率的原理,在不同宽高比的开口底部获得不同厚度的金属,并最终获得不同厚度的硅化物。
总体而言,当硅材料上方的介质层的开口的宽高比越大,则所淀积的金属就越厚,最终形成的硅化物也越厚。当硅材料上方的介质层的开口的宽高比越小,则所淀积的金属就越薄,最终形成的硅化物也越薄。
上述第一实施例中,介质层2的各个开口具有相同的高度(深度),这样各个开口的宽高比实际上就成为宽度之比。优选地,最大开口的宽度在最小开口的宽度的两倍以上。
有些金属在与硅反应形成金属硅化物的过程中,硅化物的厚度不仅与金属的厚度有关,还与开口的宽度有关。例如在上述第一实施例中,当金属层4为钛,且介质层2上有一个开口的宽度≤0.3μm时,即使各区域具有相同厚度的钛,该开口中所形成的硅化物5还是要薄于其余区域(即开口宽度>0.3的区域)。类似地,当金属层4为钴,且介质层2上的开口宽度在0.1μm以下时,在该开口底部所形成的硅化物5的厚度也要薄于其余区域(即开口宽度>0.1μm)中相同厚度的钴所形成的硅化物。在这种情况下,特定金属在小于特定宽度的开口中形成的硅化物明显要薄;这只与金属种类和开口宽度有关,而与开口的高度(深度)无关。
金属与硅反应形成金属硅化物还具有一种特殊情况,当金属层4为具有较好迁移性能的金属,例如为钛;且介质层4的致密性不高,例如为较为疏松的常压CVD膜时,在A2区域所形成的间距为L2的两个或更多开口处,如果L2≤0.1μm,则硅化物会同时在纵向和横向方向生成,从而在A2区域的各个开口底部所形成的金属硅化物5将在横向上连为一体。
图2a~图2d展示了本发明的第二实施例。
第1步,请参阅图2a,在衬底1上已形成有栅氧化层6及其上方的多晶硅栅极7。栅氧化层6的厚度例如为
Figure GDA00003047343700061
多晶硅栅极7的厚度例如为
Figure GDA00003047343700062
第2步,请参阅图2b,在整个硅片淀积一层介质2,其厚度例如为
Figure GDA00003047343700063
Figure GDA00003047343700064
该介质层2的上表面平坦,无凸起。接着在介质层2上旋涂光刻胶3,采用光刻工艺在光刻胶3上形成光刻图形。所述光刻图形为:在需要较厚硅化物的区域(包括多晶硅栅极7的上方)去除光刻胶,形成尺寸较大的开口;在需要较薄硅化物的区域去除光刻胶,形成尺寸较小的开口。
第3步,请参阅图2c,根据光刻图形对介质层2进行刻蚀,刻蚀终点为衬底1的上表面或多晶硅栅极7的上表面。然后去除光刻胶3,此时介质层2的图形为:在需要较厚硅化物的区域(包括多晶硅栅极7的上方)具有尺寸较大的开口;在需要较薄硅化物的区域具有尺寸较小的开口。多晶硅栅极7的上方的开口的深度>衬底1上各个开口的深度。
第4步,请参阅图2d,在整个硅片淀积一层金属,并采用高温退火使该层金属与硅接触的区域形成金属硅化物5,该层金属与多晶硅接触的区域形成多晶硅化物5。再将介质层2之上的金属和没有形成硅化物5的金属去除掉。
此时,在尺寸较大的开口中形成的硅化物5的厚度较厚,在尺寸较小的开口中形成的硅化物5的厚度较薄。
所述第二实施例的第2步中,当硅材料上方的介质层的开口的宽高比越大,则所淀积的金属就越厚,最终形成的硅化物也越厚。当硅材料上方的介质层的开口的宽高比越小,则所淀积的金属就越薄,最终形成的硅化物也越薄。优选地,最大开口的宽高比在最小开口的宽高比的两倍以上。
图3a~图3f展示了本发明的第三实施例。
第1步,请参阅图3a,在衬底1上具有栅氧化层6及其上方的多晶硅栅极7。在整个硅片表面覆盖有一层介质2。在多晶硅栅极7的位置,介质层2具有一个向上的凸起。所述栅氧化层6的厚度例如为
Figure GDA00003047343700071
多晶硅栅极7的厚度例如为
Figure GDA00003047343700072
介质层2例如为氧化硅,厚度为
Figure GDA00003047343700073
Figure GDA00003047343700074
第2步,请参阅图3b,在整个硅片表面旋涂一层底部抗反射涂层(BARC,bottom anti-reflective coating)8。在多晶硅栅极7的位置,该BARC层8仍有向上的凸起,但该凸起已变得较为平缓。可选地,BARC层8也可改用光刻胶,旋涂的光刻胶也会在多晶硅栅极7的位置具有一个陡峭程度减缓的凸起。
第3步,请参阅图3c,采用刻蚀工艺将多晶硅栅极7上方的BARC层8和介质层2去除,保留其余区域的BARC层8和介质层2。接着去除BARC层8,例如采用湿法腐蚀工艺。这样便使多晶硅栅极7的上表面和部分侧壁暴露出来,且凸出于平坦的介质层2之上。
优选地,可首先将多晶硅栅极7上方的BARC层8去除,保留其余区域的BARC层8;接着以剩余的BARC层8作为保护,将多晶硅栅极7上方的介质层2刻蚀掉。最后再去除BARC层8。
第4步,请参阅图3d,采用光刻和刻蚀工艺在介质层2上形成一个或多个开口,每个开口的底部都是衬底1的上表面。
第5步,请参阅图3e,在硅片表面淀积一层金属4,优选为钛。金属4淀积在多晶硅栅极7的上表面、介质层2的上表面、以及介质层2中的各个开口的底部。
第6步,请参阅图3f,采用高温退火使金属4与硅接触的区域形成金属硅化物5,金属4与多晶硅接触的区域形成多晶硅化物5。再将介质层2之上的金属4和没有形成硅化物5的金属4去除掉。
此时,在无遮蔽环境(即多晶硅栅极7的上方)和尺寸较大的开口中形成的硅化物5的厚度较厚,在尺寸较小的开口中形成的硅化物5的厚度较薄。
所述第三实施例的第4步中,当硅材料上方的介质层的开口的宽高比越大,则所淀积的金属就越厚,最终形成的硅化物也越厚。当硅材料上方的介质层的开口的宽高比越小,则所淀积的金属就越薄,最终形成的硅化物也越薄。优选地,最大开口的宽高比在最小开口的宽高比的两倍以上。
进一步地,在上述三个实施例中,可以在完成金属淀积之后,采用化学腐蚀工艺将介质层2去除掉,然后再进行高温退火工艺以形成硅化物5。
在上述第一实施例中,需要形成硅化物的区域是衬底1,其在介质层2以下,在介质层2上刻蚀开口,各个开口的高度(深度)一致。
在上述第二实施例中,需要形成硅化物的区域是衬底1和多晶硅栅极7,这两者仍然在介质层2以下,在介质层2上刻蚀开口,各个开口的高度(深度)不同。
在上述第三实施例中,需要形成硅化物的区域是衬底1和多晶硅栅极7,衬底1在介质层2以下,多晶硅栅极7的上表面在除多晶硅栅极7以外区域的介质层2的上表面以上,在介质层2上刻蚀使多晶硅栅极7的上表面暴露并凸出于介质层2的上表面,同时在介质层2上刻蚀开口,各个开口的高度(深度)一致。
请参阅图4,这是一个射频LDMOS器件的示意图。采用如本发明所述的方法之后,在多晶硅栅极7上方的多晶硅化物5的厚度t6可达
Figure GDA00003047343700091
而源漏区的硅化物5的厚度t5可
Figure GDA00003047343700092
这样在同一个器件(乃至同一个硅片上)形成不同厚度的硅化物,既满足了栅极G对超低方块电阻的要求,又在漏极D上形成薄的金属硅化物,解决了源漏区的漏电问题。
以上仅为本发明的优选实施例,并不用于限定本发明。对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (6)

1.一种形成硅化物的方法,其特征是,包括如下步骤:
第1步,在硅片上淀积一层介质层;
第2步,采用光刻和刻蚀工艺在所述介质层上将需要形成硅化物的区域暴露出来;
当需要形成硅化物的区域低于所述介质层时,在所述介质层上刻蚀出开口,每个开口底部为需要形成硅化物的区域;
当需要形成硅化物的区域高于除该需要形成硅化物的区域以外区域的所述介质层时,刻蚀该需要形成硅化物的区域上方的介质层以使该需要形成硅化物的区域的上表面凸出于所述介质层之上;
第3步,淀积金属并进行高温退火,从而在介质层的每个开口中、和凸出于介质层之上的需要形成硅化物的区域的上表面形成硅化物;
开口的宽高比或宽度越大,在该开口中形成的硅化物就越厚;反之亦然;
第4步,去除未形成硅化物的金属。
2.根据权利要求1所述的形成硅化物的方法,其特征是,所述方法第2步所形成的具有最大宽高比的开口的宽高比为具有最小宽高比的开口的宽高比的两倍以上。
3.根据权利要求1所述的形成硅化物的方法,其特征是,包括如下步骤:
第1步,在硅片上淀积一层介质层,需要形成硅化物的区域低于所述介质层;
第2步,采用光刻和刻蚀工艺,在所述介质层上对应于需要形成硅化物的各个区域形成开口,每个开口均贯穿所述介质层;
第3步,淀积金属并进行高温退火,从而在各个开口底部形成硅化物,宽高比或宽度越大的开口中的硅化物就越厚;
第4步,去除未形成硅化物的金属。
4.根据权利要求1所述的形成硅化物的方法,其特征是,包括如下步骤:
第1步,硅片上已形成有多晶硅栅极,在硅片上淀积一层介质层和一层底部抗反射涂层,所述多晶硅栅极高于除该多晶硅栅极以外区域的介质层;
第2步,采用光刻和刻蚀工艺,使多晶硅栅极的上表面暴露在所述底部抗反射涂层和介质层上,还在所述底部抗反射涂层和介质层上对应于需要形成硅化物的各个区域形成开口,每个开口均贯穿所述介质层;
第3步,淀积金属并进行高温退火,从而在多晶硅栅极上方形成多晶硅化物,在各个开口底部形成硅化物;
第4步,去除未形成硅化物的金属。
5.根据权利要求1或3所述的形成硅化物的方法,其特征是,所述方法第3步中,在淀积金属之后,采用化学腐蚀工艺去除第1步所淀积的介质层,接着再进行高温退火。
6.根据权利要求4所述的形成硅化物的方法,其特征是,所述方法第3步中,在淀积金属之后,采用化学腐蚀工艺去除第1步所淀积的底部抗反射涂层和介质层,接着再进行高温退火。
CN2011103667583A 2011-11-18 2011-11-18 形成硅化物的方法 Active CN102437052B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2011103667583A CN102437052B (zh) 2011-11-18 2011-11-18 形成硅化物的方法
US13/678,752 US20130130486A1 (en) 2011-11-18 2012-11-16 Method of forming silicide layers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011103667583A CN102437052B (zh) 2011-11-18 2011-11-18 形成硅化物的方法

Publications (2)

Publication Number Publication Date
CN102437052A CN102437052A (zh) 2012-05-02
CN102437052B true CN102437052B (zh) 2013-07-24

Family

ID=45985047

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011103667583A Active CN102437052B (zh) 2011-11-18 2011-11-18 形成硅化物的方法

Country Status (2)

Country Link
US (1) US20130130486A1 (zh)
CN (1) CN102437052B (zh)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3047850B2 (ja) * 1997-03-31 2000-06-05 日本電気株式会社 半導体装置
US6319784B1 (en) * 1999-05-26 2001-11-20 Taiwan Semiconductor Manufacturing Company Using high temperature H2 anneal to recrystallize S/D and remove native oxide simultaneously
US6451679B1 (en) * 2000-04-03 2002-09-17 Taiwan Semiconductor Manufacturing Company Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology
JP2002261161A (ja) * 2001-03-05 2002-09-13 Hitachi Ltd 半導体装置の製造方法
US20050124128A1 (en) * 2003-12-08 2005-06-09 Kim Hag D. Methods for manufacturing semiconductor device
KR100642648B1 (ko) * 2005-09-13 2006-11-10 삼성전자주식회사 실리사이드막들을 갖는 콘택 구조체, 이를 채택하는반도체소자, 및 이를 제조하는 방법들
JP2007180181A (ja) * 2005-12-27 2007-07-12 Elpida Memory Inc 半導体記憶装置及びその製造方法
US20080150026A1 (en) * 2006-12-26 2008-06-26 International Business Machines Corporation Metal-oxide-semiconductor field effect transistor with an asymmetric silicide

Also Published As

Publication number Publication date
CN102437052A (zh) 2012-05-02
US20130130486A1 (en) 2013-05-23

Similar Documents

Publication Publication Date Title
JP4836304B2 (ja) 半導体装置
US20120068347A1 (en) Method for processing semiconductor structure and device based on the same
US20070054486A1 (en) Method for forming opening
CN103489786B (zh) 一种阵列基板的制作方法
US20140159172A1 (en) Transistors, Semiconductor Devices, and electronic devices including transistor gates with conductive elements including cobalt silicide
TW202046378A (zh) 具有縮減臨界尺寸的半導體元件及其製備方法
KR100714287B1 (ko) 반도체 소자의 패턴 형성방법
CN102437052B (zh) 形成硅化物的方法
US7341955B2 (en) Method for fabricating semiconductor device
CN115050701A (zh) 半导体结构的制备方法及半导体结构
JP2006148052A (ja) 半導体素子の格納電極形成方法
CN101178549A (zh) 移除光致抗蚀剂层的方法以及开口的形成方法
US20060286756A1 (en) Semiconductor process and method for reducing parasitic capacitance
CN109817528A (zh) Mos晶体管的制造方法
JP2004509465A (ja) 残留物除去を助ける等方性抵抗保護エッチング
US5466640A (en) Method for forming a metal wire of a semiconductor device
CN101562151B (zh) 具有金属硅化物的半导体结构及形成金属硅化物的方法
CN213716906U (zh) 氮化镓半导体器件
US10636658B1 (en) Methods of forming patterns, and methods of patterning conductive structures of integrated assemblies
CN101604670B (zh) 防止芯片压焊时金属层脱落的栅极焊点结构及其形成方法
CN103094473B (zh) 氧化钨阻变存储器的制备方法
KR20100088292A (ko) 반도체 소자의 미세 콘택홀 형성 방법
KR100992631B1 (ko) 반도체 소자의 제조방법
KR20090103508A (ko) 반도체 소자
KR100657164B1 (ko) 컨택 공정 마진을 향상시키는 반도체 소자의 제조 방법 및그 구조

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

Effective date: 20131219

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI

TR01 Transfer of patent right

Effective date of registration: 20131219

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Patentee before: Shanghai Huahong NEC Electronics Co., Ltd.