CN102412209A - 封装基板及使用该封装基板的模块和电气/电子装置 - Google Patents

封装基板及使用该封装基板的模块和电气/电子装置 Download PDF

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Publication number
CN102412209A
CN102412209A CN2011102742479A CN201110274247A CN102412209A CN 102412209 A CN102412209 A CN 102412209A CN 2011102742479 A CN2011102742479 A CN 2011102742479A CN 201110274247 A CN201110274247 A CN 201110274247A CN 102412209 A CN102412209 A CN 102412209A
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China
Prior art keywords
resistance
conductive layer
packaging
base plate
corresponding position
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Pending
Application number
CN2011102742479A
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English (en)
Chinese (zh)
Inventor
花边充广
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Sony Corp
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Sony Corp
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Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of CN102412209A publication Critical patent/CN102412209A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN2011102742479A 2010-09-22 2011-09-15 封装基板及使用该封装基板的模块和电气/电子装置 Pending CN102412209A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010211641A JP5581933B2 (ja) 2010-09-22 2010-09-22 パッケージ基板及びこれを用いたモジュール並びに電気・電子機器
JP2010-211641 2010-09-22

Publications (1)

Publication Number Publication Date
CN102412209A true CN102412209A (zh) 2012-04-11

Family

ID=45817006

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011102742479A Pending CN102412209A (zh) 2010-09-22 2011-09-15 封装基板及使用该封装基板的模块和电气/电子装置

Country Status (5)

Country Link
US (1) US8866277B2 (enExample)
JP (1) JP5581933B2 (enExample)
KR (1) KR20120031121A (enExample)
CN (1) CN102412209A (enExample)
TW (1) TW201214647A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104051420B (zh) * 2013-03-14 2017-08-15 英特尔公司 用于嵌入式互连桥封装的直接外部互连
TWI719231B (zh) * 2016-11-29 2021-02-21 台灣積體電路製造股份有限公司 半導體裝置及佈局方法
CN115377051A (zh) * 2022-08-25 2022-11-22 飞腾信息技术有限公司 封装基板、封装基板设计方法及相关设备

Families Citing this family (11)

* Cited by examiner, † Cited by third party
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US9368477B2 (en) * 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8987872B2 (en) * 2013-03-11 2015-03-24 Qualcomm Incorporated Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages
US9955568B2 (en) * 2014-01-24 2018-04-24 Dell Products, Lp Structure to dampen barrel resonance of unused portion of printed circuit board via
US9824990B2 (en) * 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9650242B2 (en) 2015-09-22 2017-05-16 International Business Machines Corporation Multi-faced component-based electromechanical device
US10431537B1 (en) * 2018-06-21 2019-10-01 Intel Corporation Electromigration resistant and profile consistent contact arrays
US11488901B2 (en) * 2020-04-29 2022-11-01 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US20240145364A1 (en) * 2022-11-02 2024-05-02 Stmicroelectronics S.R.L. Semiconductor device and corresponding method
WO2024104843A1 (en) * 2022-11-16 2024-05-23 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with rows of equidistant wiring elements and further wiring elements at different level connected to mutually spaced conductive areas
EP4372812A1 (en) * 2022-11-16 2024-05-22 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Defining distribution of wiring elements compliant with target current-related value in component carrier with rows of equidistant wiring elements
US12389538B2 (en) * 2023-01-26 2025-08-12 Hewlett Packard Enterprise Development Lp Varying diameters of power-vias in a PCB based on via location

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004134679A (ja) * 2002-10-11 2004-04-30 Dainippon Printing Co Ltd コア基板とその製造方法、および多層配線基板
US20080290495A1 (en) * 2007-03-15 2008-11-27 Hitachi, Ltd. Low noise semiconductor device
CN101542719A (zh) * 2007-03-30 2009-09-23 住友电木株式会社 倒装芯片半导体封装件用接合体、积层材料、密封树脂组合物和电路基板
US7791204B2 (en) * 2005-04-19 2010-09-07 Renesas Technology Corp. Semiconductor device and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
US5665473A (en) * 1994-09-16 1997-09-09 Tokuyama Corporation Package for mounting a semiconductor device
JP2007201030A (ja) * 2006-01-25 2007-08-09 Fujitsu Ltd 電子デバイス
JP2007221014A (ja) 2006-02-20 2007-08-30 Hitachi Ltd 多層配線基板構造

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004134679A (ja) * 2002-10-11 2004-04-30 Dainippon Printing Co Ltd コア基板とその製造方法、および多層配線基板
US7791204B2 (en) * 2005-04-19 2010-09-07 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20080290495A1 (en) * 2007-03-15 2008-11-27 Hitachi, Ltd. Low noise semiconductor device
CN101542719A (zh) * 2007-03-30 2009-09-23 住友电木株式会社 倒装芯片半导体封装件用接合体、积层材料、密封树脂组合物和电路基板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104051420B (zh) * 2013-03-14 2017-08-15 英特尔公司 用于嵌入式互连桥封装的直接外部互连
TWI719231B (zh) * 2016-11-29 2021-02-21 台灣積體電路製造股份有限公司 半導體裝置及佈局方法
CN115377051A (zh) * 2022-08-25 2022-11-22 飞腾信息技术有限公司 封装基板、封装基板设计方法及相关设备
CN115377052A (zh) * 2022-08-25 2022-11-22 飞腾信息技术有限公司 封装基板设计方法及相关设备

Also Published As

Publication number Publication date
TW201214647A (en) 2012-04-01
JP2012069618A (ja) 2012-04-05
US20120068322A1 (en) 2012-03-22
KR20120031121A (ko) 2012-03-30
JP5581933B2 (ja) 2014-09-03
US8866277B2 (en) 2014-10-21

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Application publication date: 20120411