CN102405522A - Semiconductor memory cell and method for manufacturing same - Google Patents

Semiconductor memory cell and method for manufacturing same Download PDF

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Publication number
CN102405522A
CN102405522A CN2009801588268A CN200980158826A CN102405522A CN 102405522 A CN102405522 A CN 102405522A CN 2009801588268 A CN2009801588268 A CN 2009801588268A CN 200980158826 A CN200980158826 A CN 200980158826A CN 102405522 A CN102405522 A CN 102405522A
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mentioned
film
memory cell
semiconductor memory
gate electrode
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田中浩之
金子幸広
加藤刚久
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

Abstract

A semiconductor memory cell is provided with a memory element, which is composed of an MFSFET (21) wherein the gate insulating film is composed of a ferroelectric film (4), and a selection switching element, which is composed of an MISFET (22) wherein the gate insulating film is composed of a paraelectric film (9). The ferroelectric film (4) and the paraelectric film (9) are laminated with an amorphous semiconductor film (5) therebetween, the first gate electrode (3) of the MFSFET (21) is formed on the side of the ferroelectric film (4), and the second gate electrode (10) of the MISFET is formed on the side of the paraelectric film (9). The amorphous semiconductor film (5) configures a shared channel layer for the MFSFET (21) and the MISFET (22), and on the main surface of the amorphous semiconductor film (5), shared source electrode (6) and the drain electrode (8) for the MFSFET (21) and the MISFET (22) are formed.

Description

Semiconductor memory cell and manufacturing approach thereof
Technical field
The present invention relates to the semiconductor memory cell that field-effect transistor that gate insulating film is made up of ferroelectric film is formed.
Background technology
Adopted ferroelectric nonvolatile memory to be broadly divided into following two kinds: capacitor type; And field-effect transistor (the Field Effect Transistor:FET) type that constitutes gate insulating film by ferroelectric film.
Capacitor type is similarly to construct with dynamic random access memory (DRAM), in ferroelectric capacitor, keeps electric charge, according to ferroelectric polarised direction, comes 0,1 state of distinguishes data.When reading of data, owing to the data of storage are destroyed, so need the write activity again of data.For this reason, can make polarization reversal when reading at every turn, thereby cause polarization reversal fatigue to become problem.In addition, in this structure,, need the above quantity of electric charge (being typically 100fC) of detection boundary of sense amplifier owing to read polarization charge with sense amplifier.About ferroelectric, the polarization charge of per unit area is that material is intrinsic, even under the situation with the memory cell miniaturization, as long as adopt identical materials, electrode area just needs certain size.Therefore, it is difficult dwindling capacitor sizes pro rata with the miniaturization of process rule (process rule), is inappropriate for high capacity.
On the other hand; The ferroelectric storage of FET type (MFSFET:Metal-Ferroelectric-Semiconductor FET) is owing to come reading of data through detecting because of the conducting state towards the raceway groove that changes of the polarization of ferroelectric film, thus can be under non-destructive situation sense data.In addition, the output voltage amplitude can be increased, miniaturization can be realized according to scaling rule through the amplification of FET.Therefore, compare, can realize miniaturization significantly with capacitor type.
Yet; Become in the memory cell array of ranks shape in ferroelectric storage matrix configuration the FET type, 2 Value Datas to writing of ferroelectric storage be through to the word line gate electrode that is connected and the source electrode that is connected with source electrode line of the memory cell of selecting between apply potential pulse and carry out.Yet, at this moment, because the memory cell of the non-access object that connects on the word line of the memory cell selected and the source electrode line is also applied voltage, thus the mistake that causes data take place writes.For this reason, between word line and gate electrode and/or between source electrode line and source electrode, for example insert the selector switch element that constitutes by MISFET (Metal-Insulator-Semiconductor FET) usually, prevent that thus mistake from writing.If adopt such structure, then can realize random access (for example, with reference to patent documentation 1) to each memory cell.
Yet, in MFSFET as memory element, if will be as the MISFET plane earth alignment arrangements of selector switch element, need be to the gate electrode electricity separate areas of these FET of major general, so exist cell size to become big problem.
To such problem, the application's applicant has proposed the semiconductor memory cell (patent documentation 2) of the little neotectonics of a kind of cell size.The semiconductor memory cell of this neotectonics adopts following structure: across semiconductor film; With constituting as the ferroelectric film of the gate insulating film of the MFSFET of memory element and constituting paraelectrics film-stack, make this semiconductor film become the shared channel layer of MFSFET and MISFET as the gate insulating film of the MISFET of selector switch element.Through adopting such structure, because the 1st gate electrode and the 2nd gate electrode plane earth of MISFET that becomes the selector switch element of MFSFET that can will become memory element is near configuration, so can dwindle cell size.Under the desirable situation, can cell size be narrowed down to 6F 2(F is the minimum process size).
The prior art document
Patent documentation
Patent documentation 1:JP spy opens flat 5-205487 communique
Patent documentation 2:JP spy opens the 2008-263019 communique
Summary of the invention
The problem that invention will solve
Disclosed semiconductor memory cell is normally made as following in the patent documentation 2: after having formed the 1st gate electrode of MFSFET on the substrate; At substrate laminated ferroelectric film and semiconductor film; Further after having formed source, drain electrode on the semiconductor film, form the paraelectrics film.
Yet; If consider with the peripheral circuit that is used to drive memory cell (decoder, column amplifier etc.) between be connected preferred these memory cell of formation on the silicon substrate of making CMOS (Complementary Metal Oxide Semiconductor) device easily then.In addition, if can use silicon substrate, then help cost and reduce.
Yet, on silicon substrate (silicon oxide film that perhaps forms on the silicon substrate), be not easy the sull that crystallinity is piled up ferroelectric film as the inscape of semiconductor memory cell, semiconductor film etc. well.Therefore, there is the problem that is not easy to obtain the good FET element of switching characteristic.
The present invention makes in view of above-mentioned problem, and its main purpose is to provide the semiconductor memory cell that a kind of switching characteristic is excellent, cell size is little.
Be used to solve the means of problem
In order to solve above-mentioned problem; The present invention adopts following structure: will constitute as the ferroelectric film of the gate insulating film of the MFSFET of memory element and the paraelectrics film that constitutes as the gate insulating film of the MISFET of selector switch element; Gather into folds across semiconductor film; And with in the semiconductor memory cell of this semiconductor film as the shared channel layer of MFSFET and MISFET, semiconductor film uses amorphous semiconductor film.
Semiconductor memory cell in the present invention's one mode possesses the selector switch element that the 2nd field-effect transistor that memory element that the 1st field-effect transistor that gate insulating film is made up of ferroelectric film forms and gate insulating film be made up of the paraelectrics film is formed; Ferroelectric film and paraelectrics film are across amorphous semiconductor film and range upon range of; In the ferroelectric film side; Form the 1st gate electrode of the 1st field-effect transistor; In paraelectrics film side, form the 2nd gate electrode of the 2nd field-effect transistor, amorphous semiconductor film constitutes the shared channel layer of the 1st field-effect transistor and the 2nd field-effect transistor; On the interarea of amorphous semiconductor film, form the 1st field-effect transistor and the 2nd field-effect transistor shared source electrode and drain electrode.
Through such structure, owing to having an even surface of amorphous semiconductor film, so can obtain the excellent selector switch element (the 2nd field-effect transistor) of switching characteristic.In addition, even under the situation that semiconductor film is made up of the material with spontaneous polarization, semiconductor film can crystallization yet, is 0 so can make spontaneous polarization.Therefore, charge carrier can be do not produced naturally, the selector switch element of threshold voltage change can be obtained not having at the interface of the amorphous semiconductor film that constitutes channel layer.
In other modes of the present invention, preferred above-mentioned amorphous semiconductor film is made up of metal oxide.Thus; Under the ferroelectric film of the gate insulating film that constitutes semiconductor memory cell and situation that the paraelectrics film is made up of metal oxide; Engage to each other with constituting the dielectric film oxide identical at these, so be difficult to form conversion zone at the interface with the amorphous semiconductor film of channel layer.Therefore, good interface can be obtained, switching characteristic excellent semiconductor memory component (the 1st field-effect transistor) and selector switch element (the 2nd field-effect transistor) can be obtained.
In other modes of the present invention, above-mentioned amorphous semiconductor film preferably is made up of a kind the metal oxide that comprises indium (In), gallium (Ga), zinc (Zn) at least.Thus, no matter whether semiconductor film is noncrystal, can both obtain the high raceway groove structure of mobility.Its result, it is big that the connection resistance of semiconductor memory component and selector switch element becomes, so the difference of the output voltage when data read becomes big, can improve the S/N ratio.At this, amorphous semiconductor film preferably is made up of the metal oxide of In-Ga-Zn-O class.Thus, can obtain mobility with the ZnO film same levels of polycrystalline.
In other modes of the present invention, the carrier concentration of preferred above-mentioned amorphous semiconductor film is 10 18Individual/cm 3Below.Thus, can reduce the turn-off current of semiconductor memory component and selector switch element.Therefore, the difference of the output voltage when data read becomes big, can improve the S/N ratio.
The manufacturing approach of the semiconductor memory cell in the mode of the present invention comprises: the operation (a) that on substrate, forms the 1st gate electrode; On substrate, form the operation (b) of ferroelectric film according to the mode that covers the 1st gate electrode; On ferroelectric film, form the operation (c) of amorphous semiconductor film; On amorphous semiconductor film, form the operation (d) of source electrode and drain electrode; On amorphous semiconductor film, form the operation (e) of paraelectrics film according to the mode that covers source electrode and drain electrode; With on the paraelectrics film, form the operation (f) of the 2nd gate electrode.
Through such method, can easily make the little above-mentioned semiconductor memory cell of cell size.
In other modes of the present invention, above-mentioned operation (b) afterwards, operation (c) before, also comprise the smoothing treatment procedures carried out on the surface of ferroelectric film.Through such method, even be formed under the situation of the big film of surface undulation (for example polycrystalline film) at ferroelectric film, also can make and the non-crystalline oxide semiconductor film between the interface precipitous.Because the at random of conduction electron is inhibited, so can increase the making current of semiconductor memory component (the 1st field-effect transistor), thus, the difference of the output voltage when data read becomes big, can improve the S/N ratio in the precipitous interface.
The invention effect
According to the present invention, the semiconductor film that constitutes the shared channel layer of semiconductor memory component (MFSFET) and selector switch element (MISFET) passes through to adopt amorphous semiconductor film, thereby can realize the semiconductor memory cell that switching characteristic is outstanding, cell size is little.
Description of drawings
Fig. 1 (a) and (b) are figure of the structure of disclosed semiconductor memory cell in the expression patent documentation 2, (a) are its cutaway view, (b) are its equivalent circuit diagrams.
Fig. 2 (a)～(d) is the cutaway view of the production order of the MFSFET in the expression semiconductor memory cell.
Fig. 3 is the curve chart of leakage current-gate electrode characteristic of the MFSFET in the expression semiconductor memory cell.
Fig. 4 (a)～(c) is the cutaway view of the production order of the MISFET in the expression semiconductor memory cell.
Fig. 5 is the curve chart of leakage current-gate electrode characteristic of the MISFET in the expression semiconductor memory cell.
Fig. 6 is the cutaway view of semiconductor memory cell of measuring point of the surface roughness of expression ZnO film.
Fig. 7 (a)～(d) is the afm image of measurement result of the surface roughness of expression ZnO film.
Fig. 8 (a) and (b) be that expression is measured the crystallinity of PZT film and ZnO film with EBSD and the result's that obtains diffraction image.
Fig. 9 (a) is the crystallization sketch map of ZnO, and Fig. 9 (b) is the cutaway view of semiconductor memory cell, and Fig. 9 (c) is the amplification view that is formed with the zone of MISFET.
Figure 10 (a) is the cutaway view of the structure of the semiconductor memory cell in the expression execution mode of the present invention, and Figure 10 (b) is its equivalent circuit diagram.
Figure 11 (a)～(d) is the cutaway view of the manufacturing process of the semiconductor memory cell in the expression execution mode of the present invention.
Figure 12 (a)～(c) is the cutaway view of the manufacturing process of the semiconductor memory cell in the expression execution mode of the present invention.
Figure 13 (a)～(d) is the afm image of measurement result of the surface roughness of the IGZO film of expression in the execution mode of the present invention.
Figure 14 (a) and (b) be that expression is measured the crystallinity of PZT film and IGZO film in the execution mode of the present invention with EBSD and the result's that obtains diffraction image.
Figure 15 is the curve chart of leakage current-gate electrode characteristic of the MISFET in the expression execution mode of the present invention.
Figure 16 (a) is the cutaway view of the structure of the semiconductor memory cell in expression other execution modes of the present invention, and Figure 16 (b) is its equivalent circuit diagram.
Figure 17 (a) is the cutaway view of the structure of the semiconductor memory cell in expression other execution modes of the present invention, and Figure 17 (b) is its equivalent circuit diagram.
Figure 18 is the table of the action of the semiconductor memory cell in this execution mode of explanation.
Figure 19 (a) and (b) be the cutaway view of the action of the semiconductor memory cell of explanation in this execution mode.
Figure 20 is the circuit diagram that expression is configured to the semiconductor memory cell in this execution mode the structure of array-like.
Embodiment
Before execution mode of the present invention is described, describe how expecting fact of the present invention.
Fig. 1 (a) and (b) are figure of applicant's structure of disclosed semiconductor memory cell 120 in patent documentation 2 of expression the application, (a) are its cutaway view, (b) are its equivalent circuit diagrams.
Shown in Fig. 1 (a), on substrate 101, ferroelectric film 104 and paraelectrics film 109 are range upon range of and form across semiconductor film 105, in ferroelectric film 104 sides, form the gate electrode 103 of MFSFET, in paraelectrics film 109 sides, form the gate electrode 110 of MISFET.In addition, semiconductor film 105 constitutes MFSFET and the shared channel layer of MISFET, on semiconductor film 105, forms MFSFET and shared source electrode 106, drain electrode 108 and the target 107 of MISFET.
Promptly; Shown in Fig. 1 (a); Semiconductor memory cell 120 becomes the structure that MISFET (selector switch element) tegillum of MFSFET (memory element) and the top gate type of bottom gate type gathers into folds, and the words of representing with equivalent electric circuit become the structure that MFSFET121 and MISFET122 are connected in series shown in Fig. 1 (b).
Data are carried out to writing through following that kind of memory element: the voltage that the gate electrode 110 of MISFET122 is applied regulation; Making the selector switch element is on-state; Between the gate electrode 103 of MFSFET121 and drain electrode 108, apply the voltage of regulation; Thereby produce electric field at ferroelectric film 104, thus, the polarized state of ferroelectric film 104 is changed.
The reading through following that kind of data that is written in the memory element carried out: the voltage that the gate electrode 110 of MISFET122 is applied regulation; Making the selector switch element is on-state; And to applying the voltage of regulation between source electrode 106 and the drain electrode 108, detect the electric current that flows through at channel layer (semiconductor film 105) according to the polarized state of ferroelectric film 104.
The application's inventors are produced on the semiconductor memory cell of said structure on the silicon substrate, have carried out the evaluating characteristics of MFSFET121 and MISFET122.
At first, in order to estimate the characteristic of MFSFET121,, on silicon substrate, make MFSFET according to the order shown in Fig. 2 (a)～(d).
Shown in Fig. 2 (a), when on silicon substrate 101, having formed silicon oxide film (SiO 2) after 102, form gate electrode 103 by the stacked film formation of platinum and ruthenic acid strontium (SRO).
Next, shown in Fig. 2 (b), at SiO 2On the film 102, pile up by titanium, lead zirconates (Pb (Zr, Ti) O 3, below be called PZT) and the gate insulating film (ferroelectric film) 104 that constitutes of film.At this moment, the PZT film 104 of the position that overlaps with gate electrode 103 plane earths is single-orientated on (111) direction, but surface roughness (RMS) arrives the degree of 10nm greatly.Therefore, make the surface smoothingization of PZT film 104, make surface roughness (RMS) become the degree of the 0.6nm of atomic layer grade through cmp.
Next, shown in Fig. 2 (c), on PZT film 104, the semiconductor film 105 that constitutes by ZnO film of ulking thickness 30nm.The ZnO film 105 of the position that overlaps with gate electrode 103 plane earths at this moment, is single-orientated on (0001) direction.
Next, on ZnO film 105, form source electrode 106, target 107 and the drain electrode 108 that the stacked film by platinum and titanium constitutes, make MFSFET through peeling off (lift off) method.
In order to estimate the characteristic of the MFSFET that produces, with source electrode 106 ground connection, middle electrode (being equivalent to drain electrode) 107 has been applied under the state of voltage of 0.1V, the voltage that makes gate electrode 103 is measured leakage current from-10V scanning (sweep) to+10V.
Fig. 3 is the curve chart of expression leakage current-gate electrode characteristic, and leakage current is to describe counterclockwise hysteresis loop with respect to grid voltage, according to the counter-rotating of ferroelectric spontaneous polarization and by modulation significantly.And then the connection of gate electrode 103 raceway groove during for 0V is broken off than being more than 5.This is the characteristic that can clearly distinguish the polarized state that is written to ferroelectric gate insulating film, and the MFSFET that can confirm to be formed on the silicon substrate has enough characteristics as memory element.
Next, in order to estimate the characteristic of MISFET122, after producing MFSFET121,, make MISFET122 further according to the order shown in Fig. 4 (a)～(c).
Shown in Fig. 4 (a), on semiconductor film 105, formed the gate insulating film (paraelectrics film) 109 that constitutes by silicon nitride film (SiNx).As Fig. 4 (b) shown in, on SiNx film 109, through peel off method formed the gate electrode 110 that by stacked film golden and titanium constitute thereafter.Further, shown in Fig. 4 (c), form and source electrode 106, target 107, drain electrode 108 electrodes in contact 111a～111c, produce MISFET thus.
In order to estimate the characteristic of the MISFET that produces, with target (being equivalent to the source electrode) 107 ground connection, drain electrode 108 has been applied under the state of voltage of 0.1V, the voltage of gate electrode 103 is scanned+10V from-10V, measure leakage current.
Fig. 5 be the expression leakage current-gate electrode characteristic curve chart, leakage current be with respect to grid voltage only modulated 2 degree, threshold value is also to the back bias voltage side shifting.And then no matter whether gate insulating film 109 is paraelectrics, leakage current has all been represented the hysteresis resume.That is, distinguished that the MISFET that produces is as the inadequate characteristic of selector switch element.
As the further result who studies the unexcellent reason of switching characteristic of the MISFET that produces and obtain of present inventors, drawn as drawing a conclusion.
At first, the surface roughness of the ZnO film 105 that constitutes raceway groove is estimated.Fig. 6 is the figure of the measuring point of presentation surface roughness; In regional A that overlaps with gate electrode 103 plane earths of MFSFET and the area B that overlaps with gate electrode 110 plane earths of MISFET; Utilize AFM (Atomic Force Microscope: atomic force microscope), come to measure respectively the surface roughness of the ZnO film 105 at interface X and the Y place, interface between ZnO film 105 and the SiNx film 109 between PZT film 104 and the ZnO film 105.
Fig. 7 is its result's of expression a afm image; The X at the interface; The surface roughness (RMS) of zone A, B is all little of 0.6nm (with reference to Fig. 7 (c), (d)); And at the interface Y, arrive 1.8nm (with reference to Fig. 7 (a)) greatly in regional A surface roughness (RMS), arrive 1.3nm (with reference to Fig. 7 (b)) greatly in area B surface roughness (RMS).The reason that the X surface roughness is little at the interface is that the surface of PZT film 104 is ground.On the other hand, be considered to be in ZnO film 105 polycrystalline growths that form on the PZT film 104 of polycrystalline in the interface big reason of Y surface roughness, produced the surface roughness that is caused by crystal grain, this is inferred to be one of unexcellent reason of the switching characteristic of MISFET.
Next, utilize electron beam backscattering diffraction (EBSD) to come the crystallinity of ZnO film 105 is estimated.Fig. 8 (a) and (b) are diffraction images of its result of expression, and Fig. 8 (a) is the regional A of PZT film 104 and the diffraction image of area B, and Fig. 8 (b) is the regional A of ZnO film 105 and the diffraction image of area B.
At regional A, PZT film 104 is single-orientated on (111) direction, and ZnO film 105 is single-orientated on (0001) direction, and the crystalline particle diameter is 150nm～250nm.On the other hand, in area B, can't obtain diffraction image, PZT film 104 and ZnO film 105 are noncrystal or micro-crystallization.Its reason is considered to: because the good crystallinity of the platinum of the gate electrode 103 of formation MFSFET, so PZT film 104, ZnO film 105 crystallizations piled up above that, and in the zone that does not have gate electrode 103, because substrate is noncrystal SiO 2Film 102 is so be difficult to crystallization.If the crystallization of ZnO film 105 is insufficient, then form oxygen vacancies easily, so carrier concentration uprises.Under the high situation of carrier concentration,, it is inferred for to be formed with the area B of MISFET one of reason that switching characteristic is unexcellent owing to can not freely modulate charge carrier.
Next, to the intrinsic character of ZnO film 105, be that spontaneous polarization is studied.Fig. 9 (a) is the crystallization sketch map of ZnO, and Fig. 9 (b) is the cutaway view of semiconductor memory cell, and Fig. 9 (c) is the amplification view that is formed with the zone of MISFET.
Shown in Fig. 9 (a), ZnO is in [0001] direction, and having size is 5.5 μ C/cm 2Spontaneous polarization Ps, thereby accumulated 3 * 10 on the surface of ZnO film 105 13Individual/cm 2Charge carrier.Therefore; Shown in Fig. 9 (c); The spontaneous polarization of the ZnO film 105 that the direction orientation forms in PZT film 104 upper edges (0001) is towards SiNx film 109 sides, so even gate electrode 110 is not being applied under the state of voltage, electronics has also been accumulated at the interface between ZnO film 105 and SiNx film 109.This is inferred to be the threshold value of the MISFET reason to the back bias voltage side shifting.
Present inventors are based on above-mentioned conclusion; Various researchs have been carried out; Even the result of research be notice through making the semiconductor film 105 that constitutes raceway groove material for concavo-convex less, the crystallinity difference also is difficult to produce the amorphous semiconductor material of residual charge carrier; Thereby can get rid of the key factor of the switching characteristic deterioration that makes MISFET, expect the present invention thus.
Below, at length execution mode of the present invention is described based on accompanying drawing.In addition, the present invention is defined in following execution mode.In addition, in not breaking away from the scope that can play effective scope of the present invention, can suitably change.In addition, also can be combination with other execution modes.
Figure 10 (a) is the cutaway view that schematically shows the structure of the semiconductor memory cell 20 in the execution mode of the present invention, and Figure 10 (b) is its equivalent circuit diagram.
Shown in Figure 10 (a) and (b), semiconductor memory cell 20 comprises: the memory element that the 1st field-effect transistor (MFSFET) 21 that gate insulating film is made up of ferroelectric film 4 is formed; The selector switch element that the 2nd field-effect transistor (MISFET) 22 that is made up of paraelectrics film 9 with gate insulating film is formed.In addition, and range upon range of, in ferroelectric film 4 sides, the 1st gate electrode 3 of formation MFSFET21 in paraelectrics film 9 sides, forms the 2nd gate electrode 10 of MISFET22 across amorphous semiconductor film 5 for ferroelectric film 4 and paraelectrics film 9.At this, amorphous semiconductor film 5 constitutes the shared channel layer of MFSFET21 and MISFET22.In addition, on the interarea of amorphous semiconductor film 5, form MFSFET21 and shared source electrode 6 and the drain electrode 8 of MISFET22.
Promptly; Semiconductor memory cell 20 in this execution mode becomes the range upon range of structure of MISFET (selector switch element) 22 of MFSFET (memory element) 21 and the top gate type of bottom gate type; If represent, then become the structure that MFSFET21 and MISFET22 are connected in series with equivalent electric circuit.
At this; Data are carried out to writing through following that kind of memory element 21: through the gate electrode 10 of MISFET22 being applied the voltage of regulation; Make selector switch element 22 be on-state, to applying the voltage of regulation between the gate electrode 3 of MFSFET21 and the drain electrode 8, thereby at ferroelectric film 4 generation electric fields; Thus, the polarized state of ferroelectric film 4 is changed.
The reading through following that kind of data that is written to memory element 21 carried out: the voltage that the gate electrode 10 of MISFET22 is applied regulation; Make the selector switch element become on-state; And to applying the voltage of regulation between source electrode 6 and the drain electrode 8, the electric current that flows through in the polarized state detection channel layer (semiconductor film 5) according to ferroelectric film 4.
Next, the manufacturing approach of the semiconductor memory cell 20 in this execution mode is described with reference to Figure 11 (a)～(d) and Figure 12 (a)～(c).
At first, shown in Figure 11 (a), on silicon substrate 1, formed silicon oxide film (SiO 2) after 2, form the 1st gate electrode 3 by the stacked film formation of platinum and ruthenic acid strontium (SRO).
Next, shown in Figure 11 (b), at SiO 2On the film 2, pile up by titanium, lead zirconates (Pb (Zr, Ti) O 3, following PZT) and the gate insulating film (ferroelectric film) 4 that constitutes of film.The PZT film 4 of the position that overlaps with the 1st gate electrode 3 plane earths at this moment, is single-orientated on (111) direction.
Next, make the surface smoothingization of PZT film 4 through cmp after, shown in Figure 11 (c), on PZT film 4, the amorphous semiconductor film 5 that constitutes by InGaZnO (IGZO) film of ulking thickness 20nm.
Next, shown in Figure 11 (d), on IGZO film 5, form source electrode 6, target 7 and the drain electrode 8 that the stacked film by platinum and titanium constitutes, form MFSFET21 thus through peeling off method.
Next, shown in Figure 12 (a), on IGZO film 5, form the 2nd gate insulating film (paraelectrics film) 9 that constitutes by silicon nitride film (SiNx).As Figure 12 (b) shown in, on SiNx film 9, through peel off method form the gate electrode 110 that by stacked film golden and titanium constitute thereafter.And then, shown in Figure 12 (c), form and source electrode 6, target 7, drain electrode 8 electrodes in contact 11a～11c, form MISFET22.Thus, accomplished the semiconductor memory cell 20 of the range upon range of structure of MFSFET (memory element) 21 and MISFET (selector switch element) 22.
To be expression carried out measuring and the result's that obtains afm image to the surface roughness of the IGZO film 5 that constitutes raceway groove Figure 13.In addition; Shown in Figure 10 (a); In regional A that overlaps with plane earth with the 1st gate electrode 3 of MFSFET21 and the area B that overlaps with the 2nd gate electrode 10 plane earths of MISFET22, measured the surface roughness on surface of the ZnO film 105 at interface X and the Y place, interface between IGZO film 5 and the SiNx film 9 between PZT film 4 and the IGZO film 5 respectively.
Shown in figure 13, the Y at the interface, the surface roughness of regional A and area B (RMS) is the degree of 0.6～0.7nm, this and the regional A at interface X place and surface roughness (RMS) 0.6nm of area B are almost same degree.Its reason is considered to: because IGZO film 5 is noncrystal, so can not produce the surface roughness that causes because of crystal grain.
Figure 14 (a) and (b) are diffraction images of the result that obtains with the crystallinity of electron beam backscattering diffraction (EBSD) measurement PZT film 4 and IGZO film 5 of expression.Figure 14 (a) is the regional A of PZT film 4 and the diffraction image of area B, and Figure 14 (b) is the regional A of IGZO film 5 and the diffraction image of area B.
PZT film 4 at regional A crystallization, does not have crystallization in area B shown in Figure 14 (a).On the other hand, IGZO film 5 does not all obtain diffraction image at regional A and area B shown in Figure 14 (b), do not have crystallization.That is, no matter the crystallinity of the PZT film 4 of substrate how, IGZO film 5 all is uniform noncrystalline state.
About the MISFET22 of the semiconductor memory cell 20 that forms, shown in figure 15 when using the method identical to measure leakage current-grid voltage characteristic with method shown in Figure 5, obtained the good switching characteristic that does not lag behind.
Its reason is considered to: through making the semiconductor film 5 that constitutes raceway groove for noncrystal; Thus; 1) surface roughness of semiconductor film 5 reduces; 2) semiconductor film 5 becomes the crystalline even of the ferroelectric film 4 that do not rely on substrate and noncrystalline state that residual charge carrier is few, 3) spontaneous polarization of semiconductor film 5 becomes 0.
In the present invention, the not special restriction of the material of amorphous semiconductor film 5, but the preferred material that constitutes by metal oxide that adopts.Under the ferroelectric film 4 of the gate insulating film that constitutes semiconductor memory cell and situation that paraelectrics film 9 is made up of metal oxide; Be engaged to each other with the amorphous semiconductor film 5 identical oxides that constitute dielectric film and channel layer, so be difficult to form conversion zone at the interface.Therefore, good interface can be obtained, switching characteristic excellent MFSFET and MISFET can be obtained.
In addition, adopted the IGZO film in the above-described embodiment as amorphous semiconductor film 5, but not limited thereto, also can adopt the material that constitutes by at least a kind the metal oxide that comprises indium (In), gallium (Ga), zinc (Zn).No matter the semiconductor film 5 that is made up of these materials is whether noncrystal, and mobility is all very high (to be typically 15～20cm 2/ Vs), so can increase the connection resistance of semiconductor memory component and selector switch element.Thus, the difference of the output voltage when data read becomes big, can improve the S/N ratio.In addition, the carrier concentration of amorphous semiconductor film 5 is preferably 10 18Individual/cm 3Below.Thus, can reduce the turn-off current of semiconductor memory component and selector switch element.Therefore, the difference of the output voltage when data read becomes big, can improve the S/N ratio.
In addition, as the material of amorphous semiconductor film 5, except metal oxide, can also adopt the silicon or the germanium of non-oxidized substance.In addition, amorphous semiconductor film 5 can form through methods such as PLD (Pulse Laser Deposition) method, MOCVD (Metal Organic Chemical Vapor Deposition) method, sputtering method, vacuum vapour depositions.
In addition, in this execution mode, ferroelectric film 4 has adopted the PZT film, but is not limited thereto, and for example, also can adopt the PZT film that has added lanthanum (La), niobium (Nb), vanadium (V), tungsten (W), praseodymium (Pr), samarium elements such as (Sm).Through adding other elements, reduced crystallized temperature, thus can under cryogenic conditions, form, and also obtained reducing the tired effect of polarization reversal repeatedly.In addition, also can adopt bismuth titanates (Bi 4Ti 3O 12), bismuth lanthanum titanate (Bi 3.25La 0.75Ti 3O 12), bismuth tantalic acid strontium (Sr (Bi, Ta) 2O 9), ferrous acid bismuth (BiFeO 3), manganous acid yttrium (YMnO 3) etc.
In addition, ferroelectric film 4 is preferably formed and is polycrystalline film.Its reason is: on the silicon substrate of required cmos circuit such as the driver that is formed with memory chip, and epitaxial growth ferroelectric film easily, so through adopting the ferroelectric film of polycrystalline, thereby can obtain and the incorporate element of drive circuit.For example have following structure: between cmos circuit and this memory element, get involved interlayer dielectric, the platinum that adopts polycrystalline is as the 1st gate electrode, and the PZT that adopts polycrystalline is as ferroelectric film.
In addition, in the present invention, semiconductor memory cell 20 is not to be defined in the structure shown in Figure 10 (a), can adopt various structures yet.For example, shown in Figure 16 (a) and (b), also can be the structure that has omitted target 7.Under this situation, the 1st gate electrode 3 preferably has the zone that a part of plane earth overlaps with the 2nd gate electrode 10.In addition, shown in Figure 17 (a) and (b), also can be the structure that the 1st gate electrode 3 and the 2nd gate electrode 10 are disposed opposed to each other.Under this situation, shown in Figure 17 (b), MFSFET21 and MISFET21 become the structure that is connected in parallel, and can carry out the action of nand type memory.
Next, the action of semiconductor memory cell is described with reference to Figure 18 and Figure 19 (a) and (b).At this semiconductor memory cell with the structure shown in Figure 16 (a) and (b) is that example describes.
Under non-Access status, the 1st gate electrode the 3, the 2nd gate electrode 10 and source electrode 6 ground connection.Through making the 2nd gate electrode 10 ground connection, thereby MISFET22 becomes off-state, even drain electrode 8 is applied voltage arbitrarily, can not produce mistake again at MFSFET21 and write.
In the write activity of data, the 2nd gate electrode 10 is applied positive voltage (for example 12V), and to make MISFET22 be on-state, and drain electrode 8 and the 1st gate electrode 3 are applied voltage, writes voltage to applying between channel layer 5 and the 1st gate electrode 3.For example, under the situation that writes data " 1 ",, the 1st gate electrode 3 is applied positive voltage (for example 10V) with drain electrode 8 ground connection.In addition, under the situation that writes data " 0 ",, drain electrode 8 is applied positive voltage (for example 10V) with the 1st gate electrode 3 ground connection.Thus; Under the situation that writes data " 1 ", the polarization of the gate insulating film 4 of MFSFET is shown in Figure 19 (b), towards last direction (channel layer 5 directions); The polarization of gate insulating film 4 is shown in Figure 19 (a), towards lower direction (the 1st gate electrode 3 directions) under the situation that writes data " 0 ".
Reading in the action of data; With the 1st gate electrode 3 ground connection; The 2nd gate electrode 10 is applied positive voltage (for example 12V), and making MISFET22 is on-state, to applying voltage (for example 1V) between drain electrode 8, the source electrode 6; If the leakage current that flows through is greatly then read " 1 ", then read " 0 " if leakage current is little.
Figure 20 is the circuit diagram that expression is configured to semiconductor memory cell 20 structure of array-like.In Figure 20, expression is configured to semiconductor memory cell 20 example of 4 row * 4 row.In each semiconductor memory cell 20; The 1st gate electrode of MFSFET (semiconductor memory component) is connected in the 1st word line WL1 of row decoder 30 sides; The 2nd gate electrode of MISFET (selector switch element) is connected in the 2nd word line WL2; Drain electrode is connected in the bit line ML of column decoder 31 sides, and the source electrode is connected in source electrode line (not shown).In this execution mode,, have source electrode and drain electrode thereby constitute neighbouring semiconductor memory component through with MFSFET alternately counter-rotating configuration on column direction.Thus, can dwindle the area that the unit occupies.In addition, MFSFET in this execution mode and MISFET are transparent for visible light, so can memory function, switching function be additional to the purposes that Electronic Paper etc. requires the transparency.
More than, through the present invention preferred embodiment has been described, but above-mentioned these descriptions do not constitute qualification of the present invention, certainly carry out various changes.
Industrial applicability
The present invention is useful for having adopted the integrated storage/switch element of ferroelectric superelevation.
The explanation of Reference numeral:
1 silicon substrate;
2SiO 2Film;
3 the 1st gate electrodes;
4 ferroelectric films (gate insulating film);
5IGZO film (amorphous semiconductor film);
6 source electrodes;
7 targets;
8 drain electrodes;
9 paraelectrics films (gate insulating film);
10 the 2nd gate electrodes;
11a～11c electrode;
20 semiconductor memory cells;
21MFSFET (the 1st field-effect transistor);
22MISFET (the 2nd field-effect transistor);
30 row decoders;
31 column decoders.

Claims (10)

1. semiconductor memory cell, it possesses: the memory element that the 1st field-effect transistor that gate insulating film is made up of ferroelectric film is formed; The selector switch element that the 2nd field-effect transistor that is made up of the paraelectrics film with gate insulating film is formed,
Above-mentioned ferroelectric film and above-mentioned paraelectrics film be across amorphous semiconductor film and range upon range of,
In above-mentioned ferroelectric film side, form the 1st gate electrode of above-mentioned the 1st field-effect transistor,
In above-mentioned paraelectrics film side, form the 2nd gate electrode of above-mentioned the 2nd field-effect transistor,
Above-mentioned amorphous semiconductor film constitutes the shared channel layer of above-mentioned the 1st field-effect transistor and above-mentioned the 2nd field-effect transistor,
On the interarea of above-mentioned amorphous semiconductor film, form above-mentioned the 1st field-effect transistor and shared source electrode and the drain electrode of above-mentioned the 2nd field-effect transistor.
2. semiconductor memory cell according to claim 1, wherein,
Above-mentioned the 2nd gate electrode is applied the voltage of regulation, and making above-mentioned selector switch element is on-state,
To applying the voltage of regulation between above-mentioned the 1st gate electrode and the above-mentioned drain electrode, the polarized state of above-mentioned ferroelectric film is changed, thus above-mentioned memory element is carried out writing of data.
3. semiconductor memory cell according to claim 1, wherein,
Above-mentioned the 2nd gate electrode is applied the voltage of regulation, and making above-mentioned selector switch element is on-state,
To applying the voltage of regulation between above-mentioned source electrode and the above-mentioned drain electrode, detect the electric current that in above-mentioned channel layer, flows through according to the polarized state of above-mentioned ferroelectric film, be written to reading of data in the above-mentioned memory element thus.
4. semiconductor memory cell according to claim 1, wherein,
Above-mentioned amorphous semiconductor film is made up of metal oxide.
5. semiconductor memory cell according to claim 4, wherein,
Above-mentioned amorphous semiconductor is made up of a kind the metal oxide that comprises indium In, gallium Ga, zinc Zn at least.
6. semiconductor memory cell according to claim 5, wherein,
Above-mentioned amorphous semiconductor film is made up of the metal oxide of In-Ga-Zn-O class.
7. semiconductor memory cell according to claim 1, wherein,
The carrier concentration of above-mentioned amorphous semiconductor film is 10 18Individual/cm 3Below.
8. the manufacturing approach of a semiconductor memory cell is used to make the described semiconductor memory cell of claim 1, and said manufacturing approach comprises:
Operation (a) forms above-mentioned the 1st gate electrode on substrate;
Operation (b) forms above-mentioned ferroelectric film according to the mode that covers above-mentioned the 1st gate electrode on aforesaid substrate;
Operation (c) forms above-mentioned amorphous semiconductor film on above-mentioned ferroelectric film;
Operation (d) forms above-mentioned source electrode and drain electrode on above-mentioned amorphous semiconductor film;
Operation (e) forms above-mentioned paraelectrics film according to the mode that covers above-mentioned source electrode and drain electrode on above-mentioned amorphous semiconductor film; With
Operation (f) forms above-mentioned the 2nd gate electrode on above-mentioned paraelectrics film.
9. the manufacturing approach of semiconductor memory cell according to claim 8, wherein,
Above-mentioned operation (b) afterwards, above-mentioned operation (c) before, also comprise the smoothing treatment procedures carried out on the surface of above-mentioned ferroelectric film.
10. the manufacturing approach of semiconductor memory cell according to claim 8, wherein,
In above-mentioned operation (b), above-mentioned ferroelectric film is formed polycrystalline film.
CN2009801588268A 2009-05-13 2009-12-14 Semiconductor memory cell and method for manufacturing same Pending CN102405522A (en)

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Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09135009A (en) * 1995-09-05 1997-05-20 Mitsubishi Chem Corp Nonvolatile semiconductor storage device and element
JP2000340759A (en) * 1999-05-31 2000-12-08 Sony Corp Nonvolatile semiconductor memory and drive method therefor
JP2008171990A (en) * 2007-01-11 2008-07-24 Toppan Printing Co Ltd Field effect transistor and manufacturing method thereof
JP2008263019A (en) * 2007-04-11 2008-10-30 Matsushita Electric Ind Co Ltd Semiconductor memory cell and its manufacturing method
KR101283539B1 (en) * 2007-08-29 2013-07-15 삼성전자주식회사 Inverted non-volatile memory devices, stack modules and method of fabricating the same
JPWO2009034953A1 (en) * 2007-09-10 2010-12-24 出光興産株式会社 Thin film transistor

Cited By (7)

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US9530794B2 (en) 2013-05-17 2016-12-27 Micron Technology, Inc. Apparatuses having a ferroelectric field-effect transistor memory array and related method
US9786684B2 (en) 2013-05-17 2017-10-10 Micron Technology, Inc. Apparatuses having a ferroelectric field-effect transistor memory array and related method
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