KR100219522B1 - A semiconductor device having single crystal ferroelectric film and fabrication method of the same - Google Patents

Abstract

The present invention relates to a semiconductor device having a single crystal ferroelectric film and a method of manufacturing the same. The present invention provides a first buffer layer, a Y ₂ O ₃ layer, a CeO ₂ layer, and a STO as a first epitaxial layer formed of a single crystal ZrO ₂ film having a crystal direction of (100) on a single crystal silicon substrate having a crystal direction of (100). The second buffer layer 60 as a second epitaxial layer is formed by growing a material layer selected from the group consisting of layers in the (100) direction, and then a ferroelectric film is formed thereon to form a ferroelectric film having a crystal direction of (100). can do.

Therefore, it is possible to prevent the deterioration of characteristics due to the defect of the ferroelectric film, and to improve the polarization characteristics, thereby preventing the pinning phenomenon in the domain of the ferroelectric film during polarization inversion. In addition, an ideal ferroelectric memory device capable of high-speed operation at a low driving voltage may be implemented by adjusting a growing crystal direction of the ferroelectric film.

Description

A semiconductor device having a single crystal ferroelectric film and a manufacturing method therefor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a ferroelectric film and a manufacturing method thereof, and more particularly to a semiconductor device having a single crystal ferroelectric film and a method of manufacturing the same.

Ferroelectrics have strong spontaneous polarization so that spontaneous polarization is generated inside the ferroelectric by the application of an external electric field, and the spontaneous polarization exists even after the external electric field is removed. It can be a material. Ferroelectrics such as PZT (Pb (Zr, Ti) O ₃ ) have been studied as memory materials since ferroelectrics are consistent with the basic concept of binary memory, which is the basic principle of digital memory devices. It was.

The first memory devices using ferroelectrics were made of bulk materials, and their size and operating voltage were not suitable for integrating memory devices, so they were excluded from active research until a few years ago. However, with the recent development of thin film formation technologies such as sol-gel, sputtering, and metal organic chemical vapor deposition, it has become possible to thin ferroelectric materials such as PZT. . Therefore, researches for applying ferroelectrics to memory devices are being actively conducted and commercially available on a limited basis.

A typical form of a memory device having a ferroelectric film is one in which a ferroelectric film is used as one component of the gate stacks 4 and 5 formed on the silicon substrate 2 as shown in cross section in FIG. The ferroelectric film 4 and the metal layer 5 are sequentially stacked on the silicon substrate 2, and a conductive impurity layer 6 is formed around these laminates to form one transistor. As described above, the ferroelectric film forms a metal-ferroelectric-semiconductor (MFS) structure with a metal and a silicon substrate in the gate region of the transistor.

There are two main methods for manufacturing a memory device using a ferroelectric film. One is to manufacture a capacitor using ferroelectrics and use transistors to read and write signals in two directions stored in the capacitor, so-called one transistor and one capacitor (1T / 1C) or two transistors and two capacitors ( 2T / 2C). Such a memory device is collectively referred to as a ferroelectric RAM (hereinafter referred to as FRAM), and basically has a basic concept corresponding to the operation principle of the dynamic RAM. Of course, unlike DRAM, it is a nonvolatile memory that does not need regular refresh and does not erase stored data even when power is not supplied.

However, since the device uses the inversion and non-inversion of the spontaneous polarization stored in the capacitor, it is erased when the stored information is read once. Destructive Read Out (hereinafter referred to as DRO).

On the other hand, there is a method of reading stored information without destroying it, so-called nondestructive read out (hereinafter referred to as NDRO) type ferroelectric memory device. Such a device basically forms a ferroelectric gate capacitor on the gate or gate electrode of the transistor, and depending on the spontaneous polarization direction of the ferroelectric gate capacitor, the presence of a channel formed on the surface of the substrate under the gate oxide is determined. Such a memory device has an advantage in integrated screens because it forms a capacitor on a single transistor without forming a separate capacitor as compared to a conventional DRAM or FRAM. However, additional transistors, such as access or select transistors, are required to select a particular cell for random access operations, such as DRAM. This type of NDRO type ferroelectric memory device is collectively referred to as a ferroelectric floating gate RAM, that is, FFRAM.

FFRAM has several advantages over nonvolatile memory such as flash memory using conventional tunneling electrons. First, the flash memory has a write count of 10 ⁵ -10 ^{6 due} to deterioration of the tunneling oxide film, whereas FFRAM is ferro. Much more than this because of electric spontaneous polarization. If platinum is used as the electrode of the capacitor, which is a representative precious metal currently used, the number of writes is about 10 ⁹ despite the fatigue problem. Furthermore, when the electrode of the capacitor is replaced with an oxide conductor, the number of recordings is reported to be 10 ¹⁴ -10 ¹⁵ . In addition, the FFRAM can adjust the formation thickness of the ferroelectric thin film to lower the coercive voltage, that is, the voltage required to invert the spontaneous polarization of the ferroelectric. That is, the operation start voltage of the FFRAM can be lowered to about 3V to 5V. Therefore, low voltage operation is possible. In addition, the polarization inversion time of the FFRAM is much faster (about 10 nanoseconds) than the time when the flash memory tunnels electrons through the gate oxide film. Thus, FFRAM enables the implementation of nonvolatile, non-destructive memory devices capable of low voltage high speed operation.

The problem encountered in implementing FFRAM is that PZT, which is used as a ferroelectric, causes severe chemical reactions or interdiffusion with a material containing silicon, such as a substrate or a silicon oxide film, making the manufacturing process extremely difficult.

Recently, Rohm of Japan has found that iridium oxide (IrO ₂ ) exhibits excellent properties as an electrode material for capacitors using PZT as a ferroelectric. Based on this, various methods for practical application of FFRAM have been proposed. One of them is a US patent (Application No. 5,345,414) entitled SEMICONDUCTOR MEMORY DEVICE HAVING FERRO ELECTRIC FILM, filed by Nakamura et al., Which is related to the circuit design of FFRAM. In this patent, one ferroelectric transistor is used as the basis of a memory cell. In addition, one write and erase transistor and one read transistor are provided to drive the transistor. As a result, one memory cell is composed of three transistors.

Another example of the prior art of constructing a ferroelectric transistor as the basis of a memory cell can be found in a domestic patent (application number: 96-29878). The patent uses a ferroelectric transistor as the basis of a memory cell, and additionally includes an access transistor and one drive line for reading a signal to drive the transistor. Implementing memory cells with drive lines can simplify circuitry and reduce chip area compared to US Pat. No. 5,345,414.

A semiconductor device having a conventional ferroelectric film having a gate stack of MFS type in a gate region as shown in FIG. 1 and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

First, a semiconductor device having a gate stack of the MFS type according to the prior art will be described with reference to FIGS. 2 and 3.

FIG. 2 is a plan view of a part of a semiconductor device structure having a ferroelectric film on a gate region in a conventional MFS form, and FIG. 3 is a cross-sectional view taken along the II-II direction of FIG.

2 and 3 illustrate an arrangement of two first memory cells 210A and first memory cells 210C that are adjacent to each other in a row. All components related to the first memory cell 210A are denoted by an uppercase letter A in English. All components related to the second memory cell 210C are indicated by an uppercase letter C in English. Of those components, those marked with the same number in uppercase letters have the same function.

Specifically, an active region 228 separated by the field oxide film 221 is formed near the surface of the P-type silicon substrate 220. N-type impurity diffusion layers 222A, 222C, and 232 are formed in the active region 228 at predetermined intervals. Adjacent memory cells 210A and 210C share the N-type impurity diffusion layer 232. The memory cells 210A and 210C are arranged to be equal to each other in an array. Therefore, among these, the memory cell indicated by reference numeral 210A is selected and described.

A gate oxide film 233A, a gate electrode 223A, and a layer insulating film 224A are sequentially formed between the N-type impurity diffusion layers 222A and 232 on the semiconductor substrate 220, and are formed in contact with the impurity diffusion layer 222A. It is. A ferroelectric gate film 225A extending from the layer insulating film 224A to the surface of the semiconductor substrate 220 is formed in contact with the diffusion layer 232. A conductive thin film 236A is formed on the ferroelectric gate film 225A. The gate electrode 223A extends in an arbitrary direction and acts as a reading word line (hereinafter referred to as RWL1).

A semiconductor film 227A is formed in contact with one end of the conductive thin film 226A on the gate electrode 223A, and the semiconductor film 227A extends to the field oxide film 221. Further, the semiconductor film 227A extends in the form of a belt or a band on the field oxide film 221. The band-shaped portion of the semiconductor thin film extending on the field oxide film 221 is used as an erasing word line (hereinafter referred to as WEWL1).

A sidewall 247 and an insulating film 248 formed of an insulating material are formed between the semiconductor thin film 227A and the gate electrode 223A and between the semiconductor thin film 227A and the N-type impurity diffusion layer 222A. The semiconductor thin film 227A is composed of one N-channel metal oxide semiconductor thin film transistor (hereinafter referred to as MOSTFT) 213A serving as a writing and erasing transistor.

Impurities are selectively injected into the conductive thin film 226A. A channel region 235A is prepared on the N-type diffusion layer 222A. The drain region 236A and the source region 237A are in contact with both sides of the channel region. In this arrangement, the presence of the channel in the channel region 235A may be controlled by adjusting the potential of the N-type impurity diffusion layer 222A.

The N-type impurity diffusion layer 222A may serve as a gate of the MOSTFT 213A. As illustrated in FIG. 2, the N-type impurity diffusion layer 222A is connected to the first bit line BL1 in the contact hole 239A.

At the position where the gate electrode 223A is formed, one inversion layer may appear or disappear on the surface of the substrate 220 according to the voltage applied to the gate electrode 223A. That is, an N-channel metal oxide semiconductor field effect transistor (hereinafter referred to as a MOSFET) 212A corresponding to a read transistor is formed in one region where the gate electrode 223A is formed. In addition, two kinds of stable states in which an inversion layer appears or disappears on the substrate 220 depending on the polarization of the ferroelectric gate film 225A at the position where the ferroelectric gate film 225A is in contact with the substrate 220. There can be.

Polarization of the ferroelectric gate film 225A may be inverted by a predetermined value or by applying a larger voltage between the conductive thin film 226A and the substrate 220. Therefore, an N-channel metal ferroelectric semiconductor field effect transistor (hereinafter referred to as MFSEFT) 211A is said to be formed in the area where the ferroelectric gate film 225A is in contact with the substrate 220. Can be. The MFSFET functions like a field effect transistor for storage.

In FIG. 3, reference numerals 230 and 231 denote interlayer insulating films and surface protection films, respectively.

Subsequently, a method of manufacturing a semiconductor memory device having such a component will be described.

4 to 23 are diagrams illustrating a method of manufacturing a semiconductor memory device according to the prior art, in which stage a thin oxide film 233 is grown on a front surface of a p-type silicon substrate 220 as shown in FIG. 4. Let's do it. Subsequently, as illustrated in FIG. 5, a silicon nitride film 245 is formed in a region corresponding to the active region on the oxide film 233. By oxidizing the resultant product of FIG. 5, the oxide film 233 is further grown in a region where the silicon nitride film 245 is not formed. As a result, as shown in FIG. 6, a field oxide film 221 is formed on the substrate 220. In this way, the active region is separated by LOCOS (Local Oxidation of Silicon).

Next, the silicon nitride film 245 is removed. As shown in FIG. 7, the metal film 223 and the insulating film 224 are sequentially formed on the entire surface of the resultant product of FIG. 6. 8, the oxide film 233, the metal film 223, and the insulating film 224 are sequentially patterned to form the gate oxide film 233A, the gate electrode 223A, and the layer insulating film 224A. The N-type impurity diffusion layer 222A can be formed in a self-aligned manner by implanting ions into the entire surface of the resultant using a stack 249 composed of the gate oxide film 233A, the gate electrode 223A, and the layer insulating film 224A as a mask. Can be. In this case, a suitable mask is formed in the region opposite the N-type impurity diffusion layer 222A and in contact with the stack 249 to prevent ions from being implanted.

The layer insulating film 224A is formed on the gate electrode 223A because the polarization of the ferroelectric gate film 225A formed in a subsequent step is prevented from being changed by the voltage applied to the gate electrode 223A. . Therefore, the layer insulating film 224A uses a material having a low dielectric constant, such as a silicon oxide film.

Thereafter, as shown in FIG. 9, the ferroelectric film 225 and the conductive thin film 226 are sequentially formed on the entire surface of the resultant product of FIG. 8. As shown in FIG. 20, the ferroelectric film 225 and the conductive thin film 226 are patterned. As a result, a conductive thin film 226A is formed extending from the ferroelectric gate film 225A and the stack 249 in a direction opposite to the N-type impurity diffusion layer 222A. A portion of the ferroelectric gate film 225A is in contact with the substrate 220.

The ferroelectric gate film 225A may be formed using a ferroelectric material such as PZT (Pb (Zr, Ti) O ₃ ). However, PZT is difficult to achieve a good alignment with the silicon layer. Therefore, an interlayer insulating film is usually formed between the ferroelectric gate film 225A and the substrate 220. As the interlayer insulating film, CaF ₂ , SrF ₂ , or a fluoride having a similar structure may be used. In addition to PZT, suitable materials for the ferroelectric membrane 225 include ABO ₃ type perovskite structures (where A and B are metal elements) such as PLZT, PTO, BTO and other ABO type ₃ ferroelectric materials. Can be. Alternatively, it is not such an ABO type ₃ ferroelectric material but a halide such as BaMgF ₄ , NaCaF ₃ , K ₂ ZnCl ₄ , and a chalcogenide such as Zn _1-x Cd _x Te, GeTe, Sn ₂ P ₂ S _6, etc. (chalcogenides) can also be used.

The patterning of the ferroelectric gate film 225A can be performed by wet etching. However, it can also be performed by dry etching such as ion milling, reactive ion beam etching (RIBE), or reactive ion etching.

After the ferroelectric gate film 225A and the conductive thin film 226A are formed, the N-type impurity diffusion region 232 is formed in a self-alignment manner as a mask. This result is shown in FIG.

In this state, the silicon oxide film 246 is laminated on the entire surface of the resultant and then etched back. As a result, as shown in FIG. 21, sidewalls 247 are formed at both sides of the stack 249 formed between the N-type impurity diffusion regions 222A and 232.

Subsequently, as illustrated in FIG. 22, the substrate 220 is thermally oxidized to form an insulating film 248 covering the exposed region, and then patterned to one end of the conductive thin film 226A formed on the gate electrode 223A. And a semiconductor thin film 213A which is in contact with and extends to the area on the field oxide film 221. The semiconductor thin film 213A is formed using polysilicon, amorphous silicon, or the like.

In the semiconductor thin film 213A, the P-type impurity is implanted into one region on the N-type impurity diffusion layer 222A to define the channel region 235A. N-type impurities are implanted into the remaining regions to form drain and source regions 236A and 237A.

In this state, as shown in FIG. 23, a layer insulating film 230 is formed on the entire surface of the resultant product of FIG. 22. The layer insulating film 230 is formed of Phospo-Silicate Glass (PSG) or Boron-doped Phospho-Silicate Glass (BPSG) film. Next, although not shown in FIG. 23, other elements may be formed from the contact hole 239A as shown in FIG. 2. The aluminum wiring and the like of the bit line BL1 are formed. Subsequently, a protective film 231 is formed on the entire surface of the resultant product.

In the conventional semiconductor device having a ferroelectric film in the MFS form as described above, at least two transistors per unit memory cell are constituted and arranged adjacent to each other on a substrate. This conventional technology is not advantageous in terms of integration compared to conventional DRAMs in which a memory cell is composed of one transistor and one capacitor, but in this MFS structure, a diffusion reaction between a silicon substrate and a ferroelectric film and a process of stacking a ferroelectric film Due to the compositional change of the oxide film or the ferroelectric film formed on the silicon substrate at the interface side of the silicon substrate, the characteristics of the ferroelectric film may sometimes deteriorate, resulting in a high voltage and a leakage current required for the reverse polarization of the ferroelectric film.

In order to overcome the above-mentioned disadvantages when the ferroelectric film is applied in the MFS form, the buffer layer is formed of an insulating material layer between the ferroelectric film F and the silicon substrate S in the MFS form without using the ferroelectric film in the MFS form. It is widely used in the form of MFIS (Metal-Ferroelectric-Insulator-Semiconductor) in which (buffer layer) is added.

By the way, in the MFIS form, a material widely used as the insulating material layer (I) may be a silicon oxide film (SiO ₂ ) or a nitride film (Si ₃ N ₄ ). Since the silicon oxide film or the nitride film has a low dielectric constant, the residual polarization ( The driving voltage of the FRAM required for remnant polarization and polarization inversion increases, making low voltage driving impossible. In addition, in order to deposit a good ferroelectric film F in the MFIS form, the crystallinity of the lower insulating film I must be excellent. That is, the insulating film must achieve single crystal growth.

In the case of stacking a polycrystalline insulating material layer or a polycrystalline metal / insulating material layer on a silicon substrate and then laminating a polycrystalline ferroelectric film thereon, the epitaxial layer is directly deposited on a single crystal silicon substrate (eg, a single crystal SrTiO ₃ substrate). Residual polarization, coercive force, retention, fatigue, or imprint characteristics are exhibited compared to the case of stacking a single crystal ferroelectric film by the method.

Therefore, there is a growing interest in the buffer layer formed on the silicon substrate to grow the ferroelectric film into a single crystal, and a recent study on this has been conducted on several specific material layers. Among the representative materials, Y ₂ O ₃ and cesium oxide ( CeO ₂ ) and STO (SrTiO ₃ ). Crystallographically, these materials are all similar to or regular multiples of lattice constants with silicon. Thus, the mismatch of the lattice is small between the two materials, so a good hetero epitaxy is expected on the silicon substrate, but these materials are perpendicular to the (110) direction instead of the (100) direction in the (100) crystal plane of silicon. Crystals grew in the normal direction. This fact can be easily seen with reference to FIG. 14 showing the X-ray diffraction results of the growth of one of these materials, Y ₂ O ₃ on a silicon substrate. In FIG. 14, the horizontal axis represents the incident angle of X-rays, and the vertical axis represents the intensity of diffracted X-rays. Referring to FIG. 14, reference numeral 10 denotes the intensity of X-ray diffracted by the (110) crystal plane of Y ₂ O ₃ , which is much stronger than that of the (100) crystal plane of silicon (8). . These materials can be grown in one direction (110) as shown in FIG. 14 but have multiple in-plane orientations, resulting in polycrystalline growth rather than single crystals. This fact can be seen in FIG. 15, which shows the diffraction intensity when X-rays are scattered on the (211) crystal plane of Y ₂ O ₃ grown in the (110) direction. It can be seen that there are three axis symmetry, not one. Thus it is clear that these materials have in-plane orientations.

As described above, in a semiconductor device having a ferroelectric film according to the related art and a method of manufacturing the same, the ferroelectric film is used in the MFIS form, and the material layers used as the buffer layer to form the single crystal ferroelectric film do not grow in the preferred direction (100) ( Direction 110). Therefore, the ferroelectric film whose quality of the crystal state is determined according to the crystal state of these buffer layers does not grow in the (100) direction. As a result, in a semiconductor device having a ferroelectric film and a method of manufacturing the same, the characteristics of the semiconductor device due to defects in the ferroelectric film are deteriorated, and pinning occurs during polarization inversion of the domain of the ferroelectric film.

Accordingly, in order to solve the problems of the prior art, the object of the present invention is to provide a semiconductor device having a double buffer layer having a crystal direction in the (100) direction.

Another object of the present invention is to provide a method of manufacturing the semiconductor device.

1 is a cross-sectional view of a semiconductor device having a ferroelectric film according to the prior art.

2 to 13 are steps illustrating a method of manufacturing a semiconductor device having a gate stack of a metal ferroelectric semiconductor (MFS) according to the prior art.

14 is a view showing the intensity according to the incident angle of the diffracted X-rays.

15 is a graph showing X-ray diffraction intensity of a Y ₂ 0 ₃ film having a crystal direction of (211).

16 is a cross-sectional view of a semiconductor device including a ferroelectric film according to the first embodiment of the present invention.

17 is a cross-sectional view of a semiconductor device having a ferroelectric film according to a second embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

40, 56: single crystal silicon substrate. 42, 58: first buffer layer.

44, 60: second buffer layer

46, 64: ferroelectric film. 48: electrode.

62, 66: first and second electrodes.

In order to achieve the above object, a semiconductor device having a ferroelectric film according to a first embodiment of the present invention comprises a single crystal first buffer layer having a crystal direction of (100) on a single crystal silicon substrate having a crystal direction of (100); A single crystal second buffer layer having a crystal direction (100) in the single crystal first buffer layer; A single crystal ferroelectric film having a crystal direction of (100) on the single crystal second buffer layer; And an electrode on the ferroelectric film.

The first buffer layer is a zirconium oxide layer. The zirconium oxide layer is a zirconium dioxide film Zr0 ₂ .

The second buffer layer is any one material layer selected from the group consisting of Y ₂ O ₃ , cesium oxide (CeO ₂ ), and STO (SrTiO ₃ ).

The ferroelectric film is a PZT film.

In order to achieve the above object, a semiconductor device having a ferroelectric film according to a second embodiment of the present invention includes a single crystal first buffer layer having a crystal direction in the (100) direction on a single crystal silicon substrate having the crystal direction (100); A single crystal second buffer layer having a crystal direction (100) in the single crystal first buffer layer; A first electrode on the single crystal second buffer layer; A single crystal ferroelectric film having a crystal direction of (100) on the single crystal first electrode; And a second electrode on the single crystal ferroelectric film.

The first buffer layer is a zirconium oxide layer, respectively. The zirconium oxide layer is a ZrO ₂ film.

The second buffer layer is any one material layer selected from the group consisting of Y ₂ O ₃ , cesium oxide (CeO ₂ ), and STO (SrTiO ₃ ).

The ferroelectric film is a PZT film.

The ferroelectric film may be a multilayer formed of a plurality of ferroelectric films.

The first electrode is a lower electrode of the gate capacitor and is a material film of Pt, SrCa _lx , Ru _X O ₃ , or LaSrCoO ₃ .

The second electrode is an upper electrode of the gate capacitor.

In order to achieve the above another object, the manufacturing method of a semiconductor device having a ferroelectric film according to the first embodiment of the present invention

(a) depositing a first epitaxial layer on the semiconductor substrate such that the crystal direction is (100); (b) depositing a second epitaxial layer on the first epitaxial layer such that the crystal direction is (100); (c) depositing a ferroelectric film on the second epitaxial layer such that the crystal direction is (100); And (d) forming an electrode on the ferroelectric film.

The first epitaxial layer is laminated with a zirconium oxide layer as a first buffer layer for the ferroelectric film.

The forming of the zirconium oxide film may include: (a1) removing the native oxide film from the entire surface of the silicon substrate having a crystal direction of (100); (a2) in-situ cleaning the silicon substrate from which the natural oxide film is removed in a lamination chamber; (a3) forming a zirconium (Zr) film on the substrate; And (a4) forming a zirconium oxide film on the substrate with a predetermined thickness or less.

Chemical vapor deposition (CVD) or physical vapor deposition (PVD) is used to form the second epitaxial layer.

The second epitaxial layer is selected from the group consisting of a Y ₂ O ₃ layer, a cesium oxide layer (CeO ₂ ), and a STO (SrTiO ₃ ) layer as either the CVD or PCVD method as the second buffer layer for the ferroelectric film. It is formed by stacking any one material layer.

The ferroelectric film may be formed in a single layer or in multiple layers. When the ferroelectric film is formed as a single layer, the ferroelectric film may be laminated with a PZT film.

In order to achieve the above object, a method of manufacturing a semiconductor device having a ferroelectric film according to a second embodiment of the present invention comprises the steps of stacking a first epitaxial layer on the semiconductor substrate so that the crystal direction is (100); Stacking a second epitaxial layer on the first epitaxial layer such that a crystal direction is (100); Forming a first electrode on the second epitaxial layer; Stacking a ferroelectric film on the first electrode such that the crystal direction is (100); And forming a second electrode on the ferroelectric film.

The first epitaxial layer is laminated with a zirconium oxide layer as a first buffer layer for the ferroelectric film.

The forming of the zirconium oxide film may include: (a1) removing the native oxide film from the entire surface of the silicon substrate having a crystal direction of (100); (a2) in-situ cleaning the silicon substrate from which the natural oxide film is removed in a lamination chamber; (a3) forming a zirconium (Zr) film on the substrate; And (a4) forming a zirconium oxide film on the substrate with a predetermined thickness or less.

Chemical vapor deposition (CVD) or physical vapor deposition (PVD) is used to form the second epitaxial layer.

The second epitaxial layer is formed of one material layer selected from the group consisting of Y ₂ O ₃ , cesium oxide (CeO ₂ ), and STO (SrTiO ₃ ) as a second buffer layer for the ferroelectric film.

The first electrode is used as a lower electrode of the gate capacitor, and is formed of any one material layer of Pt, SrCa _lx , Ru _X O ₃ , or LaSrCoO ₃ .

The ferroelectric film may be formed in a single layer or in multiple layers. When the ferroelectric film is formed as a single layer, the ferroelectric film may be laminated with a PZT film.

The second electrode is used as a lower electrode of the capacitor.

According to the present invention, the ferroelectric film can be grown in the same direction as the crystallographic direction of the lower film to form a high-quality ferroelectric film. Therefore, it is possible to prevent the deterioration of characteristics due to the defect of the ferroelectric and the pinning phenomenon at the time of polarization changeover.

Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

16 is a cross-sectional view of a semiconductor device having a ferroelectric film according to a first embodiment of the present invention, and FIG. 17 is a cross-sectional view of a semiconductor device having a ferroelectric film according to a second embodiment of the present invention.

FIG. 16 is a cross-sectional view of a semiconductor device having a MFIS shape. Referring to this, there is a p-type semiconductor substrate 40 divided into an active region and a field region, and a predetermined interval is provided in a part of the active region of the semiconductor substrate 40. There is an impurity layer 50 composed of a conductive impurity of a different form from the substrate. On the active region of the substrate 40, which is in contact with the impurity layer 50, there is a first buffer layer 42 in contact with both of the impurity layer 50, and an upper surface of the first buffer layer 42. 2 buffer layer 44 is in contact. The semiconductor substrate 40 is a single crystal silicon substrate having a crystal direction of (100). The first buffer layer 42 is also a single crystal zirconium oxide layer as a single crystal material layer having the same (100) direction as the silicon (Si) crystal direction of the semiconductor substrate 40. Specifically, a single crystal zirconium oxide film (ZrO ₂ ) in the (100) direction whose lattice shape is tetragonal. In addition, the second buffer layer 44 is a Y ₂ O ₃ layer as a single crystal material layer having a crystal direction of (100). The second buffer layer 44 may be any one material layer selected from among the single crystal CeO ₂ layer or the single crystal STO layer having the same crystal direction in addition to the Y ₂ O ₃ layer.

Subsequently, a single crystal ferroelectric film 46 having a crystal direction of (100) is in contact with the second buffer layer 44, and an electrode 48 is in contact with the single crystal ferroelectric film 46. The single crystal ferroelectric film 46 is a PZT film.

In the semiconductor device according to the first embodiment of the present invention, the semiconductor substrate is a single crystal silicon semiconductor substrate 40 into which P-type impurities are injected. However, this is only one example and may be a single crystal silicon substrate into which other types of impurities are injected. have.

17, a semiconductor device including a ferroelectric film according to a second embodiment of the present invention will be described. The semiconductor device according to the second embodiment of the present invention relates to a semiconductor device of the MFMIS type. Specifically, the semiconductor device according to the second embodiment of the present invention is provided in a part of the active region of the single crystal silicon semiconductor substrate 56 having the P-type and the crystal direction (100). There is an impurity layer 68 composed of a conductive impurity of a different form from the substrate 56 at intervals of. On the active region of the substrate 56 that is in contact with the impurity layer 68, the first buffer layer 58, which is in contact with both of the impurity layer 68, is in contact with the upper surface of the first buffer layer 58. The second buffer layer 60 is in contact with each other.

The first buffer layer 58 is a single crystal zirconium oxide layer as a single crystal material layer having the same (100) direction as the silicon (Si) crystal direction of the semiconductor substrate 56. In other words, the first buffer layer 58 is a single crystal zirconium oxide film (ZrO ₂ ) having a tetragonal lattice shape.

The second buffer layer 60 is a single crystal Y ₂ O ₃ layer having a (100) direction in which the crystal direction is the same as the crystal direction of the first buffer layer 42. The second buffer layer 44 may be any material layer selected from a single crystal CeO ₂ layer or a single crystal STO layer in addition to the single crystal Y ₂ O ₃ layer.

The first electrode 62 is in contact with the entire surface on the second buffer layer 60. The ferroelectric film 64 is in contact with the entire surface on the first electrode 62, and the second electrode 66 is in contact with the ferroelectric film 64.

The first and second electrodes 62 and 66 are lower and upper electrodes of the capacitor. The first electrode 62 is any one material film selected from the group consisting of a Pt film, an SrCa _lx film, a Ru _X O ₃ film, and a LaSrCoO ₃ film.

Next, a method of manufacturing a semiconductor device having the ferroelectric films according to the first and second embodiments of the present invention will be described. For this purpose, reference is again made to FIGS. 16 and 17. First, referring to FIG. 16, in the method of manufacturing the ferroelectric semiconductor device according to the first embodiment of the present invention, a P-type single crystal silicon substrate 40 having a crystal direction of 100 is prepared as a first step. Subsequently, the single crystal silicon substrate 40 is divided into an active region and a field region, and then a field oxide film (not shown) is formed in the field region for device isolation.

A single crystal first buffer layer 42 having a crystal direction of 100 is formed as an epitaxial layer on the active region of the silicon substrate 40. The first buffer layer 42 is formed of a single crystal zirconium oxide layer in the (100) direction, for example, zirconium dioxide oxide (ZrO ₂ ).

Zirconium dioxide (ZrO ₂ ) is an insulating material having a relatively large dielectric constant (about 18) and a relatively wide energy gap of about 5 electron volts (eV). Therefore, ZrO ₂ has the potential to be used as a storage capacitor in DRAM and also as an insulating layer in silicon-on-insulator (SOI) devices.

The process of forming the zirconium oxide layer proceeds as follows.

First, a single crystal silicon substrate in the (100) direction is prepared and wet-etched using dilute hydrofluoric acid (HF) to remove the native oxide film formed on the surface of the silicon substrate. The wet etched single crystal silicon substrate 40 is then in situ cleaned in a deposition chamber. The cleaning may be performed at a temperature range of 850 ° C. or higher, or under a pressure of 10 ⁻⁸ torr or less, or by using a thermal cleaning method or hydrogen radical. Use

Subsequently, vacuum deposition techniques such as evaporation, sputtering, laser ablation, molecular beam epitaxy, or ICBD are used, and the pressure is reduced from 5 kPa to 10 ^-6 torr or less. A zirconium (Zr) film is formed on the cleaned single crystal silicon substrate 40 to a thickness of about 10 GPa. Subsequently, a ZrO ₂ film is formed on the zirconium film formed by forming the zirconium film while flowing oxygen gas in the stacking chamber. In view of the process conditions for forming the ZrO ₂ film, the pressure in the deposition chamber is maintained at a value between 10 ⁻³ torr and 10 ⁻⁶ torr. The thickness of the ZrO ₂ is formed to a thickness of 100 kPa or less.

It is possible to form a single crystal zirconium oxide layer having a crystal direction of (100) on the single crystal silicon substrate 40 having the crystal direction of (100) .Refer to Evaluation of crystalline quality of zirconium dioxide films on silicon by means of ion. beam channeling: J. Appl. Phys., 63, No. 2,15 January 1988).

The ZrO ₂ lattice structure has a lattice structure and an in-plane direction in the (100) direction when deposited on a monocrystalline silicon substrate in the (100) direction at a temperature of 700 ° C. It is deposited into a single crystal layer.

However, since a plane of the ZrO ₂ lattice having the tetragonal lattice structure is not square, a desired single-crystal ferroelectric film of desired quality is not formed when the ferroelectric film is directly formed thereon. Therefore, before forming the ferroelectric layer on the first buffer layer 42 formed of the ZrO ₂ layer having the tetragonal lattice structure, the second buffer layer 44 capable of ensuring the single crystallinity of the ferroelectric layer is formed. As the second buffer layer 44, when any one material layer selected from the group consisting of a Y ₂ O ₃ layer, a CeO ₂ layer, and an STO layer having a cubic lattice structure is used, the ZrO ₂ layer, which is the first buffer layer 42, is used. The second buffer layer 44 may be formed as a single crystal layer having a (100) direction thereon. The second buffer layer 44 may be formed by a CVD method or a PVD method.

The formation of the second buffer layer 44 on the first buffer layer 42 without directly forming the single crystal silicon substrate 40 in the (100) direction is the same as described above in the description of the related art. When the second buffer layer 44 is formed of a material layer selected from a group consisting of a Y ₂ O ₃ layer, a CeO ₂ layer, and an STO layer on the single crystal silicon substrate 40 in the direction of the second buffer layer 44 ( This is because when the ferroelectric film is formed thereon without being grown in the 100) direction and growing in the (110) direction, it cannot have the (100) direction.

The _second buffer layer 44 is a material layer selected from the group consisting of a Y ₂ O ₃ layer, a CeO ₂ layer, and an STO layer (particularly, a Y ₂ O ₃ layer) on the first buffer layer 42 that is the ZrO ₂ layer. When forming a second buffer layer 44 is formed on the first buffer layer 42 as a single crystal material layer in the (100) direction, which is referred to as reference 2 (Growth of Buffer Layers on Si Substrate for High- _Tc Superconducting) Thin Filmsby Keiizo et.al .: Japanese Journal of Applied Physics Vol. 30, No. 5. May, 1991. pp 934-938.

After forming the double buffer layer composed of the first and second buffer layers 42 and 44 as described above, if the ferroelectric film 46 is formed on the second buffer layer 44, the second buffer layer 44 is formed. Since it has a normal direction in this (100) direction, a single crystal ferroelectric film having a crystal direction excellent in polarization characteristics in the (100) direction can be formed. The ferroelectric film 46 is formed of a single crystal PZT film. The ferroelectric film 46 may be formed in multiple layers without forming a single layer.

Subsequently, an electrode 48 is formed of a conductive material layer on the single crystal ferroelectric film 46. The electrode 48 acts as a gate electrode. Subsequently, a conductive impurity layer opposite to the impurity implanted into the substrate 40 is injected into the exposed active region of the substrate to contact the first buffer layer 42 in the active region of the substrate 40. 68). The conductive impurity layer 68 is used as a source or a drain, and a ferroelectric gate transistor on the substrate 40 together with a gate stack composed of first to second buffer layers, ferroelectric films, and electrodes sequentially formed on the active region. To form.

Next, with reference to FIG. 17, the manufacturing method of the semiconductor device provided with the single-crystal ferroelectric film by 2nd Example of this invention is demonstrated in detail.

First, as in the first embodiment of the present invention, a single crystal silicon substrate 56 in the (100) direction is prepared by wet etching and in-situ cleaning in the stacking chamber. Subsequently, the single crystal silicon substrate 56 is divided into an active region and a field region, and then a field oxide film (not shown) is formed in the field region. A ferroelectric gate capacitor stack is formed on the active region at a predetermined distance from the field oxide film. Specifically, a first buffer layer 58 is formed as the first epitaxial layer on the active region. The first buffer layer 58 is formed of a zirconium oxide layer having a crystal direction of (100), particularly a ZrO ₂ film having a tetragonal lattice structure. The reason why the first buffer layer 58 is formed on the substrate 56 and the zirconium oxide layer in the (100) direction may be formed on the substrate 56 are described in the first embodiment of the present invention. There is a bar.

The process of forming the ZrO ₂ film is also the same as described in the first embodiment.

On the first buffer layer 58, a single crystal second buffer layer 60 is grown as a second epitaxial layer by growing a material layer selected from a group consisting of a Y ₂ O ₃ layer, a CeO ₂ layer, and an STO layer in the (100) direction. To form. The single crystal second buffer layer 60 may be formed by a CVD method or a PVD method.

Subsequently, a first electrode 62 serving as a lower electrode of the capacitor is formed on the second buffer layer 60. The first electrode 62 is formed of a material film selected from a Pt film, an SrCa _lx film, a Ru _X O ₃ film, or a LaSrCoO ₃ film. Subsequently, a single crystal ferroelectric film 64 in the (100) direction is formed on the first electrode 62. The ferroelectric film 64 is formed of a single crystal PZT film. The ferroelectric film 64 may be formed in a single layer or a plurality of layers. The second electrode 66 is formed on the ferroelectric film 64 as an upper electrode of the capacitor.

Thus, on the active region of the single crystal silicon substrate 56 in the (100) direction, a ferroelectric gate capacitor composed of the first and second buffer layers as the epitaxial layer, the first electrode, the ferroelectric film, and the second electrode, that is, an MFMIS structure A gate stack of is formed.

Next, conductive impurity opposite to the conductive impurity injected into the single crystal silicon substrate 56 is implanted into the active region where the gate stack of the MFMIS structure is not formed, thereby contacting the gate entire layer of the MFMIS structure. Form layer 68. The conductive impurity layer 68 forms a transistor on the single crystal silicon substrate 56 together with the gate stack of the MFMIS structure as a source or a drain. In other words, a transistor having a ferroelectric gate capacitor is formed.

As described above, the present invention provides a first buffer layer, a Y ₂ O ₃ layer, and a CeO ₂ layer as a first epitaxial layer formed of a single crystal ZrO ₂ film having a crystal direction of (100) on a single crystal silicon substrate having a crystal direction of (100). And a material layer selected from the group consisting of STO layers is grown in the (100) direction to form a second buffer layer 60 as the second epitaxial layer, and then a ferroelectric film is formed thereon to form a ferroelectric having a crystal direction of (100). A film can be formed.

Therefore, it is possible to prevent the deterioration of characteristics due to the defect of the ferroelectric film, and to improve the polarization characteristics, thereby preventing the pinning phenomenon in the domain of the ferroelectric film during polarization inversion. In addition, an ideal ferroelectric memory device capable of high-speed operation at a low driving voltage may be implemented by adjusting a growing crystal direction of the ferroelectric film.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical scope of the present invention.

Claims (31)

A single crystal first buffer layer having a crystal direction of (100) on a single crystal silicon substrate having a crystal direction of (100); A single crystal second buffer layer having a crystal direction (100) in the single crystal first buffer layer; A single crystal ferroelectric film having a crystal direction of (100) on the single crystal second buffer layer; And A semiconductor device comprising an electrode on the ferroelectric film The semiconductor device according to claim 1, wherein said single crystal first buffer layer is a zirconium oxide layer. The semiconductor device according to claim 2, wherein the zirconium oxide layer is ZrO ₂ whose crystal direction is in the (100) direction. The semiconductor device of claim 1, wherein the single crystal second buffer layer is any one material layer selected from the group consisting of a Y ₂ O ₃ layer, a CeO ₂ layer, and an STO layer having a crystal direction of (100). The semiconductor device according to claim 1, wherein the single crystal ferroelectric film is a PZT film whose crystal direction is (100). A single crystal first buffer layer having a crystal direction in the (100) direction on the single crystal silicon substrate having the crystal direction (100); A single crystal second buffer layer having a crystal direction (100) in the single crystal first buffer layer; A first electrode on the single crystal second buffer layer; A single crystal ferroelectric film having a crystal direction of (100) on the single crystal first electrode; And And a second electrode on the single crystal ferroelectric film. 7. The semiconductor device according to claim 6, wherein the first buffer layer is a single crystal zirconium oxide layer having a crystal direction of (100). The semiconductor device according to claim 7, wherein the zirconium oxide layer is single crystal ZrO ₂ . The semiconductor device according to claim 6, wherein the single crystal second buffer layer is any single crystal material layer selected from the group consisting of single crystal Y ₂ O ₃ , single crystal CeO _2, and single crystal STO having a crystal direction of (100). The semiconductor device according to claim 6, wherein the single crystal ferroelectric film is a single crystal PZT film having a crystal direction of (100). The semiconductor device according to claim 6, wherein the single crystal ferroelectric film is a multilayer. The semiconductor device according to claim 6, wherein the first electrode is a lower electrode of the gate capacitor and is a material film selected from a Pt film, an SrCa _lx film, a Ru _X O ₃ film, or a LaSrCoO ₃ film. (a) depositing a single crystal first epitaxial layer on the single crystal silicon substrate having a crystal direction of (100) so that the crystal direction is (100); (b) depositing a single crystal second epitaxial layer on the first epitaxial layer such that the crystal direction is (100); (c) depositing a single crystal ferroelectric film on the second epitaxial layer such that the crystal direction is (100); And (d) forming an electrode on the single crystal ferroelectric film. The method of manufacturing a semiconductor device according to claim 13, wherein said single crystal first epitaxial layer is formed of a zirconium oxide layer as a first buffer layer for said single crystal ferroelectric film. The method of claim 14, wherein the zirconium oxide layer (a1) removing the native oxide film from the entire surface of the silicon substrate having a crystal orientation of (100); (a2) in-situ cleaning the silicon substrate from which the natural oxide film is removed in a lamination chamber; (a3) forming a zirconium (Zr) film on the substrate; And (a4) A method of manufacturing a semiconductor device, comprising the step of forming a zirconium oxide film with a predetermined thickness on the zirconium film. The method of claim 15, wherein the substrate is wet etched to remove the native oxide film of the silicon substrate in the step (a1). The method of manufacturing a semiconductor device according to claim 15, wherein the in-situ cleaning in the step (a2) is performed by any one of thermal cleaning or a method using hydrogen radicals. 18. The method of manufacturing a semiconductor device according to claim 17, wherein any one of the above methods is performed at a temperature of 850 DEG C or higher and 10 ^-3 torr to 10 ^-6 torr. The method of manufacturing a semiconductor device according to claim 15, wherein the zirconium film of step (a3) is formed by vacuum deposition. The method of claim 19, wherein the zirconium film is formed by a vacuum deposition method of any one of evaporation, sputtering, laser ablation, MBE (Molecular Beam Epitaxy), ICBD method Method of manufacturing a semiconductor device. 21. The method of manufacturing a semiconductor device according to claim 20, wherein the vacuum deposition method of any one method is performed under a pressure of 10 ^-6 Torr or less. 20. The method of manufacturing a semiconductor device according to claim 19, wherein the zirconium is formed to a thickness of 5 kPa to 10 kPa. The method of manufacturing a semiconductor device according to claim 15, wherein the zirconium oxide film of step (a4) is formed by laminating zirconium on the zirconium film while oxygen is flowing in the stacking chamber. 24. The method of manufacturing a semiconductor device according to claim 23, wherein said zirconium oxide film is formed under a pressure between 10 ^-3 torr and 10 ^-6 torr. The semiconductor device manufacturing method according to claim 15 or 23, wherein the zirconium oxide film is formed to a thickness of 100 kPa or less. The method of manufacturing a semiconductor device according to claim 13, wherein said second epitaxial layer is formed by either CVD or PVD. 27. The group of claim 26, wherein the second epitaxial layer is composed of single crystal Y ₂ O ₃ , single crystal CeO _2, and single crystal STO having a crystal direction of (100) as a second buffer layer for the single crystal ferroelectric film in the (100) direction. A semiconductor device manufacturing method, characterized in that formed of any one of the selected single crystal material layer. The method of manufacturing a semiconductor device according to claim 13, wherein said single crystal ferroelectric film is formed in multiple layers. 29. The method of manufacturing a semiconductor device according to claim 13 or 28, wherein said single crystal ferroelectric film is formed of a PZT film. The method of claim 13, wherein the single crystal ferroelectric film of step (c) is formed on the first electrode after forming a first electrode on the second epitaxial layer. The semiconductor device according to claim 30, wherein the first electrode is formed of any one material film selected from the group consisting of a Pt film, an SrCa _lx film, a Ru _X O ₃ film, and a LaSrCoO ₃ film as a lower electrode of the capacitor. Manufacturing method.

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