JPH08330451A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To provide a new memory cell structure which uses the hetero junction of ferroelectric and semiconductor and provide a semiconductor storage device which allows nonvolatile storage, non-destructive reading, is small in size and capable of high integration. CONSTITUTION: A semiconductor storage device is provided with a hetero junction structure, where a PZT ferroelectric film 16 is sandwiched by two STO electrodes 13 and 15 formed of semiconductor film; an SFS diode, which controls current that flows to the hetero junction by polarization of the ferroelectric film 15, and a switch transistor, connected to the SFS diode, constitute the memory cell on an insulation layer 9 that covers the silicon substrate 1 whereupon the switch transistor is formed, a single crystal silicon layer 17 is grown from an opening provided at the part of the insulation layer 9, and on the single crystal silicon layer 17, a ferroelectric film 15 is epitaxially grown.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using a diode having a junction structure of a ferroelectric substance and a semiconductor.

[0002]

2. Description of the Related Art Conventionally, a method of controlling a current by utilizing a junction characteristic between a ferroelectric substance and a semiconductor has been studied.
As an example, as shown in FIG. 8, a remanent polarization of a ferroelectric substance induces a charge on a semiconductor surface, and a change in lateral conductivity of the charge in the semiconductor due to the polarization charge is used. This is a structure (MFS-FET) in which the gate insulating film of MIS (metal / insulator / semiconductor) FET is replaced with a ferroelectric film.
Therefore, the conductive state of the field effect transistor can be controlled by the residual polarization of the ferroelectric film, and in principle, it can be used as a nonvolatile memory.

However, there are various problems in utilizing the conductivity of the semiconductor surface in contact with the ferroelectric substance. One of them is the problem of diffusion of the elements constituting the ferroelectric substance into the semiconductor. Low-melting-point metals such as lead and bismuth are required to realize ferroelectricity, but these metals are extremely easy to diffuse into semiconductors such as silicon. Therefore, even if the ferroelectric film is formed at a low temperature, diffusion of these metals is inevitable near the semiconductor surface, and a large amount of impurity levels are formed. Further, since the ferroelectric substance and the semiconductor do not lattice match, a large amount of interface states are formed at the interface. Interface levels and impurity levels formed near the surface of these semiconductors act as carrier traps, and a large amount of carriers are injected and trapped even when an electric field is applied to invert the polarization of the ferroelectric substance. However, there is a problem that the semiconductor does not operate or the operation becomes very unstable.

As described above, the device utilizing the change in the conductivity of the junction interface between the semiconductor and the ferroelectric has a great difficulty in practical use for the above-mentioned reasons, and particularly, the silicon semiconductor and the ferroelectric. The reality is that there is no prospect of commercialization of a device that directly bonds to and.

In recent studies (40th Joint Lecture on Applied Physics 31a-GC-1 and 42nd Joint Lecture on Applied Physics 29a-D-9), vertical metal / ferroelectric Body-to-semiconductor (MFS) diodes with memory effect have been announced. In the MFS junction, as described above, charges are induced on the semiconductor surface due to the remanent polarization of the ferroelectric substance, and this charge forms a depletion layer or a charge storage layer, so that the barrier height of the semiconductor / ferroelectric junction is increased. Since it changes, the polarization state can be read as a change in resistance value through the junction.

In the MFS diode as well, it is necessary to reduce the level formed at the interface as much as possible. Therefore, it is desirable to use a single crystal or an epitaxially grown thin film as the semiconductor electrode and the ferroelectric film. Therefore, all of the MFS diodes known to date are made by using an oxide single crystal substrate such as strontium titanate or magnesium oxide, which is combined with a silicon semiconductor to produce a highly integrated semiconductor memory. Was impossible.

On the other hand, as another semiconductor device using a ferroelectric substance, a ferroelectric random access memory (F
RAM). This FRAM uses a metal electrode / ferroelectric film / metal electrode (MFM) capacitor as a charge storage element, and shows the polarization direction of the ferroelectric film when a voltage higher than a coercive electric field that can cause polarization reversal is applied. This is a semiconductor memory device having a structure in which a difference in current due to the difference is detected by a sense amplifier, and there is a great advantage that the stored contents can be retained even when the power is cut off.

However, in principle, since the polarization direction is reversed during writing and reading, the ferroelectric film deteriorates due to fatigue when the number of times of reversal increases, and there is a drawback that storage becomes impossible. In order to reduce the number of inversions, a normal D that is driven as a simple capacitor with a voltage below the coercive electric field that does not cause inversion at power input
Although it can be used in the RAM mode, in this case, another difficult problem arises in that it is necessary to reduce the leakage current of the capacitor with respect to the storage capacity.

In addition, recent literature (Physical Review Lett
ers, Vol.73, No.15, pp.2107-2110), using a MFM structure in which a semiconducting ferroelectric film is sandwiched between two different metal electrodes, the metal and the semiconducting ferroelectric are It has been reported that the current value in the Schottky junction with and changes with the polarization direction of the semiconducting ferroelectric. This phenomenon is shown in FIG.
Will be described below.

As shown in the potential diagram of FIG. 9A, a double Schottky junction with two kinds of metals having different work functions (each Schottky barrier height φM1
And φM2) semiconducting ferroelectric (assuming n-type semiconductor)
ΦM1 and φ even when there is no external bias voltage
A built-in potential equivalent to the difference of M2 is added. Therefore, the polarization characteristics of such a semiconducting ferroelectric are shown in FIG.
As shown in the polarization P-electric field E curve of (b), it becomes asymmetric due to the internal electric field. Therefore, the dielectric constant of the ferroelectric substance corresponding to the slope of the PE curve differs depending on the direction of the remanent polarization when the bias voltage is 0 (ε1 and ε).
2).

Since the potential profile generated on the semiconducting ferroelectric side of the Schottky barrier shown in FIG. 9A changes depending on the permittivity, when the permittivity changes depending on the remanent polarization direction, it is indicated by a solid line and a broken line. As described above, the thickness of the depletion layer changes. Therefore, when the Schottky barrier is thin, the tunnel current across the barrier changes depending on the direction of remanent polarization. By utilizing this change in the characteristics of the Schottky barrier, it can be used as a non-volatile memory.

However, since the height itself of the Schottky barrier does not change depending on the polarization direction, it is difficult to obtain a steep switch characteristic, and a built-in potential is added inside even when the bias voltage is 0. However, when remanent polarization occurs in the direction opposite to the built-in potential, there is a defect that the polarization is easily lost.

[0013]

As described above, various semiconductors such as the MFS transistor, the MFS diode, the charge storage device having the MFM structure, and the double Schottky structure of the MFM, which have conventionally used the ferroelectric film as the gate oxide film, have been used. Although the structure as a device is considered, each has a peculiar disadvantage, and becomes a big problem when using it as a non-volatile semiconductor memory device.

The present invention has been made in consideration of the above circumstances, and an object thereof is to realize a new memory cell structure utilizing a heterojunction between a ferroelectric substance and a semiconductor,
An object of the present invention is to provide a semiconductor memory device which has non-volatile memory contents and non-destructive characteristics at the time of reading, and is small in size and can be highly integrated.

[0015]

The gist of the present invention is to provide a vertical metal / ferroelectric / semiconductor (MFS) or semiconductor / ferroelectric / semiconductor (SF) on an insulating layer on a silicon substrate.
The purpose is to produce a diode having a memory function consisting of S) by epitaxial growth.

That is, the present invention has a heterojunction structure in which a ferroelectric film is sandwiched between two electrodes, at least one of which is a semiconductor film, and the current flowing through the heterojunction is controlled by polarization of the ferroelectric film. A semiconductor memory device comprising a memory cell including a diode and a switching transistor connected to the diode, wherein a part of the insulating layer is formed on an insulating layer covering a silicon substrate on which the switching transistor is formed. From the opening provided in (10
A 0) oriented silicon layer is grown, and the ferroelectric film is epitaxially grown on the (100) oriented silicon layer.

The preferred embodiments of the present invention are as follows. (1) The two electrodes that sandwich the ferroelectric film must both be semiconductors. (2) The semiconductor electrode must be made of a material having a perovskite structure. (3) The ferroelectric film should be made of a material having a perovskite structure. (4) The (100) oriented silicon layer should be a single crystal silicon layer. (5) The single crystal silicon layer is epitaxially grown by a selective growth method on a silicon substrate, or is a single crystal formed by solid phase growth from a silicon substrate after selective growth of amorphous silicon. (6) Between the (100) oriented silicon layer and the ferroelectric film,
To sandwich a metal or insulating film with a large barrier property. (7) The ferroelectric film has strain introduced by utilizing lattice mismatch with the underlying layer.

[0018]

As described above, in the present invention, the vertical metal / ferroelectric / semiconductor (MF) is formed on the insulating layer on the silicon substrate.
S) or a semiconductor / ferroelectric / semiconductor (SFS) diode having a memory function is formed by epitaxial growth.

That is, the (100) plane of silicon used as a substrate for integrated circuits has a square lattice arrangement, and the (100) plane of many perovskite compounds known as ferroelectrics likewise has a square lattice arrangement. Therefore, it is possible to epitaxially grow the perovskite crystal on the silicon (100) surface directly or through some single crystal barrier layer. In fact, the literature (J.App.
According to Phys. Vol.74, No.2, pp.1366-75, 1933), S
It is introduced that a film in which (100) and (110) epitaxial layers of SrTiO ₃ are mixed is formed on the (100) surface of the i substrate via the (100) surface of CaF ₂ .

However, when a silicon substrate on which a switching transistor is actually formed and a diode made of a perovskite-based ferroelectric substance are combined, if elements such as lead and bismuth forming the ferroelectric film diffuse into the transistor, Since it adversely affects the switching operation, it is necessary to form a diode in a place separated from the substrate through an insulating layer. On the other hand, what is currently used as an insulating layer is a mixture of silicon oxides and nitrides and phosphorus and boron, which are all amorphous (non-crystalline) films. It is impossible to form a diode composed of a ferroelectric film epitaxially grown on the substrate.

Therefore, in the present invention, the inventors have focused on introducing a selective growth technique of silicon in order to form a (100) oriented silicon layer on an amorphous insulating layer on a silicon substrate. That is, a contact hole is opened in a part of the insulating layer covering the silicon substrate, and (100) oriented silicon is grown from this contact hole onto the insulating layer to obtain (1
The ferroelectric film can be epitaxially grown through the (00) oriented silicon layer. In order to form the (100) -oriented silicon layer from the contact hole opened in a part of the insulating layer, a method of selectively epitaxially growing the (100) -oriented silicon layer directly on the insulating layer, or an amorphous silicon on the insulating layer is used. There is a method in which a layer is selectively or directly grown, and then annealing is performed to cause solid phase growth from the interface of the silicon substrate to single crystallize.

In the present invention, it is not necessary at this time to selectively grow a single crystal silicon layer containing no sub-grain boundaries, but to a certain extent a dielectric film can be epitaxially grown thereon (100). A sub-grain boundary or the like may be included as long as it is oriented. Specifically, when the epitaxially grown dielectric film is θ-2,
In the X-ray diffraction measurement by the θ method, the peaks corresponding to (100) and its multiples are 5 times or more, preferably 10 times or more, as high as the peaks of (110), (211), (111), etc. It only has to be (100) oriented. further,
The half-width of the rocking curve of the (200) peak measured by X-ray diffraction of the dielectric film is preferably 2 ° or less, more preferably 1 ° or less.

Further, in order to avoid mutual diffusion between the grown silicon layer and the ferroelectric film, it is desirable to sandwich a metal film or an insulating film having a large barrier property therebetween. Examples of the barrier metal film include silicides such as nickel and cobalt which are substantially lattice-matched with silicon, and nitrides such as titanium and tungsten. In the case of silicide, the upper surface of the single crystal silicon layer may be reacted with cobalt, nickel or the like to form the silicide layer. Examples of the barrier insulating film include fluoride such as calcium and oxides such as cerium and magnesium which are substantially lattice-matched with silicon.

Further, a great advantage of epitaxially growing a dielectric is that strain can be introduced into the dielectric by utilizing lattice mismatch with the substrate at the time of epitaxial growth so that the paraelectric can be made ferroelectric. is there. By using this technique, it is possible to realize a ferroelectric film that does not use lead or bismuth, which has a low melting point and is easily diffused, or sodium or potassium, which is essential for a ferroelectric substance.

According to the research conducted by the present inventors, in the (BaSr) TiO ₃ dielectric film epitaxially grown on the MgO substrate (100) surface via the platinum electrode layer, the paraelectric substance is transformed into the ferroelectric substance. A phenomenon in which the Curie temperature rises by 200 ° C or more is seen, and the accumulated charge amount is 20% or more.
It was observed that the phenomenon increased by about 200%. The cause is (BaSr) TiO 2 from the Pt (100) plane spacing.
_{3 Since the} (100) plane spacing is slightly larger, (BaS
r) When TiO ₃ is epitaxially grown on Pt,
It was revealed that there is residual elastic strain in the direction of in-plane compression and extension in the direction perpendicular to the plane, and this residual strain induces ferroelectricity.

Therefore, instead of the MgO substrate, the above selectively grown (100) -oriented silicon layer is used as a base, and an epitaxially grown barrier layer is appropriately placed on the epitaxial growth base electrode slightly smaller than the lattice constant of the dielectric. A dielectric layer such as (BaSr) TiO ₃ is epitaxially grown. As a result, the ferroelectric film can be formed without using the lead or bismuth necessary for producing the ferroelectricity.

Using this strain inducing ferroelectric film to make a diode with a ferroelectric / semiconductor junction, (BaSr) TiO _{3 is} deposited on an epitaxial semiconductor electrode slightly smaller than the lattice constant of the dielectric. A method of epitaxially growing a dielectric layer or the like and further stacking a semiconductor or metal upper electrode, and (BaSr) TiO ₃ on an epitaxial metal electrode slightly smaller than the lattice constant of the dielectric
There are two methods: a method of epitaxially growing a dielectric layer and the like, and a method of stacking a semiconductor layer.

In the example of the former method, (BaSr) TiO 3 is used.
_{3 It} is necessary to select a semiconductor layer having a lattice constant slightly smaller than that of the dielectric film. For this, an oxide semiconductor having a perovskite structure, specifically, S doped with Nb or La is used.
A rTiO ₃ crystal or the like can be used.

In the example of the latter method, platinum or an alloy of platinum having a lattice constant slightly smaller than that of the (BaSr) TiO ₃ dielectric film can be used as the base metal electrode,
Further, as the semiconductor upper electrode, in addition to the above oxide semiconductor having the perovskite structure, a semiconductor such as amorphous silicon or polycrystalline silicon grown at low temperature can be used.

Here, the operation mechanism of the diode having a memory function using the ferroelectric / semiconductor junction will be described below with reference to FIG. Now, consider the n-type semiconductors A and B and the ferroelectric substance as shown in FIG. Here, for convenience of description, it is assumed that the semiconductors A and B are made of the same material and the ferroelectric substance is insulative. Further, the dielectric constant of the ferroelectric substance is the semiconductor A
Or, it is almost the same as B.

Then, as shown in (b), the semiconductor A /
A ferroelectric / semiconductor B double heterojunction is formed. Here, polarization is generated in the ferroelectric substance in the positive direction (c) or the reverse direction (d) (actually, a bias voltage is applied in the positive or negative direction to polarize the ferroelectric substance to return the voltage to 0), and "0 Or "1" is written. At this time, charges of opposite signs are induced on the semiconductor side of the junction corresponding to the polarization charges, causing band bending in the semiconductor due to formation of a depletion layer or charge storage layer, and uniform electric field in the ferroelectric. Cause

In this state, when a read operation is performed by applying a bias voltage to the extent that the polarization is not inverted in the positive or reverse direction ((e) or (f)), the semiconductor A and the ferroelectric are changed depending on the polarization direction. Since the heights of the barriers formed between the bodies are different, depending on the state of polarization "0" or "1", electrons are not injected from the semiconductor A into the ferroelectric body "OFF" or are injected. The state becomes "ON", and nondestructive read becomes possible depending on the presence or absence of current. further,
When a voltage exceeding the coercive voltage is applied (g), the ferroelectric substance, which has been polarized in the opposite direction, is also inverted-polarized, so that the polarization state of "1" is rewritten.

Therefore, when the semiconductor / ferroelectric / semiconductor structure is formed in this manner, the current flowing through the junction can be controlled by the direction of polarization in the voltage range in which the polarization does not invert, and further voltage is applied. Thus, a diode element capable of controlling the polarization direction can be manufactured. Moreover, if the diode element has a symmetrical structure as described above, the direction of so-called diode characteristics can be inverted by remanent polarization, and a variable polarity diode can be manufactured.

In the characteristics of the element using the semiconductor / ferroelectric heterojunction, the above-mentioned example is an example, and the conductivity type of semiconductor or ferroelectric (carrier concentration, p-type /
Since the height of the barrier formed at the interface and the internal electric field differ depending on the n-type), work function, dielectric constant, etc., various variations are possible.

As described above, the diode based on the principle of the present invention utilizes the fact that the height of the barrier of the ferroelectric / semiconductor junction changes depending on the polarization direction of the ferroelectric. It must include a ferroelectric / semiconductor junction. That is, a semiconductor / ferroelectric / semiconductor structure or a semiconductor / ferroelectric / metal structure. Here, an insulating material or a semiconductive material can be used as the ferroelectric material.

Further, in order to reduce the interface level generated at the ferroelectric / semiconductor junction interface as much as possible, both are preferably made of the same crystalline material, for example, a combination of a perovskite ferroelectric material and a semiconductor material, and further epitaxially grown. It is desirable to use a single crystal or an oriented film.

Further, since the diode of the present invention utilizes the height of the barrier of the ferroelectric / semiconductor heterojunction, the above-mentioned change utilizing the conduction characteristic in the interface direction at the ferroelectric / semiconductor interface is used. There is a great practical advantage that the influence of various levels formed at the interface can be reduced as compared with the MFS-FET device and the like.

The diode according to the present invention can exert great power by being incorporated in an integrated circuit as described above. That is, on a semiconductor substrate on which switching transistors are formed in advance, metal / ferroelectric /
A semiconductor or a semiconductor / ferroelectric / semiconductor stacked diode is formed, and one transistor and one diode are combined to form a memory unit, and writing is performed by applying a voltage above the coercive voltage of the ferroelectric, and read operation is performed at a voltage below the coercive voltage By doing so, it is possible to create a non-volatile and non-destructive read-out memory cell.

As the diode, two types of semiconductor / ferroelectric / semiconductor (SFS) junction and metal / ferroelectric / semiconductor (MFS) junction can be used.
By using S, a variable polarity diode can be created, and as a result, reading can be performed with both a positive voltage and a negative voltage. Therefore, by alternately applying positive and negative voltages, it is possible to avoid the adverse effect on the memory retention due to the voltage application at the time of reading.

As described above, according to the present invention, by using the new diode utilizing the heterojunction of the ferroelectric and the semiconductor formed on the silicon substrate, the non-destructiveness of the stored contents and the non-destructiveness at the time of reading are In addition to the above, it is possible to realize a small-sized semiconductor memory device that can be highly integrated.

[0041]

The present invention will be described below with reference to the illustrated embodiments. (Embodiment 1) FIG. 1 shows an S according to a first embodiment of the present invention.
It is an element structure sectional view showing a nonvolatile semiconductor memory device using an FS diode. One MOS for switching
A nonvolatile memory cell is configured by combining the -FET and the variable polarity diode of the SFS structure. Although one cell portion is shown in the drawing, a plurality of memory cells are arranged in a matrix like a normal DRAM. Further, a sense amplifier or the like is formed adjacent to the memory cell array composed of these memory cells.

A method of manufacturing the device of this embodiment will be described with reference to the process sectional views of FIGS. FIG. 2A shows a state where the insulating layer 9 for planarization and the polishing stopper layer 10 are formed after the transistor portion and the bit line of the memory cell are formed. In the figure, 1 is a p-type single crystal Si substrate having a plane orientation (100),
2 is an element isolation oxide film, 3 is a gate oxide film, 4 is poly-Si
Gate electrodes (word lines) made of, for example, 5 and 7 are interlayer insulating films, 6 is an n-type source / drain region, and 8 is a bit line, and these are formed in the same manner as in general DRAM manufacturing. . An etch back method may be used to planarize the insulating layer 9, or a CMP method or the like may be used. As the polishing stopper layer 10, an insulating film such as aluminum oxide can be used.

Then, as shown in FIG. 2B, S is formed by known photolithography and plasma etching.
A shallow trench portion for forming the FS diode and a contact hole to the source region 6 were formed, and an amorphous Si layer 12 was formed by a selective growth technique. As a film forming technique, LPCVD using disilane and diborane as raw material gases
Amorphous silicon layer 12 at a growth temperature of 450 ° C.
Was selectively grown on the single crystal Si substrate 1. Then, heat treatment at 600 ° C. in forming gas is performed to remove S.
growing single crystal Si from the i substrate interface by solid phase growth,
The amorphous Si layer 12 was entirely made into a single crystal.

Then, as shown in FIG. 2C, CMP is performed.
Alternatively, the single crystal Si formed on the polishing stopper layer 10 is removed by mechanical polishing, and the contact 1 of the single crystal Si is formed.
1 and a single crystal Si layer 17 were formed. After that, Figure 2
As shown in (d), a barrier metal film having a thickness of 4 is formed by a known method using a magnetron sputtering apparatus.
A TiN film 18 having a thickness of 00 nm was formed and processed into a plate electrode by lithography and reactive ion etching.
At this time, the plate electrode 18 of the TiN film grown on the single crystal Si layer 17 is epitaxially grown.

Next, on the plate electrode 18 of the TiN film, a magnetron sputtering apparatus was used and a SrTiO ₃ (STO) sintered body target containing 5% lanthanum was used at a substrate temperature of 200 ° C. in a mixed atmosphere of argon and oxygen. Was used to form a lanthanum-doped STO thin film (lower electrode) 13 which is an n-type semiconductor having a thickness of 200 nm. Furthermore, zircon / lead titanate (Pb (Zn _0.5 Ti _0.5 ))
A PZT thin film (ferroelectric film) 16 having a thickness of 300 nm is formed by using a sintered body target of O ₃ , which will be abbreviated as PZT hereinafter, and lanthanum, which is an n-type semiconductor having a thickness of 200 nm, is formed again.
A doped STO thin film (upper electrode) 15 was formed.

Then, lithography and ammonia water,
The SFS diode element was processed by wet etching using a mixed solution of hydrogen peroxide solution and EDTA. Then, using an infrared lamp anneal device, it is 70 in nitrogen.
By heat treatment at 0 ℃ for 1 minute, lanthanum-doped ST
The O thin film 13 and the PZT thin film 16 were formed into epitaxial films by solid phase growth.

The ferroelectric film 16 obtained here was subjected to X-ray diffraction measurement by the θ-2θ method.
Only peaks corresponding to (100) and its multiples were observed, and peaks corresponding to (110), (211), (111), etc. were not observed.

Next, as shown in FIG. 2 (e), a flattening insulating film 19 was formed, and the surface was flattened by the CMP method or the etch back method. After that, as shown in FIG. 2F, a contact hole with the contact 11 of single crystal Si and the upper electrode 15 of the SFS diode was opened by photolithography and plasma etching to form an aluminum wiring 20.

As in this embodiment, the MOS-FET and SF
If a memory cell composed of an S diode is used, by applying a voltage higher than the coercive electric field of the PZT ferroelectric film 16 to the SFS diode through the MOS-FET selected by the word line 4 and the bit line 8, a positive or negative voltage is applied. It becomes possible to write 1-bit information by polarization in the direction. On the other hand, similarly, when an appropriate voltage below the coercive electric field is applied to the SFS diode, the read current becomes 1 depending on the polarization direction.
Since there is a large difference of one digit or more, written information can be read nondestructively. (Embodiment 2) FIG. 3 shows an M according to a second embodiment of the present invention.
It is an element structure sectional view showing a nonvolatile semiconductor memory device using an FS diode. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The difference of this embodiment from the first embodiment described above is that instead of PZT which is a ferroelectric substance, a strain induced ferroelectric film is formed by utilizing the mismatch strain generated during epitaxial growth. It has been formed. That is, the MFS diode is formed from the epitaxial barrier metal 22, the epitaxial semiconductor lower electrode 23, the epitaxial strain inducing ferroelectric film 26, and the upper electrode 25.

The manufacturing method of this embodiment will be described with reference to the process sectional views of FIGS. The process up to FIG. 4A is substantially the same as that of the first embodiment, and the transistor portion of the memory cell and the bit line 8, the insulating layer 9 for planarization and the polishing stopper layer 10 are formed.

Next, as shown in FIG. 4B, a contact hole to the source region 6 and a shallow trench portion for forming the MFS diode are formed at the same position by known photolithography and plasma etching, and the selective growth technique is used. Thus, the contact plug 11 of single crystal Si was formed. The contact plug 11 does not single-crystallize amorphous Si by solid phase growth, but directly grows single-crystal Si in a contact hole by a selective growth technique.

Then, as shown in FIG. 4C, CMP is performed.
Alternatively, the single crystal Si formed on the polishing stopper layer 10 was removed by mechanical polishing, and the single crystal Si was removed to a position lower than the lower portion of the polishing stopper layer 10 by photolithography and ion etching. After that, FIG.
As shown in (d), a TiN thin film was epitaxially grown as a barrier metal 22 at 600 ° C. by the reactive sputtering method. Subsequently, a STO thin film of niobium-doped (5 at%) to be the semiconductor lower electrode 23 is formed by sputtering.
It was epitaxially grown at 00 ° C.

Then, as shown in FIG.
The barrier metal 22 and the semiconductor lower electrode 23 formed on the polishing stopper layer 10 were removed by the MP method. afterwards,
As shown in FIG. 4 (f), a Ba _0.5 Sr _0.5 TiO ₃ thin film (ferroelectric film) 26 is epitaxially grown on the semiconductor lower electrode 23, and strain-induced ferroelectricity is added by a mismatch strain with the lower electrode 23. The nickel upper electrode 25
Were sequentially formed.

The ferroelectric film 26 obtained here was subjected to X-ray diffraction measurement by the θ-2θ method.
Only peaks corresponding to (100) and its multiples were observed, and peaks corresponding to (110), (211), (111), etc. were not observed.

With such a structure, the MOS-FET is
A memory cell is composed of the MFS diode and, and the same effect as that of the first embodiment can be obtained. Moreover, when the dielectric film is epitaxially grown, strain is introduced by utilizing the lattice mismatch with the base to make the paraelectric material ferroelectric, so that lead or bismuth, which has a low melting point and easily diffuses, or sodium or potassium, etc. A ferroelectric film without using can be realized. (Embodiment 3) FIG. 5 shows an M according to a third embodiment of the present invention.
It is an element structure sectional view showing a nonvolatile semiconductor memory device using an FS diode. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The difference between this embodiment and the second embodiment described above is that the lower electrode is a metal and the upper electrode is a semiconductor. That is, an epitaxial barrier metal (single crystal nickel silicide layer) 32, a platinum thin film lower electrode 33,
An MSF diode is formed from the epitaxial strain inducing ferroelectric film 36 and the semiconductor upper electrode 35.

The manufacturing method of this embodiment will be described with reference to the process sectional views of FIGS. The process up to FIG. 6A is substantially the same as that of the first embodiment, and the transistor portion of the memory cell and the bit line 8, the insulating layer 9 for planarization, and the polishing stopper layer 10 are just formed.

Next, as shown in FIG. 6B, a contact hole to the source region 6 is continuously formed in the opening of the polishing stopper layer 10 by known photolithography and plasma etching, and the single crystal is formed by the selective growth technique. Si
The contact plug 11 was formed. That is, as the contact plug 11, LP using dichlorosilane as a raw material gas
Single crystal Si was selectively embedded at a growth temperature of 820 ° C. by the CVD method.

Then, as shown in FIG. 6C, CMP is performed.
Alternatively, the single crystal Si formed on the polishing stopper layer 10 is removed by mechanical polishing, and the nickel thin film 31 is formed by the sputtering method. After that, as shown in FIG. 6D, the surface of the single crystal Si layer is reacted with nickel by heat treatment at 500 ° C. in a forming gas to form a single crystal nickel silicide layer 32 as a barrier metal.
The nickel thin film 31 formed on the polishing stopper layer 10 was removed by the MP method.

Next, as shown in FIG. 6E, the nickel silicide layer 32 is removed to a position lower than the upper surface of the polishing stopper layer 10 by photolithography and plasma etching, and then a platinum thin film to be the lower electrode 33 is formed. Was formed by a sputtering method.

Then, as shown in FIG. 6 (f), C
After removing the platinum thin film formed on the polishing stopper layer 10 by the MP method, the (BaSr) TiO ₃ strain-induced ferroelectric film 36 was formed. To form the ferroelectric film 36,
It was epitaxially grown at 600 ° C. by a known magnetron sputtering method. Furthermore, on the ferroelectric film 36,
An amorphous Si semiconductor upper electrode 35 was formed. The upper electrode 35 was formed at a growth temperature of 300 ° C. by a plasma CVD method using monosilane and phosphine as source gases.

The ferroelectric film 36 obtained here was subjected to X-ray diffraction measurement by the θ-2θ method.
Only peaks corresponding to (100) and its multiples were observed, and peaks corresponding to (110), (211), (111), etc. were not observed.

With such a structure, the MOS-FET is
Since the memory cell is composed of the MFS diode and the MFS diode, and strain is introduced by utilizing the lattice mismatch with the base during epitaxial growth of the dielectric film to make the paraelectric material ferroelectric, The same effect can be obtained. In addition,
The present invention is not limited to the above embodiments,
Various modifications can be implemented without departing from the gist of the invention.

[0065]

As described above in detail, according to the present invention, S
It is possible to create a memory cell that uses a heterojunction of a ferroelectric and a semiconductor on an i substrate, and realize a small highly integrated semiconductor memory device that has nonvolatility of stored contents and nondestructiveness at the time of reading. The industrial value of the present invention is extremely high.

[Brief description of drawings]

FIG. 1 is a sectional view of an element structure showing a nonvolatile semiconductor memory device using an SFS diode according to a first embodiment.

FIG. 2 is a sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment.

FIG. 3 is an element structure cross-sectional view showing a nonvolatile semiconductor memory device using an MFS diode according to a second embodiment.

FIG. 4 is a sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the second embodiment.

FIG. 5 is an element structure cross-sectional view showing a nonvolatile semiconductor memory device using an MFS diode according to a third embodiment.

FIG. 6 is a sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the third embodiment.

FIG. 7 is an operation principle diagram of an SFS diode according to the present invention.

FIG. 8 is a schematic cross-sectional view of a conventional MFS-FET.

FIG. 9 is an operation principle diagram of a known MFM laminated structure element.

[Explanation of symbols]

1 ... Single crystal Si substrate 2 ... Element isolation oxide film 3 ... Gate oxide film 4 ... Gate electrode (word line) 5, 7 ... Interlayer insulating film 6 ... Source / drain region 8 ... Bit line 9, 19 ... Insulation for planarization Film 10 ... Polishing stop layer 11 ... Single crystal silicon contact 13, 23 ... STO thin film (lower electrode) 15 ... STO thin film (upper electrode) 16 ... PZT thin film (ferroelectric film) 17 ... Single crystal silicon layer 18 ... TiN film (Plate electrode) 22 ... TiN film (barrier metal) 25 ... Nickel layer (upper electrode) 26, 36 ... (BaSr) TiO ₃ strain induction ferroelectric film 31 ... Nickel thin film 32 ... Nickel silicide layer (barrier metal) 33 ... Platinum thin film (lower electrode) 35 ... Amorphous Si semiconductor layer (upper electrode)

Claims (1)

[Claims] 1. A diode having a heterojunction structure in which a ferroelectric film is sandwiched between two electrodes, at least one of which is a semiconductor film, and the current flowing through the heterojunction is controlled by polarization of the ferroelectric film. A semiconductor memory device comprising a switching transistor connected to the diode and a memory cell, the semiconductor memory device being provided on a part of the insulating layer covering an insulating layer covering a silicon substrate on which the switching transistor is formed. A (100) -oriented silicon layer is grown from the opening, and this (10)
0) A semiconductor memory device characterized in that the ferroelectric film is epitaxially grown on an oriented silicon layer.