JPH0997877A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method by which a ferroelectric memory which can secure a degree of freedom in design and can improve the characteristics of a transistor can be manufactured. SOLUTION: After a contact layer 3 is formed on the surface of an Si substrate 1, a thin film capacitor section 15 composed of a TiN film, a Pt film 12, a strain inducing BaSrTiO3 film 13 and a Pt film 14 is formed on the substrate 1 so that the section 15 can come into contact with the layer 3. A conductive layer 22 is provided on the contact layer 3 and a transistor layer 36 is formed on an insulating layer 21 so that the section 36 can come into contact with the layer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, as a semiconductor memory device, a ferroelectric memory in which a ferroelectric thin film is used for a capacitor of a memory cell has been developed, and some have already been put to practical use. Ferroelectric memory is non-volatile, and the stored contents are not lost even after the power is turned off. Moreover, when the ferroelectric thin film is thin, reversal of remanent polarization is fast, and it is similar to DRAM (volatile memory). It has features such as high-speed writing and reading. In addition, one memory cell is
Since it can be made with one transistor and one capacitor, it is suitable for large capacity. Also, recently, a technique for operating the ferroelectric memory in DRAM has been studied.

A conventional ferroelectric memory has the following structure. A transistor is formed on the surface of the Si substrate, and an insulating film is formed on the transistor. An opening is formed in the insulating film above the drain layer of the transistor, and polycrystalline Si is embedded in the opening as a lead electrode of the drain layer. This polycrystalline Si
A lower electrode, a ferroelectric thin film, and an upper electrode are stacked on top of each other to form a thin film capacitor.

[0004]

The conventional ferroelectric memory has the following problems. Since the position where the ferroelectric thin film is formed is limited to the upper part of the drain layer, it is difficult to secure the degree of freedom in design. In addition to this, for example, PZT (PbTiO ₃ and Pb), which is a typical ferroelectric thin film, is used.
When a solid solution of ZrO ₃ ) is used, Pb, which is a constituent component of the ferroelectric substance, diffuses downward in the high temperature treatment process for crystallization of the ferroelectric thin film, and the diffused Pb
Deteriorates the characteristics of the transistor.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device capable of ensuring a degree of freedom in design. Another object of the present invention is to provide a method for manufacturing a semiconductor memory device in which the characteristics of transistors are good.

[0006]

In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate as an invention according to claim 1.
A contact layer formed on the surface of the semiconductor substrate; a thin-film capacitor portion formed on the semiconductor substrate so as to contact the contact layer and having a lower electrode, a ferroelectric layer, and an upper electrode laminated thereon; An insulating layer formed on the substrate, a conductive layer provided in an opening of the insulating layer formed at a position different from the thin film capacitor portion on the contact layer, and contacting the conductive layer. A semiconductor memory device is also provided, which includes a transistor portion formed on the insulating layer.

According to a second aspect of the present invention, a step of forming a contact layer on the surface of a semiconductor substrate, and laminating a lower electrode, a ferroelectric layer and an upper electrode on a portion of the semiconductor substrate which is in contact with the contact layer, are thin film capacitors. A part of the insulating layer, a step of forming an insulating layer on the semiconductor substrate, a step of forming an opening of the insulating layer at a position different from that of the thin film capacitor part on the contact layer, and a conductive layer in the opening. Provided is a method of manufacturing a semiconductor memory device, comprising: a step of depositing a conductive layer; and a step of forming a transistor portion on the insulating layer so as to be in contact with the conductive layer.

In the conventional semiconductor memory device, the transistor portion is formed on the surface of the semiconductor substrate, and the thin film capacitor portion formed on the insulating layer is formed directly on the transistor portion. The position of will be decided by itself.

On the other hand, in the semiconductor memory device of the present invention, the thin film capacitor portion is formed directly on the semiconductor substrate,
The thin film capacitor section is formed on the insulating layer through the contact layer formed on the surface of the semiconductor substrate and the conductive layer formed on the contact layer at a position different from that of the thin film capacitor section. Electrically connected to the transistor part. Therefore, by adjusting the length of the contact layer, the positions of the thin film capacitor portion and the transistor portion can be arbitrarily adjusted, and the degree of freedom in design increases.

Further, in the conventional method for manufacturing a semiconductor memory device, since the transistor portion is formed on the surface of the semiconductor substrate, the conductive layer is deposited on the upper portion of the transistor portion, and the thin film capacitor portion is formed on the conductive layer. Due to the high-temperature treatment during formation, the material forming the thin-film capacitor portion diffuses into the transistor portion from the transistor portion,
The characteristics of the transistor deteriorate.

On the other hand, in the method of manufacturing the semiconductor memory device of the present invention, the thin film capacitor portion is formed on the semiconductor substrate, then the conductive layer is deposited on the contact layer, and finally the transistor portion is formed. . Therefore, diffusion to the transistor portion due to high-temperature processing when forming the thin film capacitor portion is eliminated, and the transistor characteristics are improved.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 3 are cross-sectional views of a manufacturing process of a ferroelectric memory as a semiconductor memory device according to a first embodiment of the present invention. These will be described below according to the manufacturing process.

First, the manufacturing process up to the part shown in FIG. An element isolation oxide film 2 is formed on an n-type Si substrate 1 having a [001] orientation by a selective oxidation (LOCOS) method.
Next, B is ion-implanted to form a p-type contact layer 3 having a depth of about 400 nm. Thin oxide film 4 by thermal oxidation
After forming, the oxide film is peeled off only on the portion to be the thin film capacitor portion to expose the Si substrate 1 by patterning. At this time, a part of the contact layer 3 is exposed.

The TiN films 11 and 100n having a thickness of about 100 nm are formed on the Si substrate 1 and the oxide film 4 by the sputtering method.
Pt film 12 of about m, BaSrTiO 2 of about 200 nm
₃ (BSTO) film 13 is continuously formed. Si substrate 1
These films formed above are oriented [100] at high temperature and will grow epitaxially. BS at this time
The TO film 13 contains strain due to the difference in lattice size.
After patterning these with photoresist,
By anisotropic etching, only the TiN film 11, the Pt film 12, and the strain-inducing BSTO film 13 which will be the thin film capacitor portion are left. The TiN film 11 and the Pt film 12 serve as the lower electrode, and the strain-induced BSTO film 13 serves as the ferroelectric layer. The substrate temperature when the strain-induced BSTO film 13 is formed is about 600 ° C.
It is. A Pt film 14 is deposited as an upper electrode on the remaining strain-induced BSTO film 13 by a sputtering method to complete the thin film capacitor section 15.

After that, an insulating layer 21 made of an insulating material such as phosphorus glass and having a thickness of about 800 to 1000 nm is formed on the entire surface.
Is deposited. The insulating layer 21 serves as an interlayer insulating film that separates the thin film capacitor portion 15 and the transistor portion, and has a role of preventing the substance forming the thin film capacitor portion 15 from adversely affecting the transistor portion.

After chemical mechanical polishing (CMP) to flatten the surface, the insulating layer 21 on the contact layer 3 is
The opening 23 is provided by using the RIE method. Next, the manufacturing process up to the part shown in FIG.

First, WSi ₂ is buried in the opening 23,
The conductive layer 22 is used. The conductive layer 22 and the insulating layer 2
An amorphous Si layer 31 having a thickness of about 200 nm is epitaxially grown on the substrate 1 and annealed at 600 ° C. for 1 hour, for example. By annealing, crystal grains of about several μm are formed in the amorphous Si layer. Since the crystal grain size is several μm, which is sufficiently larger than the length of the channel portion of the transistor to be formed later, the characteristics of the transistor can be as good as those of the single crystal.

The crystallized Si layer is thermally oxidized to form an oxide film on the surface. A polycrystalline Si layer is deposited on the oxide film by the LPCVD method, and phosphorus is ion-implanted or vapor-phase diffused into the polycrystalline Si layer to have sufficient conductivity. After patterning with a photoresist, anisotropic etching is performed to form a gate oxide film 32 and a gate electrode 33. B using this gate electrode 33 as a mask
Ion implantation is performed to form a p-type source layer 34 and a drain layer 35. As a result, the polycrystalline Si layer 31 ₁ under the gate oxide film 32 becomes a channel region, and the transistor section 36 is completed.

Finally, the manufacturing process up to the part shown in FIG. Thickness 5 made of insulating material such as phosphorous glass on the entire surface
After depositing an insulating layer 41 having a thickness of about 00 nm and making the surface flat by CMP, an opening 43 is provided on each of the thin film capacitor portion 15 and the source layer 34 of the transistor portion 36 by the RIE method. Al in each of the openings 43
A ferroelectric memory is completed by embedding an alloy as the lead wiring 42.

In this ferroelectric memory, the thin film capacitor portion 15 is formed directly on the Si substrate 1, and the transistor portion 36 has the thin film capacitor portion 15, the contact layer 3 on the surface of the Si substrate 1 and the conductivity of the upper portion of the contact layer 3. It is formed on the insulating layer 21 via the layer 22. Therefore, the degree of freedom in design is increased by arbitrarily adjusting the length of the contact layer 3.

Further, since the transistor portion 36 is formed after the thin film capacitor portion 15 is formed, the transistor portion 36 is formed by the diffusion of the material forming the thin film capacitor portion 15 by the heat treatment when forming the thin film capacitor portion 15.
Can be prevented from being adversely affected. Therefore, the characteristics of the transistor section 36 are improved.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
3 is a cross-sectional view of the ferroelectric memory according to the embodiment of FIG. In this figure, the same parts as those in FIG. 3 are designated by the same reference numerals.

This ferroelectric memory differs from the ferroelectric memory shown in FIG. 3 in that the conductive layer 22 formed on the contact layer 3 is made of single crystal Si having the same orientation as that of the Si substrate 1, and the single crystal silicon is used. Is the drain layer 3 of the transistor section 36
It is also serving as 5.

This single crystal Si is prepared as follows. First, polycrystalline Si is formed on the insulating layer 21 including the opening 23.
Is deposited and annealed at 600 ° C. for 1 hour, for example. Since the polycrystalline Si is in contact with the Si substrate 1 at the bottom of the opening 23, solid layer growth with the same orientation as that of the Si substrate 1 occurs from this bottom, and a single crystal region is formed. Since this single crystal region is formed over a region of several tens of μm, the transistor 36 can be formed in this portion.

With this ferroelectric memory, the same effect as that of the ferroelectric memory shown in FIG. 3 can be obtained. The present invention is not limited to the above embodiment. The conductivity types in the above embodiments can be reversed. Further, Si ₃ N ₄ , BPSG, TEOS, SiO ₂ deposited from a liquid phase, or the like is used as the insulating layer, and doped polycrystalline S is used as the conductive layer.
It is also possible to use i, epitaxially grown Si, or the like. Further, RuO ₂ , Ir or the like is used as the lower electrode of the thin film capacitor portion, and PZT or S
rBi ₂ TaO ₇ , Y1, etc. are made of ReO as the upper electrode.
₃ or the like can also be used. In addition, various modifications can be made without departing from the scope of the present invention.

[0026]

As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of ensuring a degree of freedom in design. Further, it is possible to provide a method for manufacturing a semiconductor memory device in which the characteristics of the transistor are good.

[Brief description of drawings]

FIG. 1 is a sectional view of a step of manufacturing a ferroelectric memory according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a step of manufacturing the ferroelectric memory according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a step of manufacturing the ferroelectric memory according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a ferroelectric memory according to a second embodiment of the present invention.

[Explanation of symbols]

1; Si substrate 3; Contact layer 11; TiN film 12; Pt film 13; Strain inducing BaSrTiO ₃ film 14; Pt film 15; Thin film capacitor part 21; Insulating layer 22; Conductive layer 36; Transistor part

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/788 29/792

Claims (2)

[Claims] 1. A semiconductor substrate, a contact layer formed on the surface of the semiconductor substrate, and a lower electrode, a ferroelectric layer and an upper electrode which are formed on the semiconductor substrate so as to be in contact with the contact layer. A thin film capacitor portion, an insulating layer formed on the semiconductor substrate, and a conductive layer provided in an opening of the insulating layer formed at a position different from the thin film capacitor portion on the contact layer, A semiconductor memory device including a transistor portion formed on the insulating layer so as to be in contact with the conductive layer. 2. A step of forming a contact layer on a surface of a semiconductor substrate, and a step of laminating a lower electrode, a ferroelectric layer and an upper electrode on a portion of the semiconductor substrate in contact with the contact layer to form a thin film capacitor section. A step of forming an insulating layer on the semiconductor substrate, a step of forming an opening of the insulating layer at a position different from the thin film capacitor section on the contact layer, and a step of depositing a conductive layer in the opening. And a step of forming a transistor portion on the insulating layer so as to be in contact with the conductive layer, the method of manufacturing a semiconductor memory device.