JP2015109426A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has high on-state current and low off-state current; or provide a semiconductor device having stable electrical characteristics.SOLUTION: Provided is a semiconductor device which uses a gate electrode having the Gibbs free energy of oxidation reaction higher than that of a gate insulation film. A semiconductor device manufacturing method comprises the steps of: forming an oxide semiconductor and a second electrode on a first electrode; forming a gate insulation film so as to contact the first electrode, the oxide semiconductor and the second electrode; forming a gate electrode which faces a lateral face of the oxide semiconductor across the gate insulation film and at least includes an oxide layer; and subsequently performing a heat treatment to supply oxygen from the gate electrode to the oxide semiconductor via the gate insulation film.

Description

The present invention relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, manufacture, or composition (composition of matter). One embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

In recent years, high integration of semiconductor devices has been achieved by miniaturization of transistors. However, in a planar type transistor which has been conventionally used and is manufactured in a planar manner, the short channel effect becomes serious and the limit of miniaturization is approaching. In order to overcome the above-mentioned problems, a vertical transistor has been proposed in which a semiconductor substrate is processed three-dimensionally and a source region, a drain region, and a gate electrode are formed so that a current flows vertically with respect to the substrate. (Non-Patent Document 2). In particular, a vertical transistor having a structure in which a gate electrode surrounds a semiconductor is called an SGT (Surrounding Gate Transistor), and is attracting attention because it can reduce the area occupied by the transistor and can realize a high on-current (non-transisting). Patent Document 1, Non-Patent Document 3).

By the way, an oxide semiconductor attracts attention as a semiconductor applicable to a transistor other than silicon. Transistors using oxide semiconductors are easier to manufacture, operate faster than transistors using amorphous silicon, and have very low off-state leakage current. Therefore, integrated circuits and image display devices (also simply referred to as display devices) Application is expected.

Oxygen deficiency existing in the oxide semiconductor film and at the interface is known to fluctuate the electrical characteristics of the transistor, but by supplying oxygen effectively to the oxide semiconductor interface and film, It is known that the above problems can be overcome. As a method for supplying oxygen to an oxide semiconductor, a method for supplying oxygen from an insulator in contact with the oxide semiconductor (Patent Document 1) and a method for supplying oxygen from a gate electrode (Patent Document 2) are disclosed.

JP 2012-009836 A JP 2013-131740 A

IEEE International Electron Devices Meeting (IEDM) Technical Digest pp. 23-26, 1989 IEEE International Electron Devices Meeting (IEDM) Technical Digest pp. 949-951, 2002 IEEE Symposium VLSI Technology Technological Digest pp. 21-22, 1993

One embodiment of the present invention provides a semiconductor device with a high on-state current, a semiconductor device with a low off-state current, or a semiconductor device that hardly exhibits a short channel effect, or is occupied. An object is to provide a semiconductor device with a small area or a semiconductor device with stable electrical characteristics. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

Note that the description of a plurality of tasks does not disturb each other's existence. Note that one embodiment of the present invention does not have to solve all of these problems. Problems other than those listed will be apparent from descriptions of the specification, drawings, claims, and the like, and these problems may also be a problem of one embodiment of the present invention.

One embodiment of the present invention is an oxide semiconductor, a first electrode in contact with a lower surface of the oxide semiconductor, a second electrode in contact with an upper surface of the oxide semiconductor, and at least a first surface facing a side surface of the oxide semiconductor. And the gate electrode including the second layer and a gate insulating film provided between the oxide semiconductor and the gate electrode, and the first electrode has a region overlapping with the second electrode The first layer of the gate electrode is a semiconductor device provided in contact with the gate insulating film and having a lower oxygen concentration than the second layer of the gate electrode.

In the above aspect, the first layer of the gate electrode contains a substance having a higher Gibbs free energy for oxidation reaction than the gate insulating film.

In the above aspect, the first layer and the second layer of the gate electrode include one or more selected from silver, copper, ruthenium, iridium, platinum, and gold.

In the above embodiment, the gate insulating film has oxygen permeability.

In the above embodiment, an insulating film having a lower oxygen permeability than the gate electrode is provided in contact with at least the side surface of the gate electrode.

In the above embodiment, the gate electrode faces all the side surfaces of the oxide semiconductor.

In the above embodiment, the side surface of the first electrode faces the gate electrode.

An oxide semiconductor and a second electrode over the oxide semiconductor are formed over the first electrode, a gate insulating film is formed so as to be in contact with the first electrode, the oxide semiconductor, and the second electrode. A gate electrode including at least an oxide layer is formed so as to face a side surface of the oxide semiconductor through the film, and then heat treatment is performed, so that oxygen is supplied from the gate electrode to the oxide semiconductor through the gate insulating film .

Note that although an example of a structure of a transistor in which an oxide semiconductor is used for a channel is described in one embodiment of the present invention, one embodiment of the present invention is not limited thereto. For example, in the channel and its vicinity, the source region, the drain region, etc., depending on the case or depending on the situation, Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), etc. You may form with the material which has.

According to one embodiment of the present invention, a semiconductor device with high on-state current, a semiconductor device with low off-state current, or a semiconductor device in which a short channel effect is unlikely to be generated or occupied A semiconductor device with a small area can be provided, or a semiconductor device with stable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device or the like can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

FIG. 11 is a perspective view illustrating a structure example of a transistor. 10A and 10B are a perspective view and a cross-sectional view illustrating a structure example of a transistor. The figure which shows the example of a shape of a semiconductor region. 10 is a cross-sectional view illustrating an example of a method for manufacturing a transistor. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a transistor. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a transistor. FIG. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. 10 is a cross-sectional view illustrating an example of a transistor structure and a manufacturing method thereof. FIG. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. FIG. 9 is a top view illustrating a structure example of a memory device. FIG. 6 is a cross-sectional view illustrating a structure example of a memory device. FIG. 6 is a cross-sectional view illustrating a structure example of a memory device. FIG. 6 is a cross-sectional view illustrating a structure example of a memory device. FIG. 6 is a cross-sectional view illustrating a structure example of a memory device. FIG. 6 is a circuit diagram illustrating an example of a memory device. 4A and 4B are a top view and a circuit diagram illustrating an example of a display device. FIG. 6 is an external view illustrating an example of an electronic device. 6A and 6B illustrate a usage example of an RF tag. The figure which shows the result of a TDS analysis. 6A and 6B illustrate oxygen diffusion in a silicon oxide film. The figure which shows the Gibbs free energy of an oxidation reaction.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments and examples. In the embodiments and examples described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In each drawing described in this specification, the size, the film thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale.

Note that the first and second ordinal numbers used in the present specification are given in order to avoid confusion between components, and are not limited numerically. Therefore, for example, “first” can be described by appropriately replacing “second” or “third”.

In addition, the functions of the “source” and “drain” of the transistor may be switched when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

(Embodiment 1)
In this embodiment, a transistor according to one embodiment of the present invention will be described with reference to drawings.

FIG. 1 is a perspective view of a transistor of one embodiment of the present invention. Note that FIG. 1 is shown with some elements omitted for clarity. A transistor 100 (or 110) illustrated in FIG. 1 includes a substrate 109, a wiring 101, a gate electrode 102 (or a gate electrode 112), and a drain electrode 105.

2B is a cross-sectional view of the transistor illustrated in FIG. 1 taken along a plane X (see FIG. 2A). 2B includes a substrate 109, a wiring 101 formed over the substrate 109, a source electrode 103 formed over the wiring 101, and an oxide semiconductor 104 formed over the source electrode 103. A drain electrode 105 formed over the oxide semiconductor 104 so as to overlap with the source electrode 103; a gate insulating film 106 provided in contact with the side surfaces of the source electrode 103, the oxide semiconductor 104, and the drain electrode 105; The gate electrode 102 provided to face the side surfaces of the source electrode 103, the oxide semiconductor 104, and the drain electrode 105 with the gate insulating film 106 interposed therebetween, and the drain electrode 105, the gate electrode 102, the gate insulating film 106, and the wiring 101 A protective insulating film 107 in contact with the protective insulating film 107, and an interlayer insulating film 108 over the protective insulating film 107. .

The substrate 109 is not limited to a mere support, and may be a substrate on which other elements such as transistors and capacitors are formed. In this case, at least one of the gate electrode 102 and the wiring 101 of the transistor may be electrically connected to the other element. Further, an insulating film may be provided between the substrate 109 and the wiring 101 in order to prevent impurity diffusion from the substrate 109.

Note that in this specification and the like, a transistor can be formed using various substrates 109, for example. The type of the substrate 109 is not limited to a specific type. Examples of the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, and a tungsten substrate. , A substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, an inorganic vapor deposition film, and papers. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, or shape, high current capability, and small size can be manufactured. . When a circuit is formed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

Note that a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on another substrate. As an example of the substrate on which the transistor is transferred, in addition to the substrate on which the transistor can be formed, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, hemp), There are synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

Note that all circuits necessary for realizing a predetermined function can be formed over the same substrate (eg, a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate). Thus, the cost can be reduced by reducing the number of components, or the reliability can be improved by reducing the number of connection points with circuit components.

The transistor 100 is a SGT (Surrounding Gate Transistor), and the distance between the source electrode 103 and the drain electrode 105, that is, the height of the oxide semiconductor 104 corresponds to the channel length of the transistor 100. The transistor 100 operates completely depleted because the entire side surface of the oxide semiconductor 104 is surrounded by the gate electrode 102, has high on-current, and prevents an increase in leakage current (off-current) due to DIBL (Drain Induced Barrier Lowering). be able to. The channel length of the transistor 100 can be, for example, 30 nm to 500 nm, preferably 50 nm to 300 nm, more preferably 100 nm to 200 nm.

Since the SGT made of single crystal silicon has a channel formed in a three-dimensionally processed single crystal silicon substrate, a channel is also formed in a plane orientation with a high interface state density. In some cases, the electrical characteristics are likely to deteriorate. On the other hand, an SGT manufactured using an oxide semiconductor has very little dependence on the interface state with respect to the plane orientation, and the above-described problem does not occur. Therefore, it is preferable to manufacture SGT with an oxide semiconductor.

In addition, when an SGT is formed using single crystal silicon, an advanced impurity implantation technique is required to form a source region and a drain region. However, when an SGT is formed using an oxide semiconductor, a transistor can be formed without performing impurity implantation. Therefore, the manufacturing process is easier than that of single crystal silicon.

In general, a transistor including an oxide semiconductor is known to have a variation in electric characteristics of the transistor due to oxygen deficiency. Therefore, the transistor 100 is preferably supplied with oxygen to the oxide semiconductor 104. In the case where oxygen is supplied to the protective insulating film 107 and the interlayer insulating film 108 and oxygen supply is attempted, the oxide semiconductor 104 is surrounded by electrodes on the top and bottom and the side surfaces. It cannot penetrate and does not reach the oxide semiconductor 104. Although there is a method in which oxygen is supplied from the gate insulating film 106, in a miniaturized transistor, the gate insulating film 106 is generally formed thin in order to ensure gate capacitance. Therefore, the gate insulating film 106 cannot contain a sufficient amount of oxygen, and oxygen vacancies in the oxide semiconductor 104 may not be sufficiently repaired. For the above reasons, in the transistor 100, it is difficult to supply oxygen to the oxide semiconductor 104 from the surrounding insulating film.

In this embodiment mode, a method for solving the above problem by giving an oxygen supply capability to a gate electrode is shown. Since the gate electrode has oxygen supply capability, the operation can be stabilized even in the vertical transistor. The details are described below.

The gate electrode 102 is a conductive film containing oxygen and contains a substance having a higher Gibbs free energy for oxidation reaction than the gate insulating film 106. That is, the gate electrode 102 has a property that it is easier to reduce than the gate insulating film 106. In other words, the gate electrode 102 has a property that it is less likely to be oxidized than the gate insulating film 106.

The thickness of the gate electrode 102 is, for example, 3 nm to 300 nm, preferably 5 nm to 100 nm, more preferably 10 nm to 50 nm.

The gate insulating film 106 has oxygen permeability. A film having oxygen permeability refers to a film that transmits oxygen molecules or a film that has a sufficiently high diffusion coefficient of oxygen atoms and allows oxygen atoms to pass through heat treatment or the like in a manufacturing process. For example, a film that transmits oxygen molecules may have a low density that allows oxygen molecules to pass through. Specifically, the film density may be less than 3.2 g / cm ³ . In addition, a film through which oxygen atoms permeate has a diffusion coefficient of oxygen atoms at 150 ° C. or higher and 450 ° C. or lower of 3 × 10 ⁻¹⁶ cm ² / second or more, preferably 1 ×, depending on the thickness of the gate insulating film 106. It may be 10 ⁻¹⁵ cm ² / second or more, more preferably 8 × 10 ⁻¹⁵ cm ² / second or more.

Since the gate electrode 102 containing oxygen is formed using a substance that is more easily reduced than the gate insulating film 106, when heat treatment is performed, the gate electrode 102 is reduced and oxygen is released. Oxygen released from the gate electrode 102 can pass through the gate insulating film 106 and reach the oxide semiconductor 104.

Note that the heat treatment may be performed at a temperature of 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state.

By performing heat treatment with the gate electrode 102 and the gate insulating film 106 as described above, oxygen can be supplied from the gate electrode 102 to the oxide semiconductor 104 through the gate insulating film 106.

For reference, FIG. 22 shows the Gibbs free energy of the oxidation reaction of each element. The horizontal axis of FIG. 22 is temperature [° C.], and the vertical axis is Gibbs free energy (ΔG [kJ / mol]). The Gibbs free energy of the oxidation reaction shown in FIG. 22 is obtained by the following calculation. First, by using the values of standard production enthalpy ΔH and standard entropy S in each substance shown in Table 1 and substituting them into the formulas of each oxidation reaction shown in Table 2, standard production enthalpy ΔH and standard production entropy in each oxidation reaction The value of ΔS is calculated. Table 2 shows the calculated standard production enthalpy ΔH and standard production entropy ΔS in each oxidation reaction. In addition, the value of standard production | generation enthalpy (DELTA) H and standard entropy S in each substance shown in Table 1 is quoted mainly from the Chemical Society of Japan "Chemical Handbook basic edition II revised 4th page 285, Maruzen Co., Ltd.".

Next, the values of the standard production enthalpy ΔH and the standard production entropy ΔS shown in Table 2 are substituted into the following formula (1), and the Gibbs free energy values of the respective oxidation reactions in the temperature range of 0 ° C. or higher and 900 ° C. or lower. Was calculated. Note that T in Equation (1) is the temperature [K].

ΔG = ΔH−TΔS × 10 ⁻³ (1)

From FIG. 22, for example, the gate electrode 102 may be a layer formed of an oxide containing one or more elements selected from silver, copper, ruthenium, iridium, platinum, and gold. Platinum and gold are not shown in FIG. 22, but are known to be difficult to oxidize. Since the oxide containing the element has high Gibbs free energy for the oxidation reaction, the oxide itself is easily reduced and the film in contact with the oxide is easily oxidized. Note that an oxide containing ruthenium or iridium is preferably used because of high conductivity. Examples of the oxide containing ruthenium or iridium include RuO _X (X is 0.5 or more and 4 or less), IrO _X (X is 0.5 or more and 4 or less), SrRuO _X (X is 1 or more and 5 or less), and the like. Can be mentioned.

A transistor 110 illustrated in FIG. 2C illustrates a state after the transistor 100 is subjected to heat treatment and the gate electrode 102 is reduced.

The transistor 110 includes a gate electrode 112 including a conductive film 112 a and a conductive film 112 b, and the conductive film 112 a is in contact with the gate insulating film 106. The conductive film 112a is a film having a lower oxygen concentration than the conductive film 112b. The structure of the transistor 110 other than the gate electrode 112 is the same as that of the transistor 100 in FIG.

The gate electrode 102 in FIG. 2B is subjected to heat treatment so that the region in the vicinity of the gate insulating film 106 is reduced, and the conductive film 112a in which the oxygen concentration is lower than that of the gate electrode 102 is the same as that of the gate electrode 102. The conductive film 112b has a certain oxygen concentration. At this time, oxygen released from the gate electrode 102 reaches the oxide semiconductor 104 and plays a role of reducing oxygen vacancies in the oxide semiconductor 104.

The thickness of the conductive film 112a may be, for example, 1 nm to 100 nm, preferably 1 nm to 50 nm, more preferably 1 nm to 10 nm.

Note that depending on the heat treatment conditions, the entire region of the gate electrode 102 may be changed to the conductive film 112a. That is, the conductive film 112b may not be formed.

In order to increase the conductivity of the gate electrode, a conductive film having a lower resistivity than the gate electrode 102 or the gate electrode 112 may be provided over the gate electrode 102 or the gate electrode 112.

When a material having a work function of 5 eV, preferably exceeding 5.2 eV, such as iridium, platinum, ruthenium oxide, or gold, is used as the conductive film 112a, compared with a case where a material having a work function of 4.7 eV or less is used. This is preferable because the threshold voltage of the NMOS transistor can be shifted in the positive direction.

The gate insulating film 106 is selected from one or more insulators including silicon oxide, silicon oxynitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and is used as a single layer or a stacked layer. That's fine.

An example of a stacked structure of the gate insulating film 106 is described. The gate insulating film 106 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride. Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Therefore, since the physical film thickness can be increased with respect to the equivalent oxide film thickness, the leakage current due to the tunnel current can be reduced even when the equivalent oxide film thickness is 10 nm or less or 5 nm or less. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system, a tetragonal system, and a cubic system. Note that one embodiment of the present invention is not limited thereto.

By the way, a hafnium oxide surface having a crystal structure may have an interface state due to a defect. The interface state may function as a trap center. Therefore, when hafnium oxide is disposed in the vicinity of the channel region of the transistor, the electrical characteristics of the transistor may be deteriorated by the interface state. Therefore, in order to reduce the influence of the interface state, it may be preferable to separate the layers by disposing another layer between the channel region of the transistor and hafnium oxide. This layer has a buffer function. As the layer having a buffer function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that for the layer having a buffer function, for example, a semiconductor or an insulator having an energy gap larger than that of a semiconductor serving as a channel region is used. Alternatively, for the layer having a buffer function, for example, a semiconductor or an insulator having an electron affinity lower than that of a semiconductor serving as a channel region is used. Alternatively, for the layer having a buffer function, for example, a semiconductor or an insulator having higher ionization energy than a semiconductor serving as a channel region is used.

As the source electrode 103 and the drain electrode 105, a conductive film having a property of extracting oxygen from the oxide semiconductor 104 is preferably used. For example, as a conductive film having a property of extracting oxygen from the oxide semiconductor 104, a conductive film containing aluminum, titanium, chromium, nickel, molybdenum, tantalum, tungsten, or the like can be given.

In some cases, oxygen in the oxide semiconductor 104 is released by the action of the conductive film having a property of extracting oxygen from the oxide semiconductor 104, so that oxygen vacancies are formed in the oxide semiconductor 104. The extraction of oxygen is more likely to occur as the temperature is higher. Since there are several heating steps in the manufacturing process of the transistor, there is a high possibility that oxygen vacancies are formed in a region in the vicinity of the oxide semiconductor 104 in contact with the source electrode 103 or the drain electrode 105. In addition, hydrogen may enter the oxygen deficient site by heating, so that the oxide semiconductor 104 becomes n-type. Therefore, by the action of the source electrode 103 and the drain electrode 105, the resistance of the region where the oxide semiconductor 104 and the source electrode 103 or the drain electrode 105 are in contact with each other can be reduced, so that the on-resistance of the transistors 100 and 110 can be reduced.

Note that in the case where a transistor with a small channel length (for example, 200 nm or less or 100 nm or less) is manufactured, the source and the drain may be short-circuited due to formation of the n-type region. Therefore, in the case of forming a transistor with a small channel length, a conductive film having a property of appropriately extracting oxygen from the oxide semiconductor 104 may be used for the source electrode 103 and the drain electrode 105. Examples of the conductive film having a property of appropriately extracting oxygen include a conductive film containing nickel, molybdenum, or tungsten.

In the case of manufacturing a transistor with a very small channel length (40 nm or less or 30 nm or less), a conductive film that hardly extracts oxygen from the oxide semiconductor 104 may be used as the source electrode 103 and the drain electrode 105. Examples of the conductive film that hardly extracts oxygen from the oxide semiconductor 104 include a conductive film containing tantalum nitride, titanium nitride, or ruthenium. Note that a plurality of types of conductive films may be stacked.

The source electrode 103 and the drain electrode 105 are not limited to the metal described above, and a semiconductor whose resistance is reduced by injecting impurities may be used.

The protective insulating film 107 preferably has a blocking effect that prevents the film from permeating both impurities such as hydrogen and moisture and oxygen. Since the protective insulating film 107 that blocks oxygen is in contact with the side surface of the gate electrode 102, oxygen can be prevented from leaking from the side surface of the gate electrode 102 when the gate electrode 102 is reduced, which is effective for the oxide semiconductor 104. Oxygen can be supplied. Therefore, the protective insulating film 107 preferably has a higher oxygen blocking effect (lower oxygen permeability) than the gate electrode 102. The protective insulating film 107 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and the like. An insulator containing one or more selected from the above can be used. In particular, an aluminum oxide film has a high blocking effect against both impurities such as hydrogen and moisture, and oxygen, and is preferable for application to the protective insulating film 107.

The interlayer insulating film 108 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and the like. An insulator containing one or more selected from the above can be used. In particular, silicon oxide or silicon oxynitride is preferable for application to the interlayer insulating film because it has a low dielectric constant and high insulating properties.

Although the semiconductor region has a truncated cone shape in this embodiment mode, the shape of the semiconductor region is not limited to this. FIG. 3 shows a shape example when the semiconductor region is three-dimensionally processed. FIG. 3A shows an example in which a semiconductor region is formed in a prismatic shape. The prismatic shape is easy to layout and can reduce the area occupied by the transistor. FIG. 3B shows an example in which a semiconductor region is formed in a wall shape. Since the wall shape can increase the area of the side surface of the semiconductor region, the on-state current of the transistor can be increased. FIG. 3C shows an example in which a semiconductor region is formed in a truncated pyramid shape. The shape of the truncated pyramid can improve the coverage of the gate insulating film or gate electrode formed on the side surface of the semiconductor region as compared with the wall shape. Note that in FIGS. 3A, 3B, and 3C, corners may be rounded to avoid unintentional concentration of the gate electric field. FIG. 3D illustrates an example in which a semiconductor region is formed in a cylindrical shape. Since the cylindrical shape has no corners on the side surfaces, the gate electric field can be uniformly applied to the semiconductor region. FIG. 3E shows an example in which a semiconductor region is formed in a truncated cone shape. The frustum shape can improve the coverage of the gate insulating film or the gate electrode formed on the side surface of the semiconductor region as compared with the cylindrical shape.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, the oxide semiconductor 104 described in Embodiment 1 will be described in detail.

The oxide semiconductor 104 is an oxide containing indium. For example, when the oxide contains indium, the carrier mobility (electron mobility) increases. The oxide semiconductor 104 preferably contains the element M. Examples of the element M include aluminum, gallium, yttrium, and tin. The element M is an element having a high binding energy with oxygen, for example. The element M is an element having a function of increasing the energy gap of the oxide, for example. The oxide semiconductor 104 preferably contains zinc. When the oxide contains zinc, for example, the oxide is easily crystallized. The energy at the upper end of the valence band of the oxide can be controlled by, for example, the atomic ratio of zinc.

Note that the oxide semiconductor 104 is not limited to the oxide containing indium. For example, the oxide semiconductor 104 may be a Zn—Sn oxide or a Ga—Sn oxide.

For the oxide semiconductor 104, an oxide with a wide energy gap is used. For example, the energy gap of the oxide semiconductor 104 is 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.

The oxide semiconductor 104 is formed by a sputtering method, a CVD (Chemical Vapor Deposition) method (a MOCVD (Metal Organic Chemical Deposition) method, an ALD (Atomic Layer Deposition Method), a thermal CVD method, or a PECVD (Plasma Deposition Method). However, the film formation may be performed using an MBE (Molecular Beam Epitaxy) method or a PLD (Pulsed Laser Deposition) method. In particular, it is preferable to use an MOCVD method, an ALD method, or a thermal CVD method because plasma is not used so that the oxide semiconductor 104 is hardly damaged and leakage current in an off state of the transistor can be suppressed low.

In the case where the oxide semiconductor 104 is formed by a sputtering method, a target containing indium is preferably used to reduce the number of particles. Further, when an oxide target having a high atomic ratio of the element M is used, the conductivity of the target may be lowered. In the case of using a target containing indium, the conductivity of the target can be increased, and DC discharge and AC discharge are facilitated, so that it is easy to deal with a large-area substrate. Therefore, the productivity of the semiconductor device can be increased.

In the case where the oxide semiconductor 104 is formed by a sputtering method, the atomic ratio of the target is as follows: In: M: Zn is 3: 1: 1, 3: 1: 2, 3: 1: 4, 1: 1: 0. 5, 1: 1: 1, 1: 1: 2, 1: 4: 4, etc.

In the case where the oxide semiconductor 104 is formed by a sputtering method, a film with an atomic ratio that deviates from the atomic ratio of the target may be formed. In particular, zinc may have a film atomic ratio smaller than the target atomic ratio. Specifically, the atomic ratio of zinc contained in the target may be 40 atomic% or more and 90 atomic% or less.

Hereinafter, the influence of impurities in the oxide semiconductor 104 is described. Note that in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor 104 to reduce carrier density and purity. Note that the carrier density of the oxide semiconductor 104 is less than 1 × 10 ¹⁷ pieces / cm ^3, less than 1 × 10 ¹⁵ pieces / cm ³ , or less than 1 × 10 ¹³ pieces / cm ³ . In order to reduce the impurity concentration in the oxide semiconductor 104, it is preferable to reduce the impurity concentration in an adjacent film.

For example, silicon in the oxide semiconductor 104 may serve as a carrier trap or a carrier generation source. Therefore, the silicon concentration between the oxide semiconductor 104 and the gate insulating film 106 is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 8 in secondary ion mass spectrometry (SIMS). ^It is less than ¹⁸ atoms / cm ³ , more preferably less than 2 × 10 ¹⁸ atoms / cm ³ .

Further, when hydrogen is contained in the oxide semiconductor 104, the carrier density may be increased. The hydrogen concentration of the oxide semiconductor 104 is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 or less in SIMS. × 10 ¹⁸ atoms / cm ³ or less. In addition, when nitrogen is contained in the oxide semiconductor 104, the carrier density may be increased. The nitrogen concentration of the oxide semiconductor 104 in SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, further preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In order to reduce the hydrogen concentration in the oxide semiconductor 104, it is preferable to reduce the hydrogen concentration in the gate insulating film 106. The hydrogen concentration of the gate insulating film 106 in SIMS is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁸ atoms / cm ³ or less. In order to reduce the nitrogen concentration in the oxide semiconductor 104, it is preferable to reduce the nitrogen concentration in the gate insulating film 106. The nitrogen concentration of the gate insulating film 106 is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably SIMS, in SIMS. 5 × 10 ¹⁷ atoms / cm ³ or less.

The structure of an oxide semiconductor film that can be used for the oxide semiconductor 104 is described below.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor film is classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. Alternatively, an oxide semiconductor is classified into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor.

Note that examples of the non-single-crystal oxide semiconductor include a CAAC-OS (C Axis Crystallized Oxide Semiconductor), a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. As a crystalline oxide semiconductor, a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, or the like can be given.

First, the CAAC-OS film is described.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

Confirming a plurality of crystal parts by observing a bright field image of a CAAC-OS film and a combined analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Microscope). Can do. On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even by a high-resolution TEM image. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when a high-resolution TEM image of a plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in a crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than the metal element included in the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, and has crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii). Therefore, if they are contained inside an oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, resulting in crystallinity. It becomes a factor to reduce. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can serve as carrier traps or can generate carriers by capturing hydrogen.

A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film is unlikely to have electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has a small change in electrical characteristics and has high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

In addition, a transistor including a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

Next, a microcrystalline oxide semiconductor film is described.

The microcrystalline oxide semiconductor film includes a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in a high-resolution TEM image.

The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal part is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Is done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter that is close to or smaller than the size of the crystal part, spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region.

The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

Next, an amorphous oxide semiconductor film is described.

An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

In the amorphous oxide semiconductor film, a crystal part cannot be confirmed in a high-resolution TEM image.

When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor film, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

Note that the oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film.

In the a-like OS film, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part. In some cases, the a-like OS film is crystallized by a small amount of electron irradiation as observed by a TEM, and a crystal part is grown. On the other hand, in the case of a good-quality nc-OS film, crystallization due to a small amount of electron irradiation comparable to that observed by TEM is hardly observed.

Note that the crystal part size of the a-like OS film and the nc-OS film can be measured using high-resolution TEM images. For example, a crystal of InGaZnO ₄ has a layered structure, and two Ga—Zn—O layers are provided between In—O layers. The unit cell of InGaZnO ₄ crystal has a structure in which a total of nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal in a portion where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less.

In addition, the oxide semiconductor film may have a different density for each structure. For example, if the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparing with the density of a single crystal having the same composition as the composition. For example, the density of the a-like OS film is 78.6% or more and less than 92.3% with respect to the density of the single crystal. For example, the density of the nc-OS film and the density of the CAAC-OS film are 92.3% or more and less than 100% with respect to the density of the single crystal. Note that it is difficult to form an oxide semiconductor film whose density is lower than 78% with respect to that of a single crystal.

The above will be described using a specific example. For example, in an oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Therefore, for example, in an oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the a-like OS film is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. It becomes. For example, in the oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS film and the density of the CAAC-OS film are 5.9 g / cm ³ or more 6 Less than ³ g / cm ³ .

Note that there may be no single crystal having the same composition. In that case, a density corresponding to a single crystal having a desired composition can be calculated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to calculate the density of the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably calculated by combining as few kinds of single crystals as possible.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. .

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, a method for manufacturing the transistor 110 described in Embodiment 1 will be described with reference to drawings.

First, the wiring 101 is formed over the substrate 109 (see FIG. 4A).

Next, a conductive film 203, an oxide semiconductor 204, and a conductive film 205 are formed (see FIG. 4B).

The conductive film 203 and the conductive film 205 may be formed by a sputtering method, a CVD method (including but not limited to an ALD method, an MOCVD method, a thermal CVD method, or a PECVD method), an MBE method, or a PLD method. In particular, the ALD method, the MOCVD method, or the thermal CVD method is preferable because it does not use plasma and causes little damage.

The oxide semiconductor 204 is formed using the method described in Embodiment 2.

Next, the conductive film 203, the oxide semiconductor 204, and the conductive film 205 are etched using common photolithography, so that the source electrode 103, the oxide semiconductor 104, and the drain electrode 105 are formed (see FIG. 4C). . A hard mask may be used when the conductive film 203, the oxide semiconductor 204, and the conductive film 205 are etched.

Next, first heat treatment may be performed. The first heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state. The atmosphere of the first heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement desorbed oxygen after heat treatment in an inert gas atmosphere. With the first heat treatment, the crystallinity of the oxide semiconductor 104 can be increased.

Next, a gate insulating film 106 and a conductive film 202 are formed (see FIG. 5A). The gate insulating film 106 and the conductive film 202 may be formed by a sputtering method, a CVD method (including but not limited to an ALD method, an MOCVD method, a thermal CVD method, or a PECVD method), an MBE method, or a PLD method. . In particular, the ALD method, the MOCVD method, or the thermal CVD method is preferable because it does not use plasma and causes little damage.

Next, the conductive film 202 and the gate insulating film 106 are processed by anisotropic etching to form the gate electrode 102 (see FIG. 5B). By anisotropic etching, the gate electrode 102 is formed at a position facing the side surface of the oxide semiconductor 104 with the gate insulating film 106 interposed therebetween. Note that although part of the gate insulating film 106 may remain without being etched depending on the etching method, there is no problem because it is removed in a later polishing step. In addition, an etching method in which a selection ratio is obtained between the gate electrode 102 and the drain electrode 105 is preferable so that the drain electrode 105 is not lost. However, if the above selection ratio cannot be obtained, etching is performed on the drain electrode 105. A stopper may be provided.

Next, a protective insulating film 107 and an interlayer insulating film 108 are formed (see FIG. 5C). The protective insulating film 107 and the interlayer insulating film 108 may be formed by sputtering, CVD (including but not limited to ALD, MOCVD, thermal CVD, or PECVD), MBE, or PLD. Good. In particular, the ALD method, the MOCVD method, or the thermal CVD method is preferable because it does not use plasma and causes little damage.

Next, second heat treatment is performed. The second heat treatment may be performed at a temperature of 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state. Through the second heat treatment, the gate electrode 102 is reduced, so that the conductive film 112a and the conductive film 112b are manufactured (see FIG. 6A). At that time, oxygen released from the gate electrode 102 reaches the oxide semiconductor 104 through the gate insulating film 106, so that oxygen vacancies in the oxide semiconductor 104 can be reduced.

Finally, the protective insulating film 107 and the interlayer insulating film 108 are polished by a CMP (Chemical Mechanical Polishing) method and planarized (see FIG. 6B). At this time, the drain electrode 105 can be used as a stopper for the CMP method. If the drain electrode 105 cannot be used as a stopper, a stopper may be provided on the drain electrode 105.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, a modification of the transistor 110 described in Embodiment 1 will be described with reference to drawings.

<Modification Example 1 of Transistor>
The transistor 410 illustrated in FIG. 7 is similar to the transistor 110 illustrated in FIG. 2C in that the height from the substrate 109 to the top of the gate electrode 112 is lower than the height from the substrate 109 to the lower surface of the drain electrode 105 by the distance d. Transistor. In the region of the distance d shown in the drawing, the gate electrode 112 does not face, so that even when the transistor is in an on state, a gate electric field is not applied and a high resistance region is formed. In the case of a transistor to which a high voltage is applied between the source electrode 103 and the drain electrode 105, the withstand voltage between the source electrode 103 and the drain electrode 105 can be improved by the presence of the high resistance region described above. it can. The length of the distance d is, for example, 10 nm to 300 nm, preferably 30 nm to 200 nm, and more preferably 50 nm to 150 nm.

<Modification Example 2 of Transistor>
A transistor 420 illustrated in FIG. 8 is a transistor in the case where the source electrode 103 between the wiring 101 and the oxide semiconductor 104 is omitted in the transistor 110 in FIG. In this case, the wiring 101 also serves as a source electrode. By omitting the source electrode 103 in the transistor 420, the process can be shortened and damage to the oxide semiconductor 104 can be eliminated when the source electrode 103 is formed by etching.

<Modification Example 3 of Transistor>
A transistor 430 illustrated in FIG. 9B is a transistor in the case where a gate electrode is formed by a CMP method. The structure shown in FIG. 5A is manufactured according to the method described in Embodiment Mode 3. After that, the conductive film 202 is patterned using photolithography to form a protective insulating film 107 and an interlayer insulating film 108 (see FIG. 9A). Next, the interlayer insulating film 108, the protective insulating film 107, the conductive film 202, and the gate insulating film 106 are simultaneously polished by a CMP method and subjected to heat treatment, so that the gate electrode 112 is formed (see FIG. 9B). ). The above-described method is effective when it is difficult to form the gate electrode by anisotropic etching shown in FIG.

<Modification 4 of transistor>
A transistor 440 illustrated in FIG. 10 is a transistor in the case where the insulating film 441 is provided between the gate electrode 112 and the wiring 101 in the transistor in FIG. The presence of the insulating film 441 can reduce the parasitic capacitance generated between the gate electrode 112 and the wiring 101, and can increase the operation speed of the transistor.

The insulating film 441 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and the like. An insulator containing one or more selected from the above can be used. In particular, silicon oxide or silicon oxynitride is suitable for the insulating film 441 because it has a low dielectric constant and high insulating properties.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
In this embodiment, an example of a memory device using a transistor which is one embodiment of the present invention will be described with reference to drawings.

FIG. 11 is a top view of a memory device 500 using a transistor according to one embodiment of the present invention. Note that FIG. 11 is shown with some elements omitted for clarity. The memory device 500 includes a plurality of bit lines BL extending in the column direction, a plurality of word lines WL extending in the row direction, a transistor 530 sandwiched between the word lines WL and disposed on the bit line BL, and a transistor 530. The upper storage element 520 has a contact 510 in contact with the bottom surface of the word line WL and the side surface of the transistor 530. The transistor 530 is a vertical transistor of one embodiment of the present invention. The transistors 530 and the memory elements 520 are arranged in a matrix at intervals of 2F, and the memory device 500 is configured by 4F ² memory cells.

When the storage device 500 is a DRAM (Dynamic Random Access Memory), a capacitor is used as the storage element 520. When the storage device 500 is a PRAM (Phase Change Random Access Memory), a phase change film is used as the storage element 520. When the device 500 is a ReRAM (Resistance Random Access Memory), a resistance change element is used as the memory element 520. Hereinafter, a case where the storage device 500 is a DRAM will be described.

FIG. 12 shows a cross-sectional view taken along line A1-A2 of FIG. A memory device 500 illustrated in FIG. 12 includes a transistor 530, a bit line BL, a word line WL, a contact 510, a plug 511, a first capacitor electrode 512, a second capacitor electrode 513, and a capacitor insulator 514. The memory element 520 is included. The contact 510 is connected to the gate electrode 532 (including the conductive films 532a and 532b) disposed on the side surface of the transistor 530 and the word line WL, and has a function of supplying the potential of the word line WL to the gate electrode 532 of the transistor 530. . A source electrode 533 of the transistor 530 is connected to the bit line BL, and a drain electrode 535 of the transistor 530 is connected to the memory element 520.

The transistor 530 is different from the transistor 110 illustrated in FIG. 2C in the positional relationship between the apex of the gate electrode and the drain electrode. In the transistor 530, the apex of the gate electrode 532 is higher than the drain electrode 535, and the gate electrode 532 and the gate insulating film 536 exist between the contact 510 and the drain electrode 535 (see FIG. 12). With the above structure, the transistor 530 prevents the contact 510 and the drain electrode 535 from being short-circuited. Except for the above features, the transistor 530 is the same as the transistor 110.

FIG. 13 is a cross-sectional view taken along line B1-B2 of FIG.

In FIG. 12 and FIG. 13, a region where no hatch pattern is applied represents a region made of an insulator. Applicable areas include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. An insulator including one or more selected ones can be used.

Since the transistor 530 is a transistor with low off-state current, when it is used in a memory cell of a DRAM, the holding time of charge accumulated in the memory element 520 can be extended. As a result, the frequency of refreshing the DRAM can be reduced and the power consumption can be reduced.

Further, in the case where a 4F ² memory cell is manufactured by SGT using single crystal silicon, an impurity implantation process when forming the source region and the drain region is complicated, but a 4F ² memory cell is manufactured by the transistor 530. In this case, the manufacturing process can be shortened because the impurity implantation step for forming the source region and the drain region is unnecessary.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 6)
In this embodiment, an example in which the memory device described in Embodiment 5 is combined with a transistor formed over a semiconductor substrate will be described with reference to drawings.

14 includes the memory device 500 described in Embodiment 5, a transistor 2200, an element isolation layer 2201, plugs 2202 to 2205, wirings 2208 to 2210, an insulating layer 2207, and a semiconductor substrate 2211. . In FIG. 14, the region where the hatch pattern is not applied is formed of an insulator. The left half area of FIG. 14 shows a cross-sectional view taken along line A1-A2 of FIG. 11, and the right half area of FIG. 14 shows a cross-sectional view taken along line B1-B2 of FIG.

The first semiconductor material used for the semiconductor substrate 2211 is preferably a material having a forbidden band width different from that of the second semiconductor material used for the transistor 530. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon having a polycrystalline structure or a single crystal structure, germanium, silicon germanium, silicon carbide, or gallium arsenide), and the second semiconductor material is an oxide. It can be a semiconductor. A transistor using single crystal silicon or the like as a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor has low off-state current.

For example, a semiconductor having a strain such as strained silicon may be used as the first semiconductor. Alternatively, as the first semiconductor, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like that can be used for a high electron mobility transistor (HEMT) is used. May be. By using these semiconductors as the first semiconductor, the transistor 2200 suitable for high-speed operation can be obtained.

The transistor 2200 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used depending on a circuit. In addition to the use of the transistor of one embodiment of the present invention using an oxide semiconductor, the specific structure of the semiconductor device, such as a material and a structure used, is not necessarily limited to that described here.

Thus, by stacking two types of transistors, the area occupied by the circuit is reduced, and a plurality of circuits can be arranged at a higher density. For example, the driver circuit of the memory device 500 may be formed using the transistor 2200.

Here, in the case where a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, hydrogen in the insulating layer provided in the vicinity of the semiconductor layer of the transistor 2200 terminates a dangling bond of silicon, thereby improving the reliability of the transistor 2200. There is an effect to improve. On the other hand, in the case where an oxide semiconductor is used for the transistor 530 provided in the upper layer, hydrogen in the insulating layer provided in the vicinity of the oxide semiconductor layer becomes one of the factors for generating carriers in the oxide semiconductor. In some cases, the reliability of 530 may be reduced. Therefore, in the case where the transistor 530 using an oxide semiconductor is stacked over the transistor 2200 using a silicon-based semiconductor material, it is particularly preferable to provide the insulating layer 2207 having a function of preventing hydrogen migration between the transistors 530. It is effective. In addition to improving the reliability of the transistor 2200 by confining hydrogen in the lower layer with the insulating layer 2207, the reliability of the transistor 530 can be improved at the same time by suppressing hydrogen diffusion from the lower layer to the upper layer.

As the insulating layer 2207, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

Note that the transistor 2200 can be a transistor of various types as well as a planar transistor. For example, a transistor of FIN (fin) type, TRI-GATE (trigate) type, or the like can be used. An example of a cross-sectional view in that case is shown in FIG. An insulating layer 2212 is provided over the semiconductor substrate 2211. The semiconductor substrate 2211 has a protruding portion (also referred to as a fin) with a thin tip. Note that an insulating film may be provided on the convex portion. The insulating film functions as a mask for preventing the semiconductor substrate 2211 from being etched when the convex portion is formed. In addition, the convex part does not need to have a thin tip, for example, it may be a substantially rectangular parallelepiped convex part or a thick convex part. A gate insulating film 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. A source region and a drain region 2215 are formed in the semiconductor substrate 2211. Note that although the example in which the semiconductor substrate 2211 includes a convex portion is described here, the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 7)
In this embodiment, the transistor which is one embodiment of the present invention is used, the memory content can be retained even when power is not supplied, and an example of a memory device in which the number of writing is not limited is described with reference to the drawings. To explain.

A memory cell illustrated in FIG. 16A includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor 3400. Note that as the transistor 3300, the transistor described in the above embodiment can be used.

The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 3300 has low off-state current, stored data can be held for a long time by using the transistor 3300. In other words, a memory device that does not require a refresh operation or has a very low frequency of the refresh operation can be used, so that power consumption can be sufficiently reduced.

In FIG. 16A, the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is electrically connected to one of a source electrode and a drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to a gate electrode of the transistor 3300. The other of the gate electrode of the transistor 3200 and the source or drain electrode of the transistor 3300 is electrically connected to the first terminal of the capacitor 3400, and the fifth wiring 3005 is a second terminal of the capacitor 3400. And are electrically connected.

In the memory cell illustrated in FIG. 16A, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor 3200 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode of the transistor 3200 and the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, so that the transistor 3300 is turned off, whereby the charge given to the gate of the transistor 3200 is held (held).

Since the off-state current of the transistor 3300 is extremely small, the charge of the gate of the transistor 3200 is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, according to the amount of charge held in the gate of the transistor 3200, The second wiring 3002 has different potentials. In general, when the transistor 3200 is an n-channel transistor, the apparent threshold V _{th_H in the} case where a high-level charge is applied to the gate electrode of the transistor 3200 is a low-level charge applied to the gate electrode of the transistor 3200. This is because it becomes lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for turning on the transistor 3200. Therefore, the charge applied to the gate of the transistor 3200 can be determined by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 3200 is turned on when the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). In the case where a low-level charge is _supplied , the transistor 3200 remains in the “off state” even when the potential of the fifth wiring 3005 is V ₀ (<V _{th_L} ). Therefore, the stored information can be read by determining the potential of the second wiring 3002.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, the fifth wiring 3005 may be _{supplied with a} potential at which the transistor 3200 is turned off regardless of the state of the gate, that is, a potential lower than V _{th_H} . _{Alternatively} , a potential that turns on the transistor 3200 regardless of the state of the gate, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring 3005.

The memory cell illustrated in FIG. 16B is different from FIG. 16A in that the transistor 3200 is not provided. In this case, information can be written and held by the same operation as described above.

Next, reading of information will be described. When the transistor 3300 is turned on, the third wiring 3003 in a floating state and the capacitor 3400 are brought into conduction, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on the potential of the first terminal of the capacitor 3400 (or charge accumulated in the capacitor 3400).

For example, the potential of the first terminal of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge is redistributed Is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. The potential (= (CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= CB × VB0 + C × V0) / (CB + C)). I understand that.

Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

In this case, a transistor to which the first semiconductor material is applied is used for a driver circuit for driving the memory cell, and a transistor to which the second semiconductor material is applied is stacked over the driver circuit as the transistor 3300. And it is sufficient.

In the memory cell described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

Further, in the memory cell described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that the problem of deterioration of the gate insulating film does not occur. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 8)
In this embodiment, a structural example of a display device using a transistor which is one embodiment of the present invention will be described.

<Configuration example>
FIG. 17A is a top view of a display device of one embodiment of the present invention, and FIG. 17B can be used when a liquid crystal element is applied to a pixel of the display device of one embodiment of the present invention. It is a circuit diagram for demonstrating a pixel circuit. FIG. 17C is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied to a pixel of the display device of one embodiment of the present invention.

The transistor provided in the pixel portion can be formed according to the above embodiment mode. In addition, since the transistor can easily be an n-channel transistor, a part of the driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. In this manner, a highly reliable display device can be provided by using the transistor described in the above embodiment for the pixel portion and the driver circuit.

An example of a top view of the active matrix display device is shown in FIG. A pixel portion 701, a first scan line driver circuit 702, a second scan line driver circuit 703, and a signal line driver circuit 704 are provided over a substrate 700 of the display device. In the pixel portion 701, a plurality of signal lines are extended from the signal line driver circuit 704, and a plurality of scan lines are extended from the first scan line driver circuit 702 and the second scan line driver circuit 703. Has been placed. Note that pixels each having a display element are provided in a matrix in the intersection region between the scan line and the signal line. In addition, the substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection unit such as an FPC (Flexible Printed Circuit).

In FIG. 17A, the first scan line driver circuit 702, the second scan line driver circuit 703, and the signal line driver circuit 704 are formed over the same substrate 700 as the pixel portion 701. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when a drive circuit is provided outside the substrate 700, it is necessary to extend the wiring, and the number of connections between the wirings increases. In the case where a driver circuit is provided over the same substrate 700, the number of connections between the wirings can be reduced, so that reliability or yield can be improved.

<Liquid crystal display device>
An example of a circuit configuration of the pixel is shown in FIG. Here, a pixel circuit which can be applied to a pixel of a VA liquid crystal display device is shown.

This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thereby, the signals applied to the individual pixel electrode layers of the multi-domain designed pixels can be controlled independently.

The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be given. On the other hand, the source or drain electrode 714 functioning as a data line is used in common by the transistor 716 and the transistor 717. The transistors described in the above embodiments can be used as appropriate as the transistors 716 and 717. Thereby, a highly reliable liquid crystal display device can be provided.

The shapes of the first pixel electrode layer electrically connected to the transistor 716 and the second pixel electrode layer electrically connected to the transistor 717 are described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a V-shaped shape, and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

A gate electrode of the transistor 716 is connected to the gate wiring 712, and a gate electrode of the transistor 717 is connected to the gate wiring 713. Different gate signals are given to the gate wiring 712 and the gate wiring 713 so that the operation timings of the transistors 716 and 717 are different, whereby the alignment of the liquid crystal can be controlled.

Further, a storage capacitor may be formed using the capacitor wiring 710, a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 includes a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween, and the second liquid crystal element 719 includes a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. Consists of.

Note that the pixel circuit illustrated in FIG. 17B is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

<Organic EL display device>
Another example of the circuit configuration of the pixel is shown in FIG. Here, a pixel structure of a display device using an organic EL element is shown.

In the organic EL element, by applying a voltage to the light-emitting element, electrons are injected from one of the pair of electrodes and holes from the other into the layer containing the light-emitting organic compound, and a current flows. Then, by recombination of electrons and holes, the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

FIG. 17C illustrates an example of an applicable pixel circuit. Here, an example in which two n-channel transistors are used for one pixel is shown. Note that the metal oxide film of one embodiment of the present invention can be used for a channel formation region of an n-channel transistor. In addition, digital time grayscale driving can be applied to the pixel circuit.

An applicable pixel circuit configuration and pixel operation when digital time gray scale driving is applied will be described.

The pixel 720 includes a switching transistor 721, a driving transistor 722, a light-emitting element 724, and a capacitor 723. In the switching transistor 721, the gate electrode is connected to the scanning line 726, the first electrode (one of the source electrode and the drain electrode) is connected to the signal line 725, and the second electrode (the other of the source electrode and the drain electrode) is driven. The transistor 722 is connected to the gate electrode. The driving transistor 722 has a gate electrode connected to the power supply line 727 via the capacitor 723, a first electrode connected to the power supply line 727, and a second electrode connected to the first electrode (pixel electrode) of the light emitting element 724. Has been. The second electrode of the light emitting element 724 corresponds to the common electrode 728. The common electrode 728 is electrically connected to a common potential line formed over the same substrate.

The transistor described in the above embodiment can be used as appropriate as the switching transistor 721 and the driving transistor 722. Thereby, an organic EL display device with high reliability can be provided.

The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. Note that the low power supply potential is lower than the high power supply potential supplied to the power supply line 727. For example, GND, 0V, or the like can be set as the low power supply potential. A high power supply potential and a low power supply potential are set so as to be equal to or higher than the threshold voltage in the forward direction of the light emitting element 724, and by applying the potential difference to the light emitting element 724, a current is passed through the light emitting element 724 to emit light. Note that the forward voltage of the light-emitting element 724 refers to a voltage for obtaining desired luminance, and includes at least a forward threshold voltage.

Note that the capacitor 723 can be omitted by substituting the gate capacitance of the driving transistor 722. As for the gate capacitance of the driving transistor 722, a capacitance may be formed between the channel formation region and the gate electrode.

Next, a signal input to the driving transistor 722 will be described. In the case of the voltage input voltage driving method, a video signal that causes the driving transistor 722 to be sufficiently turned on or off is input to the driving transistor 722. Note that a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode of the driving transistor 722 in order to operate the driving transistor 722 in a linear region. In addition, a voltage equal to or higher than a value obtained by adding the threshold voltage Vth of the driving transistor 722 to the power supply line voltage is applied to the signal line 725.

When analog grayscale driving is performed, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the forward voltage of the light emitting element 724 is applied to the gate electrode of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in a saturation region, and a current is supplied to the light-emitting element 724. Further, in order to operate the driving transistor 722 in the saturation region, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By making the video signal analog, current corresponding to the video signal can be passed through the light-emitting element 724 to perform analog gradation driving.

Note that the structure of the pixel circuit is not limited to the pixel structure illustrated in FIG. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated in FIG.

When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. 17, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. It is assumed that it is connected. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and the potential exemplified above can be input to the second gate electrode, such as a potential lower than the potential applied to the source electrode by a wiring (not shown). do it.

For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. I can do it. As an example of a display element, a display device, a light emitting element, or a light emitting device, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED) , Blue LED, etc.), transistor (transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, grating light valve (GLV), plasma display (PDP), MEMS (micro electro Mechanical system), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element, electrowetting element, piezoelectric ceramic display , Carbon nanotubes, etc., by an electric magnetic action, those having contrast, brightness, reflectance, a display medium such as transmittance changes. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper.

This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 9)
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, mobile phones, game machines including portable devices, portable information terminals, electronic book terminals, video cameras, digital still cameras and other cameras, goggle type displays (head-mounted displays), navigation systems, sound playback devices (car audio, Digital audio player, etc.), copiers, facsimiles, printers, printer multifunction devices, and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 18A illustrates a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, speakers 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 18A includes the two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.

FIG. 18B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image | video in the 1st display part 913 according to the angle between the 1st housing | casing 911 and the 2nd housing | casing 912 in the connection part 915. FIG. Further, a display device to which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 18C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

FIG. 18D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.

FIG. 18E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. The video on the display portion 943 may be switched according to the angle between the first housing 941 and the second housing 942 in the connection portion 946.

FIG. 18F illustrates an ordinary automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

(Embodiment 10)
The storage device described in the above embodiment can be used for cache memories, main memories, and storages of various processors (for example, programmable devices such as CPUs, microcontrollers, FPGAs, and RF tags). In this embodiment, an example of use of an RF tag using the above storage device will be described with reference to FIGS. Applications of RF tags are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 19A), packaging containers (wrapping paper and Bottle, etc., see FIG. 19C), recording medium (DVD, video tape, etc., see FIG. 19B), vehicles (bicycle, etc., see FIG. 19D), personal items (such as bags and glasses) , Articles such as foods, plants, animals, human bodies, clothing, daily necessities, medical products including drugs and drugs, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Alternatively, it can be used by being provided on a tag attached to each article (see FIGS. 19E and 19F) or the like.

The RF tag 4000 according to one embodiment of the present invention is fixed to an article by being attached to the surface or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. The RF tag 4000 according to one embodiment of the present invention achieves small size, thinness, and light weight, and thus does not impair the design of the article itself even after being fixed to the article. In addition, by providing the RF tag 4000 according to one embodiment of the present invention to bills, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided. Counterfeiting can be prevented. In addition, by attaching the RF tag according to one embodiment of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved. You can plan. Even in the case of vehicles, the security against theft or the like can be improved by attaching the RF tag according to one embodiment of the present invention.

As described above, by using the RF tag according to one embodiment of the present invention for each application described in this embodiment, operating power including writing and reading of information can be reduced, so the maximum communication distance can be increased. Is possible. In addition, since the information can be held for a very long period even when the power is cut off, it can be suitably used for applications where the frequency of writing and reading is low.

This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

In this example, the results of investigation on desorption of oxygen contained in ruthenium oxide by temperature programmed desorption analysis (TDS analysis) will be described.

Thermal desorption analysis is to obtain a mass spectrum of desorbed components from a sample for each temperature by mass analysis of gas molecules emitted while heating the sample with infrared in high vacuum. Since the background vacuum degree of the measuring apparatus is 1.33 × 10 ⁻⁷ Pa (10 ⁻⁹ Torr), it is possible to analyze a trace amount component. In this example, EMD-WA1000S manufactured by ESCO was used.

Moreover, the peak in the curve showing the result of the TDS analysis is a peak that appears when atoms or molecules contained in the analyzed sample are released to the outside. Note that the total amount of atoms or molecules released to the outside corresponds to the integrated value of the peak. Therefore, the total amount of atoms or molecules contained in the ruthenium oxide film can be evaluated based on the level of the peak intensity.

In this example, a ruthenium oxide film was formed on a silicon wafer by a sputtering method. The ruthenium oxide film formation conditions were an oxygen flow rate of 20 sccm, a pressure in the processing chamber of 0.4 Pa, 100 W (DC), a target-substrate distance of 60 mm, and a substrate temperature of 150 ° C. The film thickness of ruthenium oxide was set to five conditions of 10 nm, 30 nm, 50 nm, 100 nm, and 200 nm. Here, ruthenium oxide having a thickness of 10 nm is sample A, 30 nm ruthenium oxide is sample B, 50 nm ruthenium oxide is sample C, 100 nm ruthenium oxide is sample D, and 200 nm ruthenium oxide is sample E. To do.

Next, the results of TDS analysis performed on Sample A to Sample E are shown in FIG. FIG. 20 is a graph showing the amount of released oxygen molecules with respect to the substrate temperature.

From the TDS analysis results shown in FIG. 20, even when the ruthenium oxide was 10 nm, the release of oxygen molecules was confirmed. It was also confirmed that the amount of released oxygen molecules increased as the ruthenium oxide film thickness increased.

From the above results, it was confirmed that ruthenium oxide is a film capable of desorbing oxygen by heating.

In this example, the behavior of oxygen in a silicon oxide film by heat treatment is described using secondary ion mass spectrometry (SIMS).

For SIMS, a quadrupole secondary ion mass spectrometer PHI ADEPT1010 manufactured by ULVAC-PHI Co., Ltd. was used.

A method for manufacturing the sample is described below.

First, a quartz substrate was prepared, and a silicon oxide film was formed on the quartz substrate using ¹⁸ O ₂ . Note that the silicon oxide film was formed by a sputtering method. Specifically, using a silicon oxide target, in an atmosphere containing 25 sccm of argon and 25 sccm of oxygen ( ¹⁸ O ₂ ), the pressure is controlled to 0.4 Pa, the substrate heating temperature during film formation is 100 ° C., and the film formation power Was formed to a thickness of 300 nm at 1.5 kW (13.56 MHz).

Here, ¹⁸ O ₂ refers to an oxygen molecule composed of an isotope of oxygen atom ( ¹⁸ O) having an atomic weight of 18.

Next, a silicon oxide film was formed over the silicon oxide film using ¹⁸ O ₂ . Note that the silicon oxide film was formed by a sputtering method. Specifically, using a silicon oxide target, in an atmosphere containing 25 sccm of argon and 25 sccm of oxygen, the pressure is controlled to 0.4 Pa, the substrate heating temperature during film formation is 100 ° C., and the film formation power is 1.5 kW ( The film was formed with a thickness of 100 nm. The silicon oxide film does not intentionally contain ¹⁸ O.

The sample manufactured as described above was subjected to heat treatment at 150 ° C., 250 ° C., 350 ° C., and 550 ° C. for 1 hour in a nitrogen atmosphere. In addition, a sample not particularly subjected to heat treatment was also prepared (referred to as as-depo).

FIG. 21 shows the analysis result of the depth direction of ¹⁸ O by SIMS. The indications of as-depo, 150 ° C., 250 ° C., 350 ° C., and 550 ° C. shown in FIG. 21 correspond to the heat treatment conditions. Also, the right side of the broken line shown in FIG. ^21, showing a film forming the silicon oxide film (silicon oxide ⁽¹⁸ _{O 2)} hereinafter) using a 18 _{O 2.}

FIG. 21 shows that ¹⁸ O diffuses from the silicon oxide film formed using ¹⁸ O ₂ into the silicon oxide film by performing heat treatment. Further, as the temperature of the heat treatment is high, ¹⁸ O ^{18 O} ₂ of a silicon oxide film formed using the silicon oxide film was found to often amounts diffuses.

From the above, it was found that oxygen was diffused by about 40 nm in the silicon oxide film even in the heat treatment at about 150 ° C.

This example shows that oxygen diffuses in the silicon oxide film by heat treatment.

100 transistor 101 wiring 102 gate electrode 103 source electrode 104 oxide semiconductor 105 drain electrode 106 gate insulating film 107 protective insulating film 108 interlayer insulating film 109 substrate 110 transistor 112 gate electrode 112a conductive film 112b conductive film 202 conductive film 203 conductive film 204 oxide Physical semiconductor 205 conductive film 410 transistor 420 transistor 430 transistor 440 transistor 441 insulating film 500 storage device 510 contact 511 plug 512 capacitor electrode 513 capacitor electrode 514 capacitor insulator 520 storage element 530 transistor 532 gate electrode 532a conductive film 532b conductive film 533 source electrode 535 Drain electrode 536 Gate insulating film 700 Substrate 701 Pixel portion 702 Scan line driver circuit 703 Run Line driver circuit 704 Signal line driver circuit 710 Capacitor wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 Pixel 721 Switching transistor 722 Driving transistor 723 Capacitance element 724 Light emitting element 725 Signal line 726 Scan line 727 Power line 728 Common electrode 901 Case 902 Case 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Case 912 Case 913 Display unit 914 Display unit 915 Connection unit 916 Operation key 921 Case 922 Display portion 923 Keyboard 924 Pointing device 931 Case 932 Refrigeration room door 933 Freezer compartment door 941 Case 942 Case 943 Display portion 944 Operation keys 45 Lens 946 Connection portion 951 Car body 952 Wheel 953 Dashboard 954 Light 2200 Transistor 2201 Element isolation layer 2202 Plug 2205 Plug 2207 Insulating layer 2208 Wiring 2210 Wiring 2211 Semiconductor substrate 2212 Insulating layer 2213 Gate electrode 2214 Gate insulating film 2215 Drain region 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitance element

Claims (8)

An oxide semiconductor;
A first electrode in contact with the lower surface of the oxide semiconductor;
A second electrode in contact with the top surface of the oxide semiconductor;
A gate electrode including at least a first layer and a second layer facing a side surface of the oxide semiconductor;
A gate insulating film provided between the oxide semiconductor and the gate electrode,
The first electrode has a region overlapping with the second electrode, the first layer of the gate electrode is provided in contact with the gate insulating film, and more than the second layer of the gate electrode A semiconductor device characterized by low oxygen concentration. In claim 1,
The semiconductor device according to claim 1, wherein the first layer of the gate electrode includes a substance having a higher Gibbs free energy for oxidation reaction than the gate insulating film. In claim 1 or claim 2,
The semiconductor device, wherein the first layer and the second layer of the gate electrode contain one or more selected from silver, copper, ruthenium, iridium, platinum and gold. In any one of Claims 1 thru | or 3,
A semiconductor device, wherein the gate insulating film has oxygen permeability. In any one of Claims 1 thru | or 4,
An insulating film having an oxygen permeability lower than that of the gate electrode is provided in contact with at least a side surface of the gate electrode. In any one of Claims 1 thru | or 5,
The semiconductor device, wherein the gate electrode faces all side surfaces of the oxide semiconductor. In any one of Claims 1 thru | or 6,
A semiconductor device, wherein a side surface of the first electrode faces the gate electrode. An oxide semiconductor and a second electrode on the oxide semiconductor are formed over the first electrode, and a gate insulating film is formed so as to be in contact with the first electrode, the oxide semiconductor, and the second electrode Then, after forming a gate electrode including at least an oxide layer, facing the side surface of the oxide semiconductor through the gate insulating film, heat treatment is performed so that the gate electrode is separated from the gate electrode through the gate insulating film. A method for manufacturing a semiconductor device, wherein oxygen is supplied to the oxide semiconductor.

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