JP2008171990A - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To pattern source/drain electrodes and an active layer by etching without using any lift-off methods in the case of a material having properties capable of etching with at least the same type of etchant. <P>SOLUTION: After the active layer is patterned, first photoresist having an inverted pattern of the source/drain electrodes is formed, the source/drain electrode layers are film-formed, second photoresist is further applied while the first photoresist is allowed to remain, the second photoresist is worked to the shape of the source/drain electrodes, the source/drain electrodes are patterned by etching and the source/drain electrodes are formed with the second photoresist as a mask and the first resist as an etching stopper, and then the first photoresist and the second photoresist are removed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a field effect transistor used for a semiconductor device, a display device, and the like and a manufacturing method thereof.

  Field effect transistors are used as various switching elements such as unit electronic elements, high-frequency signal amplifying elements, and liquid crystal driving elements in semiconductor memory integrated circuits, and the thinned transistors are well known as thin film transistors (TFTs).

  In general, in a TFT, when a substrate is disposed below, a structure in which a gate electrode is disposed below a source / drain electrode is a bottom gate type, and a structure in which a gate electrode is disposed above a source / drain electrode is a top gate. It is called a type TFT.

  Further, in the bottom gate type, a structure in which a source / drain electrode is disposed on an active layer (also called a channel layer) is a top contact type, and a structure in which a source / drain electrode is disposed under an active layer is a bottom contact type. Called.

  FIG. 5 shows a top contact type TFT and FIG. 6 shows a bottom contact type TFT. Each of these TFTs includes a substrate 301, a gate electrode 302, a gate insulating film 303, an active layer 304, and source / drain electrodes 305.

  Silicon or silicon compounds are widely used for the active layers of these transistors. Silicon single crystals are used for high-frequency amplifying elements and integrated circuit elements that require high-speed operation, and amorphous (amorphous) elements are required for large-area liquid crystal driving elements that require low-speed operation. ) Silicon is used.

  A flexible display expected as a substitute for paper is required to use a flexible substrate. A representative example thereof is an organic substrate such as plastic. However, since such a substrate generally has a low heat-resistant temperature of 120 to 180 ° C., a reduction in process temperature is required. CVD is widely used for the production of amorphous silicon thin films. In particular, in plasma CVD, plasma decomposes silane, which is a raw material gas, so that it can be formed at a lower temperature than thermal CVD, but still 200 to 300 ° C. The reaction temperature is required.

In recent years, an amorphous oxide semiconductor InGaZnO ₄ that can be deposited at room temperature and has a field effect mobility higher than that of amorphous silicon has been announced, and its potential as an active layer of a TFT has been shown (see Patent Document 1). Since this material has a property of easily dissolving in acid, patterning by wet etching with acid is possible. Further, it has been reported that materials such as oxides containing Zn and Sn also function as an active layer at room temperature (see Non-Patent Document 1).
JP 2006-165532 A Appl. Phys. Lett. , Vol. 86, 2005, 013503

  When the TFT is used for an element such as a memory, a metal is often used as an electrode material. On the other hand, when a TFT is used for a display device or the like, a transparent conductive film is used as a material except for an extraction electrode other than the display area. As this transparent conductive film, tin-doped indium oxide (ITO) is widely known, has alkali resistance, and can be patterned by etching with acid. The etching rate greatly depends on the crystallinity, film thickness, and film forming method of the material. In particular, the etching rate is extremely fast for an amorphous or microcrystalline film formed by film formation at room temperature.

When an attempt was made to produce a TFT by combining such a transparent conductive film such as ITO and an amorphous oxide semiconductor such as InGaZnO ₄ , both were easily dissolved in an acid, and individual patterning was difficult. Several methods have been proposed to solve this problem. Here, for convenience, in the bottom gate type top contact TFT, the active layer is referred to as a lower layer, and the source / drain electrode layer is referred to as an upper layer, and in the bottom gate type bottom contact TFT, the source / drain electrode layer is referred to as a lower layer. The active layer will be called the upper layer.

  In one of the proposed methods, after forming a lower layer and patterning it by etching, only a resist pattern was formed thereon to form an upper layer, and at the same time the resist was removed and applied to the resist This is a so-called lift-off process in which the upper layer is patterned by removing the upper layer. Although there is an advantage that patterning can be performed regardless of the properties of the film formed on the resist, there are problems such as pattern loss due to missing patterns and residues, and pattern defects due to reattachment of the peeled upper layer film pieces. It was. In the lift-off process, the effect of accelerating lift-off by pulverizing the inorganic thin film on top of the resist by dipping the substrate in a solvent and applying ultrasonic waves can be expected. In some cases, an unexpected peeling occurred from the portion, and depending on the combination of materials, there was a problem caused by using ultrasonic waves. In addition, the pattern forming portion is a process in which the upper layer material is embedded in the opening of the resist. Therefore, if the pattern is thinned, the upper layer material is difficult to enter the narrowed opening. Difficulties were associated with miniaturization.

  Another proposed method is to select a material that has a difference in dissolution rate (etching rate), or to fire the electrode, even if both the upper layer and the lower layer have the property of dissolving in acid. There is a method of crystallizing or improving crystallinity by performing the etching of the upper layer on the assumption that the lower layer is etched to some extent, but if there is in-plane variation in the film thickness or etching rate, it will be produced As a result, variations in the performance of the obtained devices occurred, and application to a large area was difficult. In addition, there is a problem in that the structure and subsequent processes are limited, for example, a material having a low etching rate must be disposed in the lower layer. Furthermore, when crystallization by firing cannot be expected, such as when using an organic substrate having low heat resistance, the difference in etching rate is extremely small, and individual patterning is difficult.

  In order to solve the above problems, a main invention of the present invention is a method of manufacturing a bottom gate type top contact type field effect transistor, wherein the source / drain electrodes and the active layer are etched by at least the same type of etchant. In the case of a material having possible properties, after patterning the active layer, a first photoresist having an inverted pattern of the source / drain electrode is formed, a source / drain electrode layer is formed, and the first photoresist is formed The second photoresist is further applied while leaving the film, and the second photoresist is processed into the shape of the source / drain electrode, and then the source is formed using the second photoresist as a mask and the first resist as an etching stopper. The source / drain electrodes are patterned by etching the drain / drain electrode layer. After form a method of manufacturing a field effect transistor formed by removing the first and second photoresist.

  Another main invention is a method for manufacturing a bottom gate type bottom contact type field effect transistor, in which the source / drain electrodes and the active layer are materials that can be etched by at least the same type of etchant. Then, after forming the source / drain electrode pattern, a first photoresist having an inverted pattern of the active layer pattern is formed, an active layer is formed, and the second photoresist is left while leaving the first photoresist. Then, the second photoresist is processed into the shape of the active layer pattern, and then the active layer is patterned by etching using the second photoresist as a mask and the first photoresist as an etching stopper. After forming the first and second photoresists. It is a manufacturing method of the gate bottom contact type field effect transistor.

  By using these manufacturing methods, even when the source / drain electrodes and the active layer are etched by the same type of etchant, the etching method can be applied to patterning, and the lift-off method with a low yield is used. A field effect transistor can be manufactured without any problems.

Another invention is to use materials that are transparent to visible light as materials for the substrate, gate electrode, source electrode, drain electrode, and active layer. Thereby, a TFT transparent to visible light can be manufactured by a simple process not using a lift-off process, and the aperture ratio can be increased when this is applied to a liquid crystal display element or the like. As a material transparent to visible light, ITO is used for an electrode, and an amorphous oxide or an amorphous oxide containing microcrystals having an electron carrier density of less than 10 ¹⁸ / cm ³ is used for an active layer. Furthermore, if this manufacturing method that does not use a lift-off process is applied, a TFT array transparent to visible light having high transistor characteristics can be manufactured, and if photolithography is used for all patterning, the TFT array can be manufactured with high accuracy. Can be made to density. Furthermore, a bent TFT can be manufactured by forming each layer at room temperature.

  According to the present invention, in the TFT manufacturing method, in the patterning by one etching in the state where the electrode and the active layer are in contact, one etching can be performed without causing damage due to overetching or the like such as cutting the other. it can. In addition, since the patterning process does not use lift-off, a high yield is expected at the time of manufacturing the TFT array, and the TFT array can be miniaturized. Further, by using a substrate, an electrode, and an active layer that are transparent to visible light, TFTs that are transparent to visible light can be manufactured with high accuracy and high density.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the drawings referred to in the following description of the embodiments are for explaining the configuration of the present invention, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the actual ones. The present invention is not limited to these.

  Embodiments of the present invention will be described in detail below with reference to FIGS. Here, unless otherwise specified, a method for manufacturing a bottom-gate top-contact field effect transistor is described.

First, the substrate 101 is prepared (FIG. 1A). The material of the substrate 101 is not particularly limited as long as it can be introduced into the vacuum vessel and can be easily handled, but a lightweight and flexible substrate is preferable. A material transparent to visible light is preferable. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE) Polypropylene (PP), nylon and the like can be used. However, surface treatment with UV, plasma, or the like may be performed to improve adhesion. In some cases, it may be thinly coated with SiO ₂ or the like.

  Next, a gate electrode layer is formed. The material of the gate electrode layer is not particularly limited, but a material that is transparent to visible light is preferable. It is preferable to use tin-doped indium oxide (ITO) as the material because the characteristics as an electrode are enhanced. The film forming method is not particularly limited, but a sputtering method capable of uniformly forming a film over a large area is desirable. The film forming method is the same except for the case where a resist is formed.

  Next, a resist pattern is formed on the formed gate electrode layer using general photolithography.

  Subsequently, the gate electrode layer is etched using the resist pattern as a mask. An etching method is not limited, but a method using wet etching is simple because subsequent resist removal is easy. After the etching is completed, the resist is removed using an appropriate solvent to obtain a patterned gate electrode 102 (FIG. 1B).

Next, a gate insulating film 103 is formed (FIG. 1C). The material of the gate insulating film is not particularly limited, but a material that is transparent to visible light and exhibits a high dielectric constant is desirable. Various materials such as SiO ₂ , SiON, HfO ₂ , Y ₂ O ₃ are widely known. The film forming method is not particularly limited. As described above, a sputtering method that can form a film at room temperature and can form a film over a large area uniformly is preferable. It is preferable to mask the lead electrode of the gate electrode provided as a contact for applying a voltage from the outside of the TFT at the time of film formation, because it is not necessary to pattern the gate insulating film when forming the gate insulating film. . The method of the mask is not particularly limited. However, since the extraction electrode generally has a large pattern size, a method such as covering with a stencil mask before film formation is simple.

Subsequently, an active layer is formed. The material for the active layer is preferably an amorphous oxide or an amorphous oxide containing microcrystals having an electron carrier density of less than 10 ¹⁸ / cm ³ . Further, a material that has alkali resistance and can be etched with an acid is desirable. It is important in the present invention that the active layer can achieve a desired carrier concentration by controlling the amount of oxygen deficiency.

  Next, a photoresist is formed on the active layer, the resist is processed into a desired pattern shape using general photolithography, and then the active layer is etched using the resist as a mask. The etching method is not limited, but wet etching using an acid is simple. After the etching is completed, the resist is removed using an appropriate solvent to obtain an active layer 104 pattern (FIG. 1D).

  Subsequently, a first photoresist 105 is formed on the substrate having the active layer pattern, and a first photomask is used by using a photomask in which patterns for source / drain electrodes are engraved. The photoresist is patterned so as to have an inverted shape of the electrodes (FIG. 1E).

  Next, a source / drain electrode layer 106 is formed (FIG. 2A). The material is not particularly limited, but a material that is transparent to visible light is preferable. When tin-doped indium oxide (ITO) is used as a material, the characteristics as an electrode may be improved, but other materials may be used.

  Next, a second photoresist 107 is formed on the formed source / drain electrode layer, and a second photomask is used using a photomask in which a pattern for the source / drain electrode is engraved. The photoresist is patterned so as to have an electrode shape (FIG. 2B). Regardless of the type of resist, if a positive type resist is used for the first photoresist, a negative type resist is used for the second photoresist, and a photomask engraved with patterns for the source / drain electrodes is formed. Can be reused. When a negative type photoresist is used for the first photoresist, the same effect can be obtained by using a positive type photoresist for the second photoresist. Since it is desirable that the second photoresist covers the entire area where the first photoresist does not exist as viewed from above the substrate without gaps, the second photoresist is first in consideration of alignment accuracy. The pattern of the second photoresist may be shaped so that it slightly overlaps the photoresist. This case can be dealt with by swelling the second photoresist or using a photomask having a larger pattern size during exposure of the second photoresist.

  Subsequently, the source / drain electrode layer 106 is etched using an acidic etchant using the formed second photoresist 107 as a mask (FIG. 2C). At this time, the first photoresist 105 functions as an etching stopper layer. The etchant for etching the source / drain electrode layer 106 may be the same as or different from the etchant for etching the active layer. Further, the concentration may be the same or different. Examples of the acidic etchant include, but are not limited to, those containing hydrochloric acid or oxalic acid as a main component.

  Finally, the first photoresist 105 and the second photoresist 107 are removed using an appropriate solvent (FIG. 2D).

  In this way, a bottom gate type top contact type TFT is completed (FIG. 2D).

  When fabricating a bottom gate type bottom contact type TFT, after forming a gate insulating film, a source / drain electrode layer is formed and patterned, a first photoresist having an inverted pattern of the active layer is formed, and then an active layer is formed. A bottom gate type is formed by forming a second photoresist having an active layer pattern thereon, patterning the active layer by etching, and removing the first and second photoresists. A bottom contact type TFT is completed. Other details are the same as the manufacturing method of the bottom gate type top contact type TFT.

  Hereinafter, an example of a manufacturing method of a bottom gate type top contact type TFT will be described with reference to FIGS. 1 and 2, but the present invention is not limited to this.

A substrate 101 made of PEN was prepared (FIG. 1A), and SiO ₂ was formed to a thickness of 20 nm using a general sputtering method.

  The gate electrode layer is formed at room temperature using a general sputtering method, and patterned into the shape of the gate electrode using general photolithography and an etchant mainly composed of hydrochloric acid. 102 was formed (FIG. 1B).

Next, using a stencil mask that masks the extraction electrode of the gate electrode, SiO ₂ was sputtered at room temperature to form the gate insulating film 103 (FIG. 1C).

Next, InGaZnO ₄ was sputtered at room temperature as the active layer 104, and patterned into a desired active layer shape by wet etching using general photolithography and an etchant containing hydrochloric acid as a main component (see FIG. 1 (d)).

  Next, a positive type photoresist was spin-coated as the first photoresist 105, and the resist was processed into the inverted shape of the source / drain electrodes using general photolithography (FIG. 1 (e)).

  Next, a sputtering method is used to form an ITO film at room temperature as the source / drain electrode layer 106 (FIG. 2A), and a negative photoresist is spin-coated thereon as a second photoresist 107. The second photoresist was processed into the shape of the source / drain electrodes using typical photolithography (FIG. 2B).

  Next, using the second photoresist 107 pattern as a mask, the ITO thin film was wet-etched and patterned using an etchant mainly composed of hydrochloric acid (FIG. 2C), and the photoresist was removed using acetone. A bottom gate type top contact type TFT transparent to visible light was completed (FIG. 2D).

  An example of a method for manufacturing a bottom gate type bottom contact type TFT will be described below with reference to FIGS.

A substrate 201 made of PEN was prepared (FIG. 3A), and SiO ₂ was formed to a thickness of 20 nm using a general sputtering method.

  The gate electrode 202 is formed into a film at room temperature using a general sputtering method, and patterned into the shape of the gate electrode using general photolithography and an etchant mainly composed of hydrochloric acid. Was formed (FIG. 3B).

Next, using a stencil mask that masks the extraction electrode of the gate electrode, SiO ₂ was sputtered at room temperature to form the gate insulating film 203 (FIG. 3C).

Next, ITO is sputter-deposited at room temperature as a material for the source / drain electrode layer 206, and ITO is formed on the source / drain electrode by wet etching using general photolithography and an etchant mainly composed of hydrochloric acid. Patterning into a shape yielded a source / drain electrode (FIG. 3D).
Next, a positive type photoresist was spin-coated as the first photoresist 205, and the resist was processed into an inverted shape of the active layer pattern using general photolithography (FIG. 3E).

Next, InGaZnO ₄ is used as the material of the active layer 204, and this is formed at room temperature using a sputtering method (FIG. 3A), and a negative photoresist is spin-coated thereon as the second photoresist 207. Then, the resist was processed into the shape of the active layer pattern using general photolithography (FIG. 3B).

Next, using the second photoresist 207 pattern as a mask, the InGaZnO ₄ thin film is wet-etched and patterned using an etchant containing hydrochloric acid as a main component (FIG. 3C), and first and second using acetone. This photoresist was removed (FIG. 3D), and a bottom gate type bottom contact type TFT transparent to visible light was completed (FIG. 3D).

  The TFTs thus produced were not observed to have overetching in each layer, and were manufactured with a high yield. The TFTs exhibited transistor characteristics suitable for good display applications.

  The present invention can be used for semiconductor devices, display devices, and the like.

It is an example which shows the manufacturing method of the bottom gate type top contact type thin-film transistor of this invention. It is an example which shows the manufacturing method of the bottom gate type top contact type thin-film transistor of this invention. 1 is an example showing a manufacturing method of a bottom gate type bottom contact type thin film transistor of the present invention. 1 is an example showing a manufacturing method of a bottom gate type bottom contact type thin film transistor of the present invention. It is a schematic diagram showing a cross section of a general bottom gate type top contact type thin film transistor. It is a schematic diagram showing a cross section of a general bottom gate type bottom contact type thin film transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Substrate 102 Gate electrode 103 Gate insulating film 104 Active layer 105 First photoresist 106 Source / drain electrode layer 107 Second photoresist

Claims (12)

Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate including the gate electrode;
Forming an active layer pattern on the substrate including the gate insulating film;
Forming a first resist pattern on the substrate including the active layer pattern in the shape of an inverted pattern of the source / drain electrodes;
Forming a source / drain electrode layer on the substrate including the first resist pattern;
Forming a second resist pattern in the shape of the source / drain electrode on the substrate including the source / drain electrode layer;
Using the second resist pattern as a mask, the source / drain electrode layer is patterned with an acidic etchant to form a source / drain electrode,
The first and second resist patterns are removed. A method of manufacturing a field effect transistor. In the manufacturing method of the field effect transistor according to claim 1,
The active layer pattern is formed by forming an active layer and then patterning the active layer by etching, and etching the active layer with an acidic etchant. Production method. In the manufacturing method of the field effect transistor according to claim 1 or 2,
The method of manufacturing a field effect transistor, wherein the first resist pattern is formed by photolithography after forming a photoresist film. In the manufacturing method of the field effect transistor according to any one of claims 1 to 3,
The method of manufacturing a field effect transistor, wherein the second resist pattern is formed by photolithography after forming a photoresist. Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate including the gate electrode;
Forming source / drain electrodes on the substrate including the gate insulating film;
Forming a first resist pattern on the substrate including the source / drain electrodes in the shape of an inverted pattern of an active layer pattern;
Forming an active layer on the substrate including the first resist pattern;
Forming a second resist pattern in the shape of the active layer pattern on the substrate including the active layer;
Using the second resist pattern as a mask, the active layer is etched with an acidic etchant to form an active layer pattern,
The first and second resist patterns are removed. A method of manufacturing a field effect transistor. In the manufacturing method of the field effect transistor according to claim 5,
The source / drain electrode is formed by forming a source / drain electrode layer and then patterning by etching, and the source / drain electrode layer is etched with an acidic etchant. Manufacturing method. In the manufacturing method of the field effect transistor according to claim 5 or 6,
The method of manufacturing a field effect transistor, wherein the first resist pattern is formed by photolithography after forming a photoresist film. In the manufacturing method of the field effect transistor according to any one of claims 5 to 7,
The method of manufacturing a field effect transistor, wherein the second resist pattern is formed by photolithography after forming a photoresist.   The substrate is made of a material transparent to visible light, the gate electrode and the source / drain electrodes are formed of a conductive film transparent to visible light, and the active layer is transparent to visible light The method for manufacturing a field effect transistor according to claim 1, wherein:   10. The method of manufacturing a field effect transistor according to claim 1, wherein the material constituting the conductive film transparent to visible light is tin-doped indium oxide (ITO). 11. The material constituting the active layer is an amorphous oxide or an amorphous oxide containing microcrystals having an electron carrier density of less than 10 ¹⁸ / cm ^3. The manufacturing method of the field effect transistor of description.   A field effect transistor manufactured by the manufacturing method according to claim 1.

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