JP2007123700A - Method of patterning oxide semiconductor and method of manufacturing thin-film transistor - Google Patents

Method of patterning oxide semiconductor and method of manufacturing thin-film transistor Download PDF

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JP2007123700A
JP2007123700A JP2005316403A JP2005316403A JP2007123700A JP 2007123700 A JP2007123700 A JP 2007123700A JP 2005316403 A JP2005316403 A JP 2005316403A JP 2005316403 A JP2005316403 A JP 2005316403A JP 2007123700 A JP2007123700 A JP 2007123700A
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thin film
etching
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Masato Kon
真人 今
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Toppan Printing Co Ltd
凸版印刷株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To pattern each of layers without using a lift-off process, and to provide a thin-film transistor to be manufactured using such a process. <P>SOLUTION: In the thin-film transistor in which an InGaZnO4 thin film is used as an active layer and an ITO thin film is used as source-drain electrodes, this method has a process of patterning the ITO thin film provided on a substrate by etching, wherein the InGaZnO4 thin film provided on the patterned ITO thin film is patterned by etching. In this case, the two kinds of thin films are etched so that the etching is performed at different etching times while using etching liquids or etching gases of the same kind and same density, or while changing the density and not changing the other conditions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for patterning a laminated thin film in which an InGaZnO 4 thin film and a Sn-doped indium oxide (ITO) thin film that can be used as elements constituting an electronic circuit are directly laminated, and a method for producing a thin film transistor using the same.

  Field effect transistors are used as various switching elements such as unit electronic elements of semiconductor memory integrated circuits, high frequency signal amplifying elements, liquid crystal driving elements, and the thinned transistors are well known as thin film transistors (hereinafter referred to as TFTs). .

  Silicon or silicon compounds are widely used for the active layers of these TFTs. Single-crystal silicon is used for high-frequency amplifying elements and integrated circuit elements that require high-speed operation, and amorphous silicon is used for display elements that are sufficient for low-speed operation due to the demand for large area. .

On the other hand, a TFT using a flexible substrate is required for a flexible display. Since a substrate for manufacturing such a TFT generally has a low heat-resistant temperature, further reduction in the process temperature for forming a thin film is required.
CVD is widely used for the production of the above-described amorphous silicon thin film. In particular, in plasma CVD, plasma decomposes silane, which is a raw material gas, so that the film can be formed at a temperature lower than that in thermal CVD.
However, this plasma CVD thin film formation requires a reaction temperature of 200 to 300 ° C. For this reason, it was difficult to form a thin film on a substrate having low heat resistance.

  In recent years, an oxide semiconductor InGaZnO 4 that can be formed at room temperature and has a field-effect mobility equal to or higher than that of amorphous silicon has been proposed, and the possibility as an active layer of a thin film transistor has been shown (see Non-Patent Document 1).

K. Nomura, H .; Ohta, A .; Takagi, T .; Kamiyama, M .; Hirano, H .; Hosono: Nature 432 (2004) 488.

  InGaZnO 4 described in Non-Patent Document 1 is a material known as a transparent conductive film. By controlling the oxygen partial pressure during film formation, oxygen vacancies serving as carrier sources are reduced, and off current Has been successfully reduced. Further, since an amorphous state can be easily obtained, it is suitable for application to a flexible display. Further, since it is transparent, a transparent thin film transistor can be formed by using a transparent material for the gate insulating film, the gate electrode, and the source / drain electrodes.

  For the patterning of InGaZnO 4, the same etching method as that for the ITO film which is a transparent conductive film can be used. That is, it is soluble in common acids and insoluble in alkali. Therefore, the etching technique cultivated with ITO is basically applicable to the patterning of InGaZnO 4.

  However, in the case of a thin film transistor in which an InGaZnO 4 thin film is used as an active layer and ITO is used as a source / drain electrode, a laminated structure in which one part is directly laminated on the other part. When patterning with different patterns for both the parts, if one part is formed and then the other part is formed by etching in the same manner, the previously formed thin film part is used to etch the subsequent thin film part. Since it was etched by the etchant, it was not possible to obtain a laminated substrate having a target pattern. Therefore, after forming one part, patterning is performed by combining a plurality of different processes, such as using a lift-off process for patterning the other part, which is inefficient.

  In addition, the lift-off process, which is a forming means other than etching, has a problem that it takes time for the lift-off and a fine pattern cannot be cut off.

  The present invention has been made in view of such a problem. By patterning both an ITO thin film as an electrode layer and an InGaZnO 4 thin film as a semiconductor active layer by etching, oxidation can be performed without using a process unsuitable for mass production such as lift-off. An object of the present invention is to manufacture a thin film semiconductor transistor.

In order to achieve the above object, first, the first invention is a process of patterning an ITO thin film provided on a substrate by etching, and patterning an InGaZnO 4 thin film provided on the patterned ITO thin film by etching. In this case, the oxide semiconductor thin film pattern forming method is characterized in that the two kinds of thin films use the same kind of etching solution or etching gas, and different concentrations of etching solution or etching gas are used.
As a result of studying the etching of the amorphous ITO thin film and the amorphous InGaZnO 4 thin film, it was found that the two can be separately etched by appropriately selecting the concentration of the etching solution. As a result, when the concentration is high, the influence of the base film thickness error becomes larger with respect to the etching time error.
On the other hand, if the concentration is low, the etching time becomes long, so that the throughput decreases. Therefore, when etching the ITO thin film, an etching solution having a high concentration is used. Next, when etching InGaZnO 4, both are patterned by etching using the same type and a low concentration etching solution. It became possible.
Here, when the film thickness of InGaZnO 4 is d, the ITO thin film is patterned by 0.25 d extra thicker than the necessary minimum amount, so that the ITO film thickness is not reduced below the required minimum amount at the end of etching. A laminated substrate can be obtained.

According to a second aspect of the present invention, when the ITO thin film provided on the substrate is patterned by etching, and the InGaZnO 4 thin film provided on the patterned ITO thin film is patterned by etching, the two kinds of thin films The oxide semiconductor thin film pattern forming method is characterized in that etching is performed at different etching times using the same kind and the same concentration of etching solution or etching gas.
Since an etching solution or etching gas having the same etching concentration can be used, the management of the etching solution or etching gas becomes easy.

The third invention of the present invention is the oxide semiconductor thin film pattern forming method according to claim 1 or 2, wherein the ITO film is crystalline.
Crystalline ITO is about 1-2 orders of magnitude slower in etching rate than amorphous ITO. As a result, the selectivity with InGaZnO 4 is also increased by 1 to 2 digits, and the etching process window can be widened.

  A fourth invention of the present invention is the pattern forming method according to any one of claims 1 to 3, wherein a wet etching technique is used in the etching. By using wet etching, an expensive etching apparatus necessary for dry etching becomes unnecessary, and the manufacturing cost can be reduced.

The fifth aspect of the present invention is the pattern forming method according to claim 4, wherein an acid containing hydrochloric acid as a main component is used as an etchant in the etching.
The effect of the present invention is maximized when hydrochloric acid is used as the etching solution. Hydrochloric acid is easily available, and it is easily neutralized with sodium hydroxide to form water and salt.

A sixth invention of the present invention is a method of manufacturing a top gate type thin film transistor using a non-single crystal InGaZnO 4 thin film as an active layer and an ITO thin film as a source electrode and / or a drain electrode. A step of forming an electrode layer, a step of patterning the source / drain electrode layer, a step of forming an active layer, a step of patterning the active layer, a step of forming a gate insulating film, and a gate electrode layer And a step of patterning the gate electrode layer, wherein the active layer and the source / drain electrode layer are both patterned by etching. It is a manufacturing method.
With such a configuration, a top-gate transparent thin film transistor using a transparent oxide semiconductor can be formed without using a lift-off process.

A seventh invention of the present invention is a method of manufacturing a bottom gate type bottom contact thin film transistor using a non-single crystal InGaZnO 4 thin film as an active layer and using an ITO thin film as a source electrode and / or a drain electrode. A step of forming an electrode layer, a step of patterning the gate electrode layer, a step of forming a gate insulating film, a step of forming a source / drain electrode layer, a step of patterning the source / drain electrode layer, In a method for manufacturing a bottom gate type bottom contact thin film transistor comprising a step of forming an active layer and a step of patterning the active layer, at least the active layer and the source / drain electrodes are both patterned by etching. This is a method of manufacturing a thin film transistor.
With such a configuration, a bottom-gate bottom-contact transparent thin film transistor using a transparent oxide semiconductor can be formed without using a lift-off process.

  From the above configuration, the present invention has the following effects.

  By patterning both the ITO thin film and the InGaZnO 4 thin film directly laminated thereon by etching, a transparent oxide semiconductor thin film transistor can be manufactured without using a process unsuitable for mass production such as lift-off.

  Embodiments of the present invention will be described in detail below with reference to FIGS.

  An example of the thin film transistor of the present invention is shown in FIG. Although the bottom gate type bottom contact thin film transistor is described in the figure and this example, a top gate type may be used.

  First, the substrate 1 is prepared (FIG. 2A). The material of the substrate 1 is preferably a lightweight and flexible plastic substrate. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE) Polypropylene (PP), nylon and the like can be used. However, surface treatment with UV, plasma, or the like may be performed to improve adhesion.

  Next, the gate electrode 2 is formed on the substrate 1 (FIG. 2B). The material of the gate electrode is not limited, but a material with high transmittance is desirable for manufacturing a transparent thin film transistor. ITO is preferable from the viewpoints of transmittance and conductivity. This does not apply when transparency is not an issue. The production method does not matter. Further, since the gate electrode is not in direct contact with the active layer, the patterning method is not limited. Examples include reactive mask vapor deposition (including sputtering) of metals, alloys, and transparent conductive films.

  Next, the gate insulating film 3 is produced (FIG. 2C). The material, manufacturing method, and patterning method of the gate insulating film 3 are not limited. For example, SiO2, SiN, SiON or the like can be used, but it is preferable to use a high dielectric constant (high-k) material such as HfO2, Y2O3, Ta2O5.

  Next, source / drain electrodes 4 are formed (FIG. 2D). ITO is used as the material of the source / drain electrodes. If the thickness of the ITO film to be laminated later is d, the thickness of the ITO film does not fall below the required minimum amount of the ITO film at the end of etching if the thickness is increased by 0.25 d more than the required minimum amount. Any film forming method is acceptable. It is desirable to use an acid resistant resist for patterning. Either dry or wet etching can be applied to the etching. Etching liquid and etching gas are not limited, but wet etching using hydrochloric acid is desirable from the environmental viewpoint and in order to obtain the maximum effect. When the ITO film is crystallized, etching is facilitated by using a mixed solution of 6M hydrochloric acid heated to 50 ° C. and 6M aqueous ferric chloride solution. If the ITO film is not crystallized, it is sufficient to treat at room temperature using only 1M hydrochloric acid. After the etching is completed, the resist is removed.

Next, the active layer 5 is formed (FIG. 2E). InGaZnO 4 is used as the material. The formation method is preferably a sputtering method capable of uniform film formation over a large area, and can be easily formed by using an InGaZnO 4 target. A film may be formed by a reactive sputtering method using an alloy target. Other methods such as pulsed laser deposition (PLD) are possible without being limited to sputtering. It is desirable to use an acid resistant resist for patterning. Either dry or wet etching can be applied to the etching. Etching liquid and etching gas are not limited, but wet etching using hydrochloric acid is desirable from the environmental viewpoint and in order to obtain the maximum effect. At this time, if the concentration of hydrochloric acid is high, the time until completion of etching is shortened, and an error in processing time has a non-negligible effect on the film thickness of the underlying ITO film, so that the ITO film may be completely etched in some cases. Accordingly, it is necessary to make the concentration sufficiently thin, and it is preferably about 0.1 M with respect to the InGaZnO 4 active layer having a thickness of 50 nm. After the etching is completed, the resist is removed.
As described above, the thin film transistor is completed (FIG. 1).

PEN was used as the substrate 1 (see FIG. 2A), and an ITO layer was formed on the substrate 1 with a thickness of 100 nm by dc magnetron sputtering, and then patterned to form a gate electrode 2 (FIG. 2 ( b)). The gate electrode 2 was formed by processing the ITO layer by wet etching using a general photolithography method.
Next, a 300 nm thick SiO 2 film was formed by plasma CVD at a substrate temperature of 50 ° C. or lower to form a gate insulating film 3 (see FIG. 2C).
Next, an ITO layer having a thickness of 100 nm is formed on the gate insulating film 3 by a dc magnetron sputtering method, a photoresist is used, and the resist is processed into the shape of an electrode by ordinary photolithography. The ITO thin film was etched for 2 minutes using hydrochloric acid to form the source / drain electrodes 4, and the resist was peeled off (see FIG. 2D).
Finally, an InGaZnO 4 thin film is formed to a thickness of 50 nm by rf magnetron sputtering using an InGaZnO 4 target, and the resist is processed into a semiconductor pattern by ordinary photolithography using a photoresist. The InGaZnO 4 thin film was etched for 3 minutes and then the resist was removed to form a patterned active layer 4 (see FIG. 2E).
As described above, a bottom-gate bottom contact thin film transistor having a channel length of 50 μm and a channel width of 800 μm was completed (see FIG. 1).

FIG. 5 is an explanatory diagram showing an upper surface and a side surface of a thin film transistor of the present invention. Explanatory drawing which shows an example of the manufacturing process of the thin-film transistor of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Gate electrode 3 ... Gate insulating film 4 ... Source / drain electrode 5 ... Active layer

Claims (7)

  1.   When the ITO thin film provided on the substrate is patterned by etching, and the InGaZnO 4 thin film provided on the patterned ITO thin film is patterned by etching, the two kinds of thin films are made of the same kind of etching solution or etching gas. And a method of forming an oxide semiconductor thin film pattern, wherein different etching solutions or etching gases are used.
  2.   Etching the ITO thin film provided on the substrate by etching, and patterning the InGaZnO 4 thin film provided on the patterned ITO thin film by etching, the two kinds of thin films are of the same type and the same concentration. Alternatively, an oxide semiconductor thin film pattern forming method, wherein etching is performed at different etching times using an etching gas.
  3.   The method for forming an oxide semiconductor thin film pattern according to claim 1, wherein the ITO film is crystalline.
  4.   4. The oxide semiconductor thin film pattern forming method according to claim 1, wherein the pattern forming method uses a wet etching technique.
  5.   5. The method of forming an oxide semiconductor thin film pattern according to claim 4, wherein the wet etching uses an etching solution using an acid containing hydrochloric acid as a main component.
  6.   A method of manufacturing a top-gate thin film transistor in which an active layer is a non-single-crystal InGaZnO 4 thin film and a source electrode or / and a drain electrode are ITO thin films, and a step of forming a source / drain electrode layer on a substrate; A step of patterning the source / drain electrode layer, a step of forming an active layer, a step of patterning the active layer, a step of forming a gate insulating film, a step of forming a gate electrode layer, and the gate electrode A method of manufacturing a top gate thin film transistor, comprising: patterning at least the active layer and the source / drain electrode layer by etching under different etching conditions.
  7.   A method of manufacturing a bottom gate type bottom contact thin film transistor in which the active layer is a non-single-crystal InGaZnO 4 thin film, the source electrode or / and the drain electrode is an ITO thin film, and a step of forming a gate electrode layer on a substrate; A step of patterning the gate electrode layer, a step of forming a gate insulating film, a step of forming a source / drain electrode layer, a step of patterning the source / drain electrode layer, a step of forming an active layer, A method of manufacturing a bottom gate type bottom contact thin film transistor comprising: patterning an active layer, wherein at least the active layer and the source / drain electrode are patterned by etching under different etching conditions. .
JP2005316403A 2005-10-31 2005-10-31 Method of patterning oxide semiconductor and method of manufacturing thin-film transistor Pending JP2007123700A (en)

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JP2008041695A (en) * 2006-08-01 2008-02-21 Canon Inc Etching method of oxide
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US8039405B2 (en) 2008-02-01 2011-10-18 Ricoh Company, Ltd. Conductive oxide-deposited substrate and method for producing the same, and MIS laminated structure and method for producing the same
EP2086014A2 (en) 2008-02-01 2009-08-05 Ricoh Company, Limited Conductive oxide-deposited substrate and method for producing the same, and MIS laminated structure and method for producing the same
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