JP2008171989A - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for patterning source/drain electrodes and an active layer by etching without using any lift-off methods in the case of a material having properties capable of etching with at least the same type of etchant. <P>SOLUTION: A light-shielding film having oxidation resistance properties is further provided after forming an active layer pattern in a manufacturing process of a bottom gate top contact type field effect transistor and after forming source/drain electrode patterns in a manufacturing process of a bottom gate bottom contact type field effect transistor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a field effect transistor used for a semiconductor device, a display device, and the like and a manufacturing method thereof.

  Field effect transistors are used as various switching elements such as unit electronic elements, high-frequency signal amplifying elements, and liquid crystal driving elements in semiconductor memory integrated circuits, and the thinned transistors are well known as thin film transistors (TFTs).

  In general, in a TFT, when a substrate is disposed below, a structure in which a gate electrode is disposed below a source / drain electrode is a bottom gate type, and a structure in which a gate electrode is disposed above a source / drain electrode is a top gate. It is called a type TFT.

  Further, in the bottom gate type, the structure in which the source / drain electrode is disposed on the active layer (also referred to as the channel layer) is a top contact type, and the structure in which the source / drain electrode is disposed under the active layer is a bottom contact. Called a type.

  FIG. 5 shows a top contact type TFT and FIG. 6 shows a bottom contact type TFT. Each of these TFTs includes a substrate 301, a gate electrode 302, a gate insulating film 303, an active layer 304, and source / drain electrodes 305.

  Silicon or silicon compounds are widely used for the active layers of these transistors. Silicon single crystals are used for high-frequency amplifying elements and integrated circuit elements that require high-speed operation, and for liquid crystal driving elements that are sufficient for low-speed operation, amorphous (amorphous) ) Silicon is used.

  A flexible display expected as a substitute for paper is required to use a flexible substrate. A representative example thereof is an organic substrate such as plastic. However, since such a substrate generally has a low heat-resistant temperature of 120 to 180 ° C., a reduction in process temperature is required. CVD is widely used for producing an amorphous silicon thin film. In particular, plasma CVD decomposes silane, which is a raw material gas, so that it can be formed at a lower temperature than thermal CVD, but still 200 to 300 ° C. The reaction temperature is required.

In recent years, an amorphous oxide semiconductor InGaZnO ₄ that can be formed at room temperature and has a field effect mobility higher than that of amorphous silicon has been announced, and the possibility as an active layer of a TFT has been shown (see Patent Document 1). Since this material has a property of easily dissolving in acid, patterning by wet etching with acid is possible. In addition, it has been reported that materials such as oxides containing Zn and Sn also function as an active layer at room temperature (see Non-Patent Document 1).
JP 2006-165532 A Appl. Phys. Lett. , Vol. 86, 2005, 013503

  When the TFT is used for an element such as a memory, a metal is often used as an electrode material. On the other hand, when a TFT is used for a display device or the like, a transparent conductive film is used as a material except for an extraction electrode other than the display area. As this transparent conductive film, tin-doped indium oxide (ITO) is widely known, has alkali resistance, and can be patterned by etching with acid. The etching rate greatly depends on the crystallinity, film thickness, and film forming method of the material. In particular, the etching rate is extremely fast for an amorphous or microcrystalline film formed by film formation at room temperature.

When an attempt was made to produce a TFT by combining such a transparent conductive film such as ITO and an amorphous oxide semiconductor such as InGaZnO ₄ , both were easily dissolved in acid, and individual patterning was difficult. Several methods have been proposed to solve this problem. Here, for convenience, in the bottom gate type top contact TFT, the active layer is referred to as the lower layer, and the source / drain electrode layer is referred to as the upper layer, and in the bottom gate type bottom contact TFT, the source / drain electrode layer is referred to as the lower layer. The active layer will be called the upper layer.

  In one of the proposed methods, after forming a lower layer and patterning it by etching, only a resist pattern was formed thereon to form an upper layer, and at the same time the resist was removed and applied to the resist This is a so-called lift-off process in which the upper layer is patterned by removing the upper layer. Although there is an advantage that patterning can be performed regardless of the properties of the film formed on the resist, there are problems in that the yield is lowered, such as pattern loss and generation of residues, and pattern defects due to reattachment of the peeled upper layer film pieces. It was. In the lift-off process, the effect of accelerating lift-off by pulverizing the inorganic thin film on top of the resist by immersing the substrate in a solvent and applying ultrasonic waves can be expected. However, organic materials are used for organic substrates and other parts other than resist. In some cases, an unexpected peeling occurred from the portion, and depending on the combination of materials, there was a problem caused by using ultrasonic waves. In addition, the pattern forming portion is a process in which the upper layer material is embedded in the opening of the resist. Therefore, if the pattern is thinned, the upper layer material is difficult to enter the narrowed opening. Difficulties were associated with miniaturization.

  Another proposed method is to select a material that has a difference in dissolution rate (etching rate), or to fire the electrode, even if both the upper layer and the lower layer have the property of dissolving in acid. There is a method to crystallize or improve crystallinity by performing the etching of the upper layer on the assumption that the lower layer is etched to some extent, but if there is in-plane variation in the film thickness or etching rate, it will be produced As a result, variations in the performance of the obtained devices occurred, and application to a large area was difficult. In addition, there is a problem in that the structure and subsequent processes are limited, for example, a material having a low etching rate must be disposed in the lower layer. Furthermore, when crystallization by firing cannot be expected, such as when using an organic substrate having low heat resistance, the difference in etching rate is extremely small, and individual patterning is difficult.

  In order to solve the above-described problems, the main invention of the present invention is to manufacture a bottom gate type top contact field effect transistor after forming an active layer pattern in the manufacturing process of a bottom gate type top contact type field effect transistor and also to manufacture a bottom gate type bottom contact type field effect transistor. In the process, after the source / drain electrode pattern is formed, a light-shielding film having acid resistance is provided in one layer. By protecting the lower layer with an acid-resistant light-shielding film, the upper layer can be patterned by etching regardless of the etching rate of the upper layer and without damaging the lower layer such as a decrease in film thickness.

  Another invention is to use a thin film mainly composed of silicon as the acid-resistant light-shielding film. Since silicon has high acid resistance, it exhibits a high etching selectivity with respect to various electrodes and active layers of TFTs that are patterned by etching with an acid, and is effective as an etching stopper. Further, it can be easily formed by a film forming method such as a sputtering method capable of forming a film uniformly over a large area. Furthermore, since it is dissolved in alkali, after the patterning of the upper layer is completed, the thin film containing silicon as a main component is etched by alkali without damaging the lower layer alkali-resistant TFT electrode or active layer. Can be removed.

Another invention is to use materials that are transparent to visible light as materials for the substrate, gate electrode, source electrode, drain electrode, and active layer. Thus, when the upper layer is patterned after forming the upper thin film, a photomask having the shape of the upper layer pattern is not required again, and the substrate is formed using the acid-resistant light-shielding film patterned on the substrate as a mask. By exposing from the back surface, the resist formed on the upper layer is exposed to pattern the resist, and the upper layer can be patterned by subsequent etching. By reducing the use of the photomask once, the time required for mask alignment can be omitted, and the upper layer can be patterned in a self-aligned manner along the pattern shape of the acid-resistant light-shielding film previously patterned ( Self-alignment), and defects due to misalignment are less likely to occur than when a photomask is used again. This is particularly useful when using an organic substrate that has a high rate of expansion and contraction during the process. The acid-resistant light-shielding film does not need to be finally removed when an insulating material is used as its material, but it can also be removed. A transparent TFT can be manufactured by a simple process not using a lift-off process, and the aperture ratio can be increased when this TFT is applied to a liquid crystal display element or the like. Although the backside exposure technology itself is a known technology, in the manufacture of TFTs, the backside exposure technology is used to pattern the active layer using the gate electrode as a mask. Therefore, the gate electrode is necessarily a light shielding film. The manufactured TFT is not transparent to visible light. In the present invention, a material that is transparent to visible light can be adopted for all the materials constituting the TFT, and as a result, a TFT that is transparent to visible light can be produced. As a material transparent to visible light, ITO is used for an electrode, and an amorphous oxide or an amorphous oxide containing microcrystals having an electron carrier density of less than 10 ¹⁸ / cm ³ is used for an active layer. Furthermore, when this manufacturing method is applied, a transparent TFT array having high transistor characteristics can be manufactured with high accuracy and high density.

  According to the present invention, there is provided a method for manufacturing a field effect transistor, in which patterning by one etching in a state where an electrode and an active layer are in contact with each other without causing damage due to overetching or the like such as cutting the other. Etching can be performed. In addition, since the patterning process does not use lift-off, a high yield is expected at the time of manufacturing the TFT array, and the TFT array can be miniaturized. Furthermore, by using a substrate, an electrode, and an active layer that are transparent to visible light, it becomes possible to pattern the thin film on the light shielding film by backside exposure using the acid resistant light shielding film as a mask. Compared with the case where no film is used, the exposure process using a photomask can be omitted once, the time required for alignment can be omitted, and the influence of defects due to misalignment can be reduced. Further, by removing the light-shielding film, a transparent TFT can be manufactured, and a curved TFT can be manufactured by forming each layer at room temperature.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the drawings referred to in the following description of the embodiments are for explaining the configuration of the present invention, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the actual ones. The present invention is not limited to these.

  An embodiment of the present invention will be described in detail below with reference to FIGS.

  Here, unless otherwise specified, a method for manufacturing a bottom-gate top-contact field effect transistor is described.

First, the substrate 101 is prepared (FIG. 1A). The material of the substrate 101 is not particularly limited as long as it can be introduced into the vacuum vessel and can be easily handled, but a lightweight and flexible substrate is preferable. A material transparent to visible light is preferable. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE) Polypropylene (PP), nylon and the like can be used. However, surface treatment with UV, plasma, or the like may be performed to improve adhesion. In some cases, it may be thinly coated with SiO ₂ or the like.

  Next, a gate electrode layer is formed. The material of the gate electrode layer is not particularly limited, but a material that is transparent to visible light is preferable. It is preferable to use tin-doped indium oxide (ITO) as the material because the characteristics as an electrode are enhanced. The film forming method is not particularly limited, but a sputtering method capable of uniformly forming a film over a large area is desirable. The same applies to the film forming method except for the case where a resist is formed.

  Next, a resist pattern is formed on the formed gate electrode layer using general photolithography.

  Subsequently, the gate electrode layer is etched using the resist pattern as a mask. An etching method is not limited, but a method using wet etching is simple because subsequent resist removal is easy. After the etching is completed, the resist is removed using an appropriate solvent to obtain a patterned gate electrode 102 (FIG. 1B).

Next, a gate insulating film 103 is formed (FIG. 1C). The material of the gate insulating film is not particularly limited, but a material that is transparent to visible light and exhibits a high dielectric constant is desirable. Various materials such as SiO ₂ , SiON, HfO ₂ , Y ₂ O ₃ are widely known. The film forming method is not particularly limited. As described above, a sputtering method that can form a film at room temperature and can form a film over a large area uniformly is preferable. It is preferable to mask the lead electrode of the gate electrode provided as a contact for applying a voltage from the outside of the TFT at the time of film formation, because it is not necessary to pattern the gate insulating film when forming the gate insulating film. . The method of the mask is not particularly limited. However, since the extraction electrode generally has a large pattern size, a method such as covering with a stencil mask before film formation is simple.

Subsequently, an active layer is formed. The material for the active layer is preferably an amorphous oxide or an amorphous oxide containing microcrystals having an electron carrier density of less than 10 ¹⁸ / cm ³ . For example, an amorphous oxide semiconductor such as InGaZnO ₄ can be given. Further, a material that has alkali resistance and can be etched with an acid is desirable. It is important in the present invention that the active layer can achieve a desired carrier concentration by controlling the amount of oxygen deficiency.

  Next, a photoresist is formed on the active layer, the resist is processed into a desired pattern shape using general photolithography, and then the active layer is etched using the resist as a mask. The etching method is not limited, but wet etching using an acid is simple. After the etching is completed, the resist is removed using an appropriate solvent. Thereby, the patterned active layer 104 is obtained (FIG. 1D).

Subsequently, a light-shielding film 105 having acid resistance is formed (FIG. 1E). Considering that this may be removed later, the material is preferably silicon or impurity-doped silicon. Depending on the state of the surface before film formation, the adhesion of the acid-resistant light-shielding film may become a problem. In such a case, before forming the acid-resistant light-shielding film, SiO ₂ is deposited to 1 nm. When the film is formed so as to have a film thickness of about a degree, the adhesive force is greatly improved. The interface of this part is an electrically important part that will later come into contact with the source / drain electrode. However, if the film thickness is about 1 nm, there is no significant influence on the conductivity.

  Subsequently, a photoresist 106 is formed on the acid-resistant light-shielding film, a photomask in which a pattern for the source / drain electrode is engraved, and the resist is inverted by using general photolithography. Patterning is performed to obtain a shape (FIG. 1 (f)). Next, after etching the light-shielding film 105 having acid resistance according to the shape of the resist pattern using an alkaline etchant using the formed resist pattern as a mask (FIG. 1 (g)), the resist is formed using an appropriate solvent. It peels (FIG. 2 (a)).

  Next, the source / drain electrode layer 107 is formed (FIG. 2B). The material is not particularly limited, but a material that is transparent to visible light is preferable. When tin-doped indium oxide (ITO) is used as a material, the characteristics as an electrode may be improved, but other materials may be used. The source / drain electrode portion is a portion in which an electrode material is embedded in the opening of the patterned acid-resistant light-shielding film formed earlier, but unlike the case of the lift-off method using a general resist. Since the light-shielding film having acid resistance can use an inorganic thin film such as silicon, the film thickness can be reduced. For this reason, even if the pattern is thinned to some extent, the electrode material can enter the opening, which contributes to the miniaturization of the pattern.

  Next, a negative type photoresist 108 is formed on the formed source / drain electrode layer, and light is applied from the back side of the substrate to expose the front side negative resist (backside exposure). At this time, the negative resist is exposed to the shape of the source / drain electrode pattern using the acid-resistant light-shielding film as a mask. The resist is developed to obtain a negative resist patterned in the shape of the source / drain electrodes (FIG. 2C).

  Subsequently, the source / drain electrode layer is etched using an acidic etchant using the formed negative resist as a mask (FIG. 2D). The etchant that etches the source / drain electrode layer may be the same as or different from the etchant that etched the active layer. Further, the concentration may be the same or different. Examples of the acidic etchant include, but are not limited to, those containing hydrochloric acid or oxalic acid as a main component.

  Finally, the acid-resistant light-shielding film is removed by etching using an alkaline etchant (FIG. 2E), and the resist is stripped using a suitable solvent. This resist peeling may be performed before the etching of the source / drain electrode layer. In this way, a bottom gate type top contact type TFT is completed (FIG. 2F). When the acid-resistant light-shielding film is insulative, there is no problem if it is left as it is, and the process can be shortened by leaving it, but in the case of manufacturing a transparent TFT, etching is performed as described above. And remove.

  When fabricating a bottom gate type bottom contact TFT, a source / drain electrode layer is formed and patterned after forming a gate insulating film, an acid-resistant light-shielding film is formed, and an active layer is formed after patterning. Then, a bottom gate type bottom contact type TFT is completed through a step of patterning the active layer using backside exposure and removing the resist and the acid-resistant light-shielding film. Also in this case, as in the method for manufacturing the bottom gate type top contact type TFT, the acid-resistant light-shielding film does not have to be removed when transparency to visible light is not required. The other details are the same as the manufacturing method of the bottom gate type top contact type TFT.

  Hereinafter, an example of a manufacturing method of a bottom gate type top contact type TFT will be described with reference to FIGS. 1 and 2, but the present invention is not limited to this.

A substrate 101 made of PEN was prepared, and SiO ₂ was deposited to a thickness of 20 nm using a general sputtering method (FIG. 1A).

  The gate electrode layer is formed by depositing ITO as a gate electrode layer at a room temperature using a general sputtering method, and patterned into a gate electrode shape using a general photolithography and an etchant mainly composed of hydrochloric acid. 102 was formed (FIG. 1B).

Next, using a stencil mask that masks the extraction electrode of the gate electrode, SiO ₂ was sputtered at room temperature to form the gate insulating film 103 (FIG. 1C).

Next, InGaZnO ₄ was sputtered at room temperature as the active layer 104, and patterned into a desired active layer shape by wet etching using general photolithography and an etchant mainly composed of hydrochloric acid (see FIG. 1 (d)).

  Next, Si was used as the light-shielding film material 105 having acid resistance, and this was formed by sputtering at room temperature (FIG. 1 (e)).

  Next, a photoresist 106 is spin-coated on the Si film, and the resist is processed into an inverted shape of the source / drain electrodes using general photolithography (FIG. 1 (f)), using this as a mask, The Si film is etched using an etchant mainly composed of tetramethylammonium hydroxide (TMAH) (FIG. 1 (g)), the resist is removed using acetone, and the Si film is removed from the source / drain electrodes. It processed into the shape of a reverse pattern (FIG. 2 (a)).

  Next, an ITO thin film 107 is formed at room temperature using a sputtering method (FIG. 2B), a negative type photoresist 108 is spin-coated thereon, and the back surface is exposed using a high-pressure mercury lamp to expose the resist. And developing to obtain a resist pattern in the shape of source / drain electrodes (FIG. 2C).

  Next, using the resist pattern as a mask, the ITO thin film is wet-etched and patterned using an etchant mainly composed of hydrochloric acid (FIG. 2 (d)), and the Si film is etched and removed using TMAH (FIG. 2). (E)) The resist was removed using acetone, and a bottom gate type top contact type transparent TFT with respect to visible light was completed (FIG. 2 (f)).

  Hereinafter, a method for manufacturing a bottom gate type bottom contact type TFT will be described with reference to FIGS.

A substrate 201 made of PEN was prepared, and SiO ₂ was deposited to a thickness of 20 nm using a general sputtering method (FIG. 3A).

  ITO was formed into a film at room temperature using a general sputtering method, and patterned into a gate electrode shape using general photolithography and an etchant mainly composed of hydrochloric acid to form a gate electrode 202. (FIG. 3B).

Next, using a stencil mask that masks the extraction electrode of the gate electrode, SiO ₂ was sputtered at room temperature to form the gate insulating film 203 (FIG. 3C).

  Next, ITO is sputtered at room temperature as a source / drain electrode material, and ITO is patterned into the shape of the source / drain electrode by wet etching using general photolithography and an etchant mainly composed of hydrochloric acid. A source / drain electrode 207 was formed (FIG. 3D).

  Next, Si was used as the light-shielding film material 205 having acid resistance, and this was formed by sputtering at room temperature (FIG. 3E).

  Next, a photoresist 206 is spin-coated on the Si film, and the resist is processed into an inverted shape of the active layer pattern using general photolithography (FIG. 3 (f)). Using this as a mask, TMAH The Si film was wet-etched using an etchant containing as a main component (FIG. 3G), the resist was removed using acetone, and the Si film was processed into an inverted shape of the active layer pattern (FIG. 4A )).

  Next, InGaZnO 4 is used as the active layer material 204, formed at room temperature using a sputtering method (FIG. 4B), a negative type photoresist is spin-coated thereon, and a back surface is formed using a high-pressure mercury lamp. The resist was exposed to light and developed to obtain a resist pattern 208 having a desired active layer pattern shape (FIG. 4C).

Next, using the resist pattern as a mask, the InGaZnO ₄ thin film is patterned by wet etching using an etchant mainly composed of hydrochloric acid (FIG. 4D), and the Si film is removed by etching using TMAH (FIG. 4). 4 (e)), the resist was removed using acetone, and a bottom gate type bottom contact type transparent TFT with respect to visible light was completed (FIG. 4 (f)).

  The TFTs thus produced were not observed to have overetching in each layer, and were manufactured with a high yield. The TFTs exhibited transistor characteristics suitable for good display applications.

  The present invention can be used for semiconductor devices, display devices, and the like.

It is an example which shows the manufacturing method of the bottom gate type top contact type thin-film transistor of this invention. It is an example which shows the manufacturing method of the bottom gate type top contact type thin-film transistor of this invention. 1 is an example showing a manufacturing method of a bottom gate type bottom contact type thin film transistor of the present invention. 1 is an example showing a manufacturing method of a bottom gate type bottom contact type thin film transistor of the present invention. It is a schematic diagram showing a cross section of a general bottom gate type top contact type thin film transistor. It is a schematic diagram showing a cross section of a general bottom gate type bottom contact type thin film transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Substrate 102 Gate electrode 103 Gate insulating film 104 Active layer 105 Acid-resistant light-shielding film 106 Photoresist 107 Source / drain electrode layer 108 Negative type photoresist

Claims (10)

Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate including the gate electrode;
Forming an active layer pattern on the substrate including the gate insulating film;
Forming a light-shielding film pattern having acid resistance on the substrate including the active layer pattern in the shape of an inverted pattern of the source / drain electrodes;
Forming a source / drain electrode layer on the substrate including the light-shielding film pattern;
Forming a photoresist on the substrate including the source / drain electrode layers;
By patterning the photoresist into the shape of the source / drain electrodes by exposing the photoresist from the back surface using the light shielding film pattern as a mask,
Forming the source / drain electrodes by etching the source / drain electrode layers with an acidic etchant using the patterned photoresist;
A method of manufacturing a field effect transistor, wherein the photoresist is removed. In the manufacturing method of the field effect transistor according to claim 1,
The active layer pattern is formed by patterning by etching after forming the active layer, and the etching of the active layer pattern is performed with an acidic etchant. Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate including the gate electrode;
Forming source / drain electrodes on the substrate including the gate insulating film;
Forming a light-shielding film pattern having acid resistance on the substrate including the source / drain electrodes in the shape of an inverted pattern of the active layer pattern,
Forming an active layer on the substrate including the light-shielding film pattern;
Forming a photoresist film on the substrate including the active layer;
The photoresist is patterned into the shape of the active layer pattern by performing exposure from the back surface using the light shielding film pattern as a mask to the photoresist,
Forming the active layer pattern by etching the active layer with an acidic etchant using the patterned photoresist;
A method of manufacturing a field effect transistor, wherein the photoresist is removed. In the manufacturing method of the field effect transistor according to claim 3,
The source / drain electrode is formed by forming the source / drain electrode layer and then patterning by etching, and the etching of the source / drain electrode is performed with an acidic etchant. A method for manufacturing a transistor.   5. The method of manufacturing a field effect transistor according to claim 1, wherein the light shielding film pattern is a thin film mainly composed of silicon.   The substrate is made of a material transparent to visible light, the gate electrode and the source / drain electrodes are formed of a conductive film transparent to visible light, and the active layer is transparent to visible light The method of manufacturing a field effect transistor according to claim 1, wherein   7. The method of manufacturing a field effect transistor according to claim 1, wherein the material constituting the conductive film transparent to visible light is tin-doped indium oxide (ITO). The material constituting the active layer is an amorphous oxide or an amorphous oxide containing microcrystals having an electron carrier density of less than 10 ¹⁸ / cm ^3. The manufacturing method of the field effect transistor of description. In the method of manufacturing the field effect transistor,
9. The method of manufacturing a field effect transistor according to claim 1, further comprising a step of removing all of the light shielding film pattern by etching.   A field effect transistor manufactured by the manufacturing method according to claim 1.

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