CN110189777A - Non-volatility ferroelectric memory device and its driving method - Google Patents
Non-volatility ferroelectric memory device and its driving method Download PDFInfo
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- CN110189777A CN110189777A CN201810157460.3A CN201810157460A CN110189777A CN 110189777 A CN110189777 A CN 110189777A CN 201810157460 A CN201810157460 A CN 201810157460A CN 110189777 A CN110189777 A CN 110189777A
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
Abstract
The present invention relates to non-volatility ferroelectric memory device and its driving methods.The non-volatility ferroelectric memory device of one embodiment of the invention is as Nonvolatile Memory Device, including semiconductor active layer, multiple storage units and control circuit, multiple storage units series combination on semiconductor active layer, control circuit executes read work and programing work to the select storage unit in multiple storage units, non-volatility ferroelectric memory device is characterized in that, each storage unit can have gate structure, and gate structure includes: the para-electric layer on above-mentioned semiconductor active layer；Dielectric stack, with ferroelectric layer and charge-trapping point, ferroelectric layer is laminated on para-electric layer, and charge-trapping point generates the negative capacitance effect of ferroelectric layer and the interface between the interface or semiconductor active layer that are configured between para-electric layer and ferroelectric layer and para-electric layer is come by the charge captured；And the control grid on above-mentioned ferroelectric layer.
Description
Technical field
The present invention relates to semiconductor technologies, in more detail, are related to non-volatility ferroelectric memory device (Non-volatile
Ferroelectric memory device) and its driving method.
Background technique
Recently, with such as digital camera, MP3 player, palm PC (PDA, personal digital
Assistants) and the increase in demand of the portable digital application apparatus of mobile phone and previous hard disk by solid state hard disk (SSD,
Solid-state drives) substitution, the positive rapid expansion in non-volatility memorizer market.As above-mentioned Nonvolatile Memory Device
It is representative have a low expense carry out highly integrated NAND flash memory device.
Above-mentioned NAND flash memory device has the transistor based on Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
Battery structure is divided into floating gate type and charge trap-type memory device according to the type of information storage layer.In general, being dodged in above-mentioned NAND
In memory device, as I-V curve has the slow gradient, the threshold voltage V of memory cell transistorthDistribution it is wider, as a result,
There is the problem of refresh rate (refresh margin) narrows.This narrow refresh rate becomes the reason of increasing read access time, from
And interfere the improvement of the operating rate of flush memory device.
In order to overcome such as previous nand flash memory device based on above-mentioned floating gate type and charge trap-type memory cell transistor
The shortcomings that distribution of threshold voltage possessed by part, controls subthreshold swing (subthreshold swing；SS) value becomes skill
The solution of art.But in previous NAND flash memory device, it is programmed by the injection of hot carrier, therefore, control
The lower physical limit value of subthreshold swing value is limited to 60mV/dec, therefore, theoretically can not be by control subthreshold swing value drop
Down to lower than 60mV/dec.Also, previous NAND flash memory device operating voltage is high, reaches 20V or more, thus will be in low-voltage
Circuit drives need to have the shortcomings that power consumption is big using special high voltage booster circuit.
Therefore, in order to reduce above-mentioned control subthreshold swing value, need to improve the electricity for constituting previous NAND flash memory device
Dielectric stack.It is attempted as correlation, discloses and utilize ferro-electric field effect transistor (Ferroelectric gate field
Effect transistor:FeFET) nand memory part structure.But above-mentioned ferro-electric field effect transistor of connecting comes
The non-volatile nand memory part constituted need to be opened and be not chosen to read the data in the interior storage unit selected of a string
Other multiple storage units selected, for this purpose, in general, being applied more than to the control grid of other non-selected multiple storage units
The flowing voltage V of the high voltage of the reading voltage applied to the grid of select storage unitpass。
But in the flowing voltage V of above-mentioned high voltagepassIn, the polarization direction of ferroelectric layer is changed and having causes to count
The problem of according to interference (disturb).For example, non-selected storage unit ferroelectric layer polarization direction towards channel layer
(in general, this is defined as elimination state) in the case where opposite direction orientation, by flowing voltage VpassWith the pole of above-mentioned ferroelectricity
The mode for changing direction towards channel layer is inverted (alternatively, depolarising (depolarization)), in the case, can produce nothing
The programming or elimination of meaning ground storage unit.This problem can become to utilize the non-volatile of ferro-electric field effect transistor
The big obstacle of nand memory part.
Therefore, when the select storage unit of the non-volatile nand memory part using ferro-electric field effect transistor is compiled
Journey, reading and when eliminating work need to prevent multiple to deposit with non-selected other of above-mentioned select storage unit share bit lines
The new driving method of the interference of storage unit, for this reason, it may be necessary to pass through improvement threshold voltage VthDistribution improve refresh rate
Improve the operating rate of nand memory part while (refresh margin).
Summary of the invention
The purpose to be realized of the invention is, provides following non-volatility ferroelectric memory device, that is, when executing selection
When programming, reading and the elimination work of storage unit, prevent or reduce because opening and above-mentioned select storage unit share bit lines
Other non-selected cells and caused by other above-mentioned non-selected cells interference, pass through improvement threshold voltage VthPoint
It dissipates to improve refresh ranges (refresh margin), while improving the operating rate of nand memory part.
Also, the other purposes of the invention to be realized are to provide to have the advantages that non-volatility ferroelectric as described above is deposited
The driving method of memory device.
According to an embodiment of the invention, can provide following non-volatility ferroelectric memory device, as non-volatile holographic storage
Device, including semiconductor active layer, multiple storage units and control circuit, above-mentioned multiple storage units are living in above-mentioned semiconductor
Property layer on series combination, above-mentioned control circuit executes read work and volume to the select storage unit in above-mentioned multiple storage units
Journey work, each storage unit of above-mentioned non-volatility ferroelectric memory device have a gate structure, on above-mentioned gate structure includes:
State the para-electric layer on semiconductor active layer；There is dielectric stack ferroelectric layer and charge-trapping point, above-mentioned ferroelectric layer to be laminated in
It states on para-electric layer, above-mentioned charge-trapping point is by the interface that is configured between above-mentioned para-electric layer and above-mentioned ferroelectric layer come by being caught
The charge that obtains and the negative capacitance effect for generating above-mentioned ferroelectric layer；And the control grid on above-mentioned ferroelectric layer.Said memory cells
Subthreshold swing (subthreshold swing；SS) size of value is in 60nmV/dec or less.Above-mentioned control circuit can be with
Mode corresponding with the two kinds of polarity of charge captured in above-mentioned charge-trapping point distributes elimination state and programming shape respectively
One of state.When above-mentioned control circuit executes read work to above-mentioned select storage unit, keep above-mentioned non-selection storage single
Polarization in the ferroelectric layer of member generates reversion, so as to open with above-mentioned select storage unit share bit lines at least one is non-selection
Storage unit, so that multiple charges in the charge-trapping point of above-mentioned non-selected cells can maintain to capture.It can be by upper
The polarization of the multiple charges and above-mentioned ferroelectric layer that capture in charge-trapping point being inverted is stated, goes to pole induce above-mentioned ferroelectric layer
Change phenomenon.Multiple charges when above-mentioned control circuit terminates read work to above-mentioned select storage unit, in charge-trapping point
Capture is maintained, before the repolarization being inverted in above-mentioned ferroelectric layer can be made to arrive by the depolarization phenomenon of above-mentioned ferroelectric layer
Polarization.When above-mentioned control circuit executes programing work to above-mentioned select storage unit, above-mentioned select storage unit can be made
Polarization in ferroelectric layer generates reversion, and multiple charges in the charge-trapping point of above-mentioned select storage unit can be made to above-mentioned choosing
The channel for selecting the semiconductor active layer of storage unit is mobile, in the channel that can make the semiconductor active layer of above-mentioned select storage unit
Other multiple charges it is captured in above-mentioned charge-trapping point.The transmission characteristic of said memory cells can pass through the of elimination state
The second voltage current curve of one voltage-current curve and programming state is shown, during above-mentioned read work, above-mentioned control
Circuit can to the control grid of above-mentioned select storage unit apply read voltage, can to above-mentioned select storage unit share bit lines
At least one non-selected cells control grid apply flowing voltage, above-mentioned reading voltage can by first threshold voltage with
Voltage between second threshold voltage determines, above-mentioned first threshold voltage can be determined with above-mentioned first voltage current curve
Justice, above-mentioned second threshold voltage can be defined with above-mentioned second voltage current curve, and be less than above-mentioned first threshold voltage, above-mentioned
Flowing voltage can be determined by the voltage in the overlapping region of above-mentioned second i-v curve overlapping.When the above-mentioned programming work of execution
When making, above-mentioned control circuit can apply program voltage to the control grid of above-mentioned select storage unit, and above-mentioned program voltage can be by
The voltage greater than above-mentioned flowing voltage in above-mentioned overlapping region determines.Above-mentioned ferroelectric layer may include oxide ferroelectric, fluorination
Object ferroelectricity, Ferro-Electric Semiconductor, macromolecule ferroelectricity or their mixture.Above-mentioned para-electric layer and above-mentioned ferroelectric layer can be having the same
Crystalline texture.Above-mentioned crystalline texture can be perovskite structure, fluorite structure or layer structure.It is generated by above-mentioned para-electric layer
Above-mentioned charge-trapping point and the channel of above-mentioned semiconductor active layer between charge-exchange time comparability read work
The time of (reading time) is long.The thickness of above-mentioned ferroelectric layer can be in the range of 1nm to 100nm.The thickness of above-mentioned para-electric layer
It can be in the range of 1nm to 100nm.
According to another embodiment of the present invention, it is possible to provide the driving method of following non-volatility ferroelectric memory device,
In, above-mentioned non-volatility ferroelectric memory device includes multiple storage units, and above-mentioned multiple storage units include: that above-mentioned semiconductor is living
Para-electric layer on property layer；Dielectric stack, has ferroelectric layer and charge-trapping point, and above-mentioned ferroelectric layer is laminated in above-mentioned para-electric layer
On, above-mentioned charge-trapping point is by the interface that is configured between above-mentioned para-electric layer and above-mentioned ferroelectric layer come by the charge captured
And generate the negative capacitance effect of above-mentioned ferroelectric layer；And the control grid on above-mentioned ferroelectric layer, above-mentioned non-volatility ferroelectric storage
The driving method of device is characterised by comprising: a step of storage unit is selected in above-mentioned multiple storage units；So that
It obtains and multiple charges in the charge-trapping point of at least one non-selected cells of above-mentioned select storage unit share bit lines
The step of maintaining the mode of capture to be controlled；And make above-mentioned non-selection deposit in a manner of opening above-mentioned non-selected cells
The step of polarization in the ferroelectric layer of storage unit generates reversion.The present invention may also include by capturing in above-mentioned charge-trapping point
Multiple charges and above-mentioned ferroelectric layer depolarization phenomenon of the polarization to induce above-mentioned ferroelectric layer being inverted the step of.The present invention
The multiple charges that may also include in above-mentioned charge-trapping point maintain capture and the depolarization phenomenon by inducing in above-mentioned ferroelectric layer
The step of come polarization before arriving the repolarization being inverted in above-mentioned ferroelectric layer.In one embodiment, the present invention may be used also
It include: the step of so that the polarization in the ferroelectric layer of above-mentioned select storage unit is generated reversion；And make above-mentioned select storage unit
Charge-trapping point in channel from multiple charges to the semiconductor active layer of above-mentioned select storage unit it is mobile and make above-mentioned choosing
Select other multiple charges in the channel of the semiconductor active layer of storage unit in the captured step of above-mentioned charge-trapping point, i.e.,
Tunnel switch step.
According to an embodiment of the invention, can provide following non-volatility ferroelectric memory device, that is, by being stored in driving
When device using on above-mentioned semiconductor active layer para-electric layer, the ferroelectric layer that is laminated on above-mentioned para-electric layer and be configured at above-mentioned suitable
The interface between interface or above-mentioned semiconductor active layer and above-mentioned para-electric layer between electric layer and above-mentioned ferroelectric layer is come by being caught
The charge that obtains and generate the negative capacitance effect of above-mentioned ferroelectric layer and the charge-trapping point of tunnel switch effect, thus executing selection
When the read work of storage unit, improve because opening other non-selected cells with above-mentioned select storage unit share bit lines
The obstruction of other above-mentioned non-selected cells caused by and, refresh ranges is improved by the dispersion of improvement threshold voltage, together
The operating rate of Shi Gaishan nand memory part.
Also, according to another embodiment of the present invention, it is possible to provide have the advantages that non-volatility ferroelectric as described above is deposited
The driving method of memory device.
Detailed description of the invention
Fig. 1 is the block diagram for showing the structure of non-volatility ferroelectric memory device of one embodiment of the invention.
Fig. 2 is the NAND ferroelectric storage cell battle array for showing the non-volatility ferroelectric memory device 100 of one embodiment of the invention
The block diagram of column.
Fig. 3 a shows the B-H loop (hysteresis curve) of the ferroelectric storage cell of one embodiment of the invention, Fig. 3 b
For show ferroelectric storage cell equivalent circuit attached drawing.
Fig. 4 a and Fig. 4 b are the storage list for illustratively showing the ferroelectric memory cell array for constituting one embodiment of the invention
The cross-sectional view of an example of member, Fig. 4 c is the equivalent circuit that storage unit is shown with transistor capacitance model.
Fig. 5 a is the elimination work in 4 × 2NAND ferroelectric memory cell array for illustrating one embodiment of the invention
Attached drawing, Fig. 5 b are the attached drawing for illustrating the programing work in 4 × 2NAND ferroelectric memory cell array, and Fig. 5 c is for illustrating 4
The attached drawing of read work in × 2NAND ferroelectric memory cell array.
Fig. 6 a and Fig. 6 b are the magnetic for showing the storage unit in the NAND ferroelectric memory cell array of one embodiment of the invention
The attached drawing of stagnant Id-Vg curve.
Fig. 7 a is the elimination work of the storage unit in the ferroelectric memory cell array for illustrating one embodiment of the invention
Attached drawing, Fig. 7 b is for illustrate and the shared position of select storage unit in the ferroelectric memory cell array of one embodiment of the invention
The attached drawing of the opening work of the non-selected cells of line, Fig. 7 c are the ferroelectric storage cell for illustrating one embodiment of the invention
The attached drawing of the programing work of storage unit in array, Fig. 7 d and Fig. 7 e are for illustrating that the ferroelectricity of one embodiment of the invention stores
The attached drawing of the read work of storage unit in cell array.
Fig. 8 a is the elimination of the storage unit in the ferroelectric memory cell array for illustrating one more embodiment of the present invention
The attached drawing of work, Fig. 8 b are single with the selection storage in the ferroelectric memory cell array of one more embodiment of the present invention for illustrating
The attached drawing of the opening work of the non-selected cells of first share bit lines, Fig. 8 c are for illustrating one more embodiment of the present invention
The attached drawing of the programing work of storage unit in ferroelectric memory cell array, Fig. 8 d and Fig. 8 e are of the invention another for illustrating
The attached drawing of the read work of storage unit in the ferroelectric memory cell array of embodiment.
Fig. 9 is the magnetic hysteresis for showing the storage unit in the NAND ferroelectric memory cell array of one more embodiment of the present invention
The attached drawing of Id-Vg curve.
Figure 10 a is the elimination of the storage unit in the ferroelectric memory cell array for illustrating another embodiment of the present invention
The attached drawing of work, Figure 10 b are for illustrating to store with the selection in the ferroelectric memory cell array of another embodiment of the present invention
The attached drawing of the opening work of the non-selected cells of unit share bit lines, Figure 10 c are for illustrating another implementation of the invention
The attached drawing of the programing work of storage unit in the ferroelectric memory cell array of example, Figure 10 d and Figure 10 e are for illustrating the present invention
Another embodiment ferroelectric memory cell array in storage unit read work attached drawing.
Figure 11 is the block diagram for showing the storage system of one embodiment of the invention.
Figure 12 is the block diagram for showing the data storage device of one more embodiment of the present invention.
Figure 13 is the flash memory for showing one embodiment of the invention and the block diagram of the computing system including it.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Multiple embodiments of the invention are for being more fully understood general technical staff of the technical field of the invention
The present invention, following embodiment can deform in a number of different manners, and the scope of the present invention is not limited to following embodiment.Instead
And these embodiments keep present disclosure more substantial, complete, for complete to general technical staff of the technical field of the invention
Site preparation transmits thought of the invention.
In the accompanying drawings, identical appended drawing reference refers to identical element.Also, if used in the present specification, term " and/
Or " it include one of cited project and more than one all combinations.
The term used in the present specification is not limit the scope of the invention for illustrating embodiment.Also, in this theory
In bright book, as long as indefinite on context point out odd number, even if recording with odd number, it may also comprise multiple forms.Also, at this
" including (comprise) " and/or " including (comprising) ... " is for specific mentioned more used in specification
A shape, number, step, work, the presence of component, element and/or their combination, however not excluded that other shapes, number, work
Work, component, element and/or multiple groups of presence are additional.
In the present specification, when proposing to be formed in the layer of substrate or other layers " upper (on) ", it can refer to and be formed directly into
Layer on the layer of aforesaid substrate or other layers or the middle layer or multiple middle layers that are formed on aforesaid substrate or other layers.And
And for those of ordinary skill, can have and above-mentioned phase with the structure or shape of other shapes " adjacent (adjacent) " configuration
The shape overlapped of neighbour or the part for being configured at lower part.
In the present specification, as shown in the picture, as " downward (below) ", " upward (above) ", " top
(upper) ", " (lower) of lower part ", " horizontal (horizontal) " or " vertical (vertical) " relative terms are used for
Describe relationship possessed by a component parts, layer or multiple regions and other component parts, layer or region.It should be understood that
These terms parts are included in attached direction marked in the figure, further include other directions of element.
Hereinafter, referring to the multiple cross-sectional views pair for schematically illustrating multiple desirable embodiments of the invention (and multiple intermediate structures)
Multiple embodiments of the invention are illustrated.In the drawings, for example, for the convenience of explanation and definition, amplifying multiple
The size and shape of component, when in actual implementation, it is contemplated that multiple deformations of illustrated shape.It is understood, therefore, that
The embodiment of the present invention is not restricted to the specific shape in region illustrated in the present specification.Also, in all the attached drawings,
The appended drawing reference of multiple components of attached drawing refers to identical component.
Fig. 1 is the block diagram for showing the structure of non-volatility ferroelectric memory device 100 of one embodiment of the invention.
Referring to Fig.1, non-volatility ferroelectric memory device 100 may include the memory cell array 110 of multiple storage units, row
Decoder 120, read/write circuits 130 and column decoder 140.Memory cell array 110 can by multiple wordline WL1,
WL2 ..., WLi ..., WLn, multiple character string route selection SSL, virtual character string route selection DSSL and ground line GSL and row solve
Code device 120 is connected.Also, memory cell array 110 can by multiple bit line BL1, BL2, BL3 ..., BLn and reading/write
Enter circuit 130 to be connected.
In the case where non-volatility ferroelectric memory device 100 is NAND-flash memory part, memory cell array 110 can
Including the multiple storage unit character strings (not shown) connected by multiple storage units.In one embodiment, it multiple is deposited above-mentioned
One end of storage unit character string may be configured with for connecting bit line and character string virtual character string select transistor (for example,
NMOS selection transistor) and at least one concatenated character string select transistor of virtual character string select transistor DSST
SST.Whether the quantity of multiple character string select transistor SST can be configured to single layer according to multiple storage unit character strings or have
It is changed with multiple-layer horizontal or the three-dimensional multilayer structure of stacked vertical, the present invention is not limited thereto.
The other end of above-mentioned multiple storage unit character strings is connected with common source line, and may be provided with for connecting altogether
The ground connection selection transistor GST (for example, NMOS selection transistor) of same source line CSL.
Multiple wordline WL1, WL2 ..., WLi ..., WLn can respectively with multiple storage units for being arranged along column direction
Multiple control gates be connected.Multiple bit line BL1, BL2, BL3 ..., BLn can be with above-mentioned multiple character string select transistors
Multiple one end are connected.Its control grid with each wordline WL1, WL2 ..., WLi ..., the WLn line direction that combines
Multiple storage units form logical page (LPAGE), and the quantity of above-mentioned multiple logical page (LPAGE)s can be by the memory capacity of storage unit come really
It is fixed.For example, can be arranged according to storage rank in the single-level cells store device of each storage unit storage 1 bit (bit), every
A storage unit stores the multi-level unit MLC memory part of 2 bits, stores the 8LC memory of 3 bits in each storage unit
Part, and the 16LC memory device of 4 bits is stored in each storage unit.
Multiple storage units of memory cell array 110 can have the two dimension knot for the main surface for being parallel to semiconductor substrate
The storage array layer of structure, or the channel with the main surface perpendicular to above-mentioned semiconductor substrate or one layer or more is along Vertical Square
To the three-dimensional matrix structure of stacking.In one embodiment, above-mentioned three-dimensional matrix structure can fold shape structure for such as channel layer, directly
Linear BICs structure (straight-shaped Bit Cost Scalable structure) and tubular BICs (pipe-sha ped
Bit Cost Scalable) structure, above structure is only exemplary architecture, and the present invention is not limited thereto.
The multiple storage units for forming the above-mentioned page can program in identical program circulation.For example, with the first wordline WL1
The each storage unit being connected can identical program circulation in can with identical program state (or target value) or mutually not
Identical program state programs.For example, a storage unit is programmed for program state P1, phase in a program circulation
Another adjacent storage unit is programmed for the second program state P2, another storage unit is programmed for third program state
P3.But this is only to illustrate, and the present invention is not limited thereto.In another embodiment, with alternating expression framework
In the case where the single stage unit of (interleaved architecture), even number and odd location can be formed 2 it is different
The page.For example, the S LC device of 4kB can have the wordline of 65536 storage units.Also, in the case of a multilevel cell,
Since each unit stores a lowest bit position (Least Significant Bit；) and a highest-order bit LBS
(Most Significant Bit；MSB), thus with 4 pages.For example, in the case, may also set up even number position
MSB and LSB page face on line and MSB and LSB page face on odd number bit line.
Row decoder 120 can control multiple character string route selection SSL and virtual character string route selection DSSL.Implement one
In example, multiple character string route selection SSL or simultaneously driving voltage or electric current are may be selected in row decoder 120.
Also, row decoder 120 may be selected one in multiple wordline of memory block.Row decoder 120 is deposited to selected
The wordline input of block is stored up from the word line voltage VWL of voltage generator generation (not shown).When pass through increment stepping pulse program
When (ISPP, Incremental Step Pul se Program) mode is programmed work, row decoder 120 can Xiang Suoxuan
Wordline (S elected WL) input program voltage VpgmIt, and can be to non-selected wordline with verifying voltage Vvfy
(Unselected WL) input flowing voltage Vpass。
Memory cell array 110 can by column decoder 140 by multiple bit line BL1, BL2, BL3 ..., BLn seeks
Location.Read/write circuits 130, which can be received by column decoder 140 from the data of outside transmitting, can be output to the outside data.
Read/write circuits 130 may include page buffer (not shown), and can be according to operating mode as detection amplification
Device or write driver work.But in the present specification, read/write circuits or page buffer can have
Same meaning, it is thus understood that interchangeable title.When being programmed work, read/write circuits 130 from external circuit by connecing
Data are received to transmit corresponding bit-line voltage to the data for the bit line that will be programmed for cell array 110.When being read out work,
Read/write circuits 130 can be by bit line to the data for being stored in selected storage unit, and can pass through the data to above-mentioned reading
It is latched to be output to the outside.
Passing through the increment stepping pulse program (incremental for being initialized to character string select transistor
Step pulse programming, ISPP) for mode come during being programmed, read/write circuits 130 can be in order to test
Card programs and the character string current or voltage of opposite bit line output is measured.Validation Mode can be by mutually tying with above-mentioned bit line
It closes, and is realized by above-mentioned current sense circuit.In one embodiment, above-mentioned current sense circuit, which may be disposed at, reads/writes
Enter in circuit 130.
Control logic 180 can be according to above-mentioned increment stepping pulse program mode, by executing programming-verifying circuit come to quilt
The storage unit of choosing and/or multiple character string select transistors are programmed.Whenever programming loop counter increase, passes through/lose
Lose whether verifying circuit 150 reaches required target level in Qualify Phase to storage unit and/or multiple character string select transistors
It is not verified.Control logic 180 can be according to instruction CMD, to row decoder 120, read/write circuits 130, column decoder
140, it is controlled by/failure detection device 150, programming circuit sequence detector 160 and/or comparator 170, is based on executing
The pulse program and verifying work of above-mentioned increment stepping pulse program mode.Program circuit sequence detector 160 and comparator 170
For for whether being abnormal low speed unit or quick list to the storage unit and/or character string select transistor to be programmed
The circuit that member is distinguished, and can be omitted.
In a variety of designs, control logic 180 can be integrated in chip identical with memory cell array 110 or be configured at
Different chips, the present invention is not limited thereto.
Fig. 2 shows the N AND ferroelectric storage cells for the non-volatility ferroelectric memory device 100 for including one embodiment of the invention
The block of array.
There is n × m referring to Fig. 2, Fig. 2 NAND ferroelectric memory cell array for illustrating non-volatility ferroelectric memory device 100
Size.Non-volatility ferroelectric memory device 100 can have the structure including being connected with page buffer (referring to Fig.1 130) side
It is n × m at the 1 × m character string select transistor SGD of GSL, 1 × m transistor SGS for being connected to common source line and size
Ferroelectric storage cell FeFET block (block).In Fig. 2, a block is exemplified, but the present invention is not limited thereto, it is non-to wave
Hair property ferroelectric memory device 100 may include multiple pieces according to capacity definition.
The ferroelectric storage cell FeFET of n × m size in above-mentioned piece can be divided into m NAND string or the n page.In this hair
In bright, a NAND string refers to multiple storage units of a shared bit line (example: BL1), and a page can refer to a shared word
Multiple storage units of line (example: WLn).The explanation of above-mentioned ferroelectric storage cell FeFET can refer to and show in fig 3b
The equivalent circuit of storage unit and Fig. 4 b for schematically showing the cross-sectional view of an example of storage unit is shown.
In one embodiment, multiple ferroelectric storage cell FeFET can be towards first direction and second direction, such as passes through court
Two-dimensional array is formed to bit line direction and word-line direction configuration.NAN D structure, for example, channel (not shown) is along bit line side
To formation, along word-line direction, can discontinuously be formed in a manner of spaced apart from each other between above-mentioned multiple channels (not shown).And
And grid (not shown) is formed along word-line direction, it, can be in a manner of spaced apart from each other between above-mentioned grid along bit line direction
It is discontinuous to be formed.This multiple channels (not shown) and grid (not shown) can intersect in multiple regions.Ferroelectricity storage is single
First FeFET is configured in the region that channel (not shown) intersects with grid (not shown).(not shown) can form bit line, grid in channel
(not shown) can form wordline for pole.
Fig. 3 a shows voltage-quantity of electric charge variation hysteresis curve of the ferroelectric storage cell based on one embodiment of the invention,
Fig. 3 b is the figure for showing the equivalent circuit of ferroelectric storage cell.
Referring to Fig. 3 a, ferroelectric storage cell may include ferroelectric layer.When the grid input grounding voltage of phase ferroelectric storage cell
When (Vss or 0V), if not inputting any electric field to above-mentioned ferroelectric layer, it may not polarize.When being input into, ferroelectricity storage is single
When the voltage of the grid of member increases to the positive direction (plus), polarizability (or quantity of electric charge) can increase to positive polarization region from (zero)
Interior state point A.In state point A, polarization occurs along a direction, and the polarizability of state point A can reach maximum value.At this point,
Polarizability, that is, the quantity of electric charge possessed by ferroelectric layer can be indicated with+Qs.Then, if the voltage for being input into grid is reduced again
To ground voltage 0V, then polarizability does not restore to zero (zero), and having in state point B is indicated with remnant polarization rate+Qr
Remnant polarization.Then, if the voltage for being input into above-mentioned grid increases to negative direction, polarizability is changed to negative electricity from state point B
State point C in lotus polairzed area.In state point C, above-mentioned ferroelectric layer can be towards the side opposite with the polarization direction in state point A
To polarization, it can be referred to as polarization reversal below.Polarizability at this time can be indicated with-Qs.Then, even if being input into above-mentioned
The voltage of grid is reduced again to ground voltage 0V, and polarizability is not reduced to zero (zero) yet, but remains on state point D.This
When remnant polarization rate can be indicated with-Qr.If the size for being input into the voltage of grid increases to positive direction again, iron
The polarizability of electric layer becomes state point A from state point D, thus this state point A, state point D can be respectively defined as information
" 1 ", " 0 " or " 0 ", " 1 " are used as memory device.
Referring to Fig. 3 b, ferroelectric storage cell can have the 1T-1C structure including transistor T1 and ferroelectric condenser C1.Direction
One direction forms bit line B/L, wordline W/L is formed towards the direction intersected with bit line B/L, to separate specified interval with wordline W/L
Mode form printed line P/L towards direction identical with wordline W/L, the grid G of transistor T1 is connected with wordline W/L, crystal
The source S of pipe T1 is connected with bit line B/L, and the drain D of transistor T1 can be connected with the first terminal of ferroelectric condenser C1.And
And the Second terminal of ferroelectric condenser C1 can be made to be connected with printed line P/L.
Fig. 4 a be schematically illustrated constitute one embodiment of the invention ferroelectric memory cell array storage unit one
The cross-sectional view of example, Fig. 4 b is the equivalent circuit that storage unit is shown with transistor capacitance model.
Referring to Fig. 4 a, ferroelectric storage cell 110 may include grid 10, ferroelectric layer 20, para-electric layer 30 and semiconductor active layer
40.Semiconductor active layer 40 may include drain region 41, source region 42 and the shape between drain region 41 and source region 42
At the semiconductor layer 43 in channel.In the present invention, channel C H is formed in semiconductor active layer 40 can be described as ferroelectricity storage list
The opening state of member 110, the closing shape that can be described as ferroelectric storage cell 110 of not formed channel C H in semiconductor active layer 40
State.In one embodiment, when the polarization direction of ferroelectric layer 20 is the direction arrow A, the polarized state referred to as born, and be allocated in
Information ' 1 ', the polarization reversal in ferroelectric layer 20, when contrary with arrow A, referred to as positive polarized state, and can divide
Assigned in information ' 0 '.In another embodiment, the negative polarized state in ferroelectric layer 20 is distributed in information ' 0 ', in ferroelectric layer 20
Positive polarized state can also be distributed in information ' 1 '.
In fig.4, example a storage unit be configured on conductor active layer 40, but plurality of source regions domain S can be with
Configuration is separated with multiple drain region D on a semiconductor layer 42, in the case, multiple storage units can be living in semiconductor
Series combination on property layer 40.Each storage unit 110 may include para-electric layer 30 on semiconductor active layer 40, be laminated in para-electric layer
Ferroelectric layer 20 on 30, the grid 10 on dielectric stack DST and ferroelectric layer 20 with charge-trapping point CTS, above-mentioned charge
Capture point CTS is configured at the interface between ferroelectric layer 20 and para-electric layer 30, and ferroelectric layer 20 is generated by the charge of capture
Negative capacitance effect.
Charge-trapping point CTS can capture negative multiple charges by eliminating work, and be captured just by programing work
Multiple charges.In some embodiments, positive multiple charges can be captured by eliminating work, and is caught by programing work
Obtain negative multiple charges.
Specifically, it when charge-trapping point CTS carries out elimination work, captures and the iron electric polarization charge in corresponding interface
Multiple compensation charges of opposite symbol, after eliminating work, even if applying flowing voltage VPASS, also Z can be continuously maintained capture
Above-mentioned multiple compensation charges apply program voltage V after eliminating workPGMWhen, multiple charges of contrary sign can be captured.Tool
Body, it is lower than program voltage V when applyingPGMFlowing voltage VPASSWhen, although multiple electricity of the capture in charge-trapping point CTS
Lotus is kept, but as application program voltage VPGMWhen, as the polarization of ferroelectricity changes, the contrary sign being consistent with this it is more
A compensation charge can be by para-electric layer 30 from 40 tunnel of semiconductor active layer, and captures in charge-trapping point CTS (hereinafter, claiming
For tunnel switch).
In one embodiment, storage unit 110 has ferroelectric metal insulator semiconductor (MFIS, Metal
Ferroelectric Insulator Semiconductor) structure, however, the present invention is not limited thereto.For example, storage unit 110
Can have metal Ferro-Electric Semiconductor (MFS, Metal Ferroelectri c Semiconductor) structure or metal ferroelectricity gold
Belong to insulator semiconductor (MFMIS, Metal Ferroelectric Metal Insulator Semiconductor) structure.
In another embodiment, as shown in Figure 4 b, para-electric layer 30 is configured between ferroelectric layer 20 and grid 10.In this feelings
Under condition, the charge-trapping point CTS for generating the negative capacitance effect of ferroelectric layer 20 by the charge of capture can be defined within para-electric layer
Interface between 30 and semiconductor active layer 40.As long as not conflicting, grid 10, the iron of the ferroelectric storage cell 110 of Fig. 4 b
Electric layer 20, para-electric layer 30 and semiconductor active layer 40 can refer to the grid 10 of the ferroelectric storage cell 110 of Fig. 4 a, ferroelectric layer 20,
The related description of para-electric layer 30 and semiconductor active layer 40.
In one embodiment, in order to generate the negative capacitance effect of ferroelectric layer 20, the subthreshold swing of storage unit 110
(subthreshold swing, SS) value can have 60nmV/dec the following value.In another embodiment, in order to not make iron
In the case where polarized state reversion in electric layer 20, using the inverse domain being present in ferroelectric layer 20, to open storage unit 110,
The SS value of storage unit 110 can have the range of 100mV/dec to 300nmV/dec.
Grid 10 may include platinum (Pt), ruthenium (Ru), iridium (Ir), silver-colored (Ag), aluminium (A l), titanium (Ti), tantalum (Ta), tungsten (W),
Silicon (Si), copper (Cu), nickel (Ni), cobalt (Co) or molybdenum (Mo) or such as their alloy conductive metal.These materials
Expect to be illustrative, the invention is not limited thereto.For example, grid 10 also may include the conductive nitride of metal as described above
(for example, TiN, MoN etc.), electric conductivity nitrogen oxides (for example, TiON etc.) or their combination are (for example, TiSiN, TiAlON
Deng).Or grid 10 also may include the polysilicon for being heavily doped with impurity.
Ferroelectric layer 20 may include oxide ferroelectric, fluoride ferroelectricity, Ferro-Electric Semiconductor, polymer ferroelectricity or its mixing
Object.Above-mentioned oxide ferroelectric may include hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), hafnium oxide zirconium
(HfZrOx), hafnium oxide titanium (HfTi Ox), hafnium silicon oxide (HfSiOx), nickel oxide (NiO), tantalum oxide (TaOx), aluminium oxide
(AlOx), zirconium oxide (ZrOx), copper oxide (CuOx), niobium oxide (NbOx), tantalum oxide (TaOx), gallium oxide (GaOx), oxidation
Gadolinium (GdOx), manganese oxide (Mn Ox), PrCaMnO and ZnONiOx.Or above-mentioned oxide ferroelectric can be for such as PZT (P
bZrxTi1-xO3)、BaTiO3、PbTiO3Deng perovskite (Perovskite) ferroelectricity, such as Li NbO3、LiTaO3Deng pseudo- ferrotianium
Mine (Pseudo-ilmenite) ferroelectricity, such as PbNb3O6、B a2NaNb5O15Deng tungsten bronze (TB) ferroelectricity, such as SBT
(SrBi2Ta2O9), BLT ((B i, La)4Ti3O12)、Bi4Ti3O12Deng bismuth layer structured ferroelectricity and including such as La2Ti2O7Deng
Pyrochlore (Pyrochlore) ferroelectricity and these ferroelectricities solid solution headed by such as Y, Er, Ho, Tm, Yb, Lu rare earth member
The RMnO of plain (R)3With PGO (Pb5Ge3O11)、BFO(BiFeO3).As above-mentioned Ferro-Electric Semiconductor, may include CdZnTe, CdZnS,
The 2-6 compounds of group of Cd ZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe etc..Above-mentioned polymer ferroelectricity may include gathering inclined two
Vinyl fluoride (PVDF), the polymer containing polyvinylidene fluoride, the copolymer containing polyvinylidene fluoride, containing gathering inclined difluoro second
The terpolymer of alkene, odd nylons, cyano and at least one of their polymer or copolymer.Ferroelectric layer 20
These materials be it is illustrative, the invention is not limited thereto.Preferably, ferroelectric layer 20 may include having selected from cube crystalline, cubic
The metal oxide of fluorite (fluorite) structure of the stabilization compositing area crystalline, at least one of monocline is crystalline.For example,
The metal oxide of above-mentioned fluorite (fluorite) structure may include the HfO for adulterating the element just like Si, Al, La, Gd etc.2, mix
The ZrO of the miscellaneous element just like Si, Al, La, Gd etc.2Or their combination.
In view of such as reading voltage, program voltage and the voltage for being applied to grid for flowing voltage, the thickness of ferroelectric layer 20
Degree can have 1nm to 100nm range.Preferably, the thickness of ferroelectric layer 20 can be 10nm.When ferroelectric layer 20 is with a thickness of 1nm
When following, it is difficult to ensure sufficient polarization for storing data works as ferroelectricity to store retentivity (retention) reduction
Layer 20 with a thickness of 100nm or more when, read voltage and program voltage and be possible to become larger, therefore, it is difficult to be driven with low-voltage
It is dynamic.
Para-electric layer 30 can be similar or identical with the material of ferroelectric layer 20.Preferably, para-electric layer 30 may include silica, but
It is without being limited thereto.In order to which the interface between semiconductor active layer 40 and para-electric layer 30 forms the charge for generating negative capacitance effect
The thickness of capture point CTS, para-electric layer 30 can have 1nm to 100nm range.For example, when para-electric layer 30 is with a thickness of 100nm or more
When, so that storage operating voltage is become larger because grid voltage becomes larger, when para-electric layer 30 is with a thickness of 1nm or less, ferroelectricity can not be made
Negative capacitance in layer 30 stabilizes, and exhibits hysteresis behavior, it is therefore preferable that (read) behavior of reading is possible to be obstructed.
In one embodiment, with regard to for terminating for driving the control circuit (referring to Fig.1 180) of storage unit 110
After the opening work of non-selected cells, for example, as shown in Fig. 5 c being addressed below, as reading voltage VreadApply
In selecting unit C22When, also simultaneously to select storage unit C22Multiple non-selected cells C of share bit lines BL221、C23、
C24Apply flowing voltage Vpass, thus openable multiple non-selected cells C21、C23、C24, it is applied in disconnection or removal more
A non-selected cells C21、C23、C24Flowing voltage VpassIn the case where, the charge captured in charge-trapping point CTS is protected
The polarity (for example, negative charge) corresponding to elimination state is held, and can control and pass through the depolarising by charge-trapping point CTS
Phenomenon is come the polarized state before being back to the polarized state being inverted in ferroelectric layer 20.Specifically, electric when applying flowing
Press VpassWhen, the first polarized state of ferroelectric layer 20 is reversed to the second polarized state, but flows voltage V when disconnecting or removingpass
When, it can restore from above-mentioned second polarized state to above-mentioned first polarized state, being caught in charge-trapping point CTS can be kept at this time
The multiple charges obtained.The polarized state that above-mentioned first polarized state can be positive, the pole that above-mentioned second polarized state can be negative
Change state.In some embodiments, the polarized state that above-mentioned first polarized state can be negative, above-mentioned second polarized state can be with
The polarized state being positive.
In one embodiment, single in selection storage for above-mentioned control circuit as shown in Fig. 5 a being addressed below
Before the programing work of member, related above-mentioned multiple storage units can also carry out elimination work.Also, the figure being such as addressed below
Shown in 5b, when carrying out the programing work of above-mentioned select storage unit, in order to which above-mentioned disappear will be corresponded in charge-trapping point CTS
Except the polarity (for example, positive charge) of state is changed to the polarity (negative charge) corresponding to above-mentioned programming state, tunnel is carried out
Switch can control the polarized state (for example, positive polarized state) corresponding to above-mentioned elimination state in ferroelectric layer 20 to be reversed to
Polarized state (for example, negative polarized state) corresponding to above-mentioned programming state.
In one embodiment, the hysteresis Id-Vg curve of the storage unit of reference is addressed below Fig. 6 or Fig. 9,
The transmission characteristic of said memory cells is to eliminate the first voltage current curve (ERS) of state and the second voltage electricity of programming state
Flow curve (PGM) indicates that above-mentioned control circuit is during above-mentioned read work to the control grid of above-mentioned select storage unit
Apply and read voltage, is applied to the control grid of at least one non-selected cells with above-mentioned select storage unit share bit lines
Add flowing voltage VpassOr Vrp, above-mentioned reading voltage can be electric by the first threshold defined by above-mentioned first voltage current curve
Pressure and defined by above-mentioned second voltage current curve and lower than above-mentioned first threshold voltage second threshold voltage between electricity
Pressure flows voltage V to determinepassOr VrpIt can be by the voltage in the overlapping region of the voltage curve of above-mentioned second electric current overlapping Lai really
It is fixed.
In one embodiment, it for above-mentioned control circuit, when carrying out above-mentioned programing work, is stored to above-mentioned selection single
The control grid of member applies program voltage, and above-mentioned program voltage VPGM can be by being greater than above-mentioned flowing voltage in above-mentioned overlapping region
VpassOr VrpVoltage determine
Fig. 4 b is the capacitor equivalent circuit of ferroelectric storage cell 110, the capacitor equivalent circuit of ferroelectric storage cell 110
Including the first capacitor device CFE by ferroelectric layer 20, the second capacitor CDE by para-electric layer 30 and by semiconductor active layer
40 third capacitor CSE, first capacitor device CFE, the second capacitor CDE and third capacitor CSE can connect.First capacitor device
CFE can have negative capacitance (negative capacitance:NC), in the second capacitor CDE and third capacitor CSE at least
One can have positive capacitor.
According to an embodiment of the invention, ferroelectric layer 20, which can form solid solution with para-electric layer 30, to be come normal in ferroelectric layer 20
There is negative capacitance in the operating temperature of temperature.In one embodiment, in ferroelectric layer 20, there is the identical crystalline texture of lattice constant
Ferroelectric layer 20 can form solid solution with para-electric layer 30 and have negative capacitance.In other embodiments, ferroelectric layer 20 can also be with tool
Have and forms solid solution with the para-electric layer 30 of the same or similar crystalline texture of ferroelectric layer 20 to have negative capacitance.In another embodiment
In, in ferroelectric layer 20, the ferroelectric layer 20 with the first perovskite (Perovskite) crystalline texture can with have the second calcium titanium
The para-electric layer of mine crystalline texture forms solid solution to have negative capacitance or ferroelectric layer 20 that can have negative capacitance from their combination.
Wherein, above-mentioned first perovskite crystalline structure can be identical or different with the second perovskite crystalline structure.Preferably, negative in order to have
The characteristic of capacitor, ferroelectric layer 20 can maintain the polarization in ferroelectric layer 20 to have polarized identical split pole all the same
(homogeneous polarization) state.It is suitble to monocrystalline for this purpose, growing by the extension (epitaxial) of ferroelectric layer 20
Therefore in such as structure of Fig. 4 a, ferroelectric layer 20, therefore, the crystallization knot of para-electric layer 30 is laminated in the upside of para-electric layer 30 in film
Structure can be identical as the crystalline texture of ferroelectric layer 20.
In one embodiment, when ferroelectric layer 20 is in negative capacitance state, the subthreshold swing of ferroelectric storage cell 110
(subthreshold Swing:SS) value is smaller than the 60mV/dec (Boltzmann tyranny) of Threshold.Specifically,
If particular grid voltage Vg can be inversely proportional to make above-mentioned grid to grid pile with static capacity CFE, CDE, the CSE in each region
Voltage Vg) it is assigned in ferroelectric layer 20, para-electric layer 30 and semiconductor active layer 40.Therefore, if first capacitor device CFE is negative, divide
The conjunction of voltage assigned in para-electric layer 30 and semiconductor active layer 40 need to be greater than above-mentioned grid voltage Vg, the second capacitor CDE > >
Under conditions of third capacitor CSE, the surface potential of semiconductor active layer 40 need to be greater than above-mentioned grid voltage Vg, to make to control
Subthreshold swing value becomes < 60mV/dec or less.60mV/dec (Boltzmann tyranny) is below to have control subthreshold value
The lag Id-Vg curve of the ferroelectric storage cell 110 of amplitude of oscillation value is illustrated in aftermentioned Fig. 6.
Fig. 5 a is for illustrating the elimination work in 4 × 2NAND ferroelectric memory cell array of one embodiment of the invention
Figure, Fig. 5 b is figure for illustrate the programing work in 4 × 2NAND ferroelectric memory cell array, and Fig. 5 c is for illustrating
The figure of read work in 4 × 2NAND ferroelectric memory cell array.
Referring to Fig. 5 a, when progress is for the elimination work of at least one storage unit in NAND ferroelectric memory cell array
When making, the data of all storage units in NAND ferroelectric memory cell array can be eliminated.For example, make source line (SOURCE) and
Bit line BL1, BL2 float, and Xiang Suoyou wordline WL1 to WL4, SGD line and SGS line apply OV, as a result, NAND ferroelectric storage cell battle array
The data of 8 storage units in column can be eliminated, later, as shown in figure 5, being programmed work at least one storage unit
Later, as shown in Figure 5 c, read work is executed to select storage unit.In another embodiment, as shown in Figure 5 c, selection is deposited
After storage unit executes read work, as shown in Figure 5 b, executed after executing programing work at least one storage unit.
Referring to Fig. 5 b, after all storage units to Fig. 5 a execute and eliminate work, to the storage unit (example of selection
Such as, C32) execute programing work.For example, applying OV voltage to SGS line, to the storage of selection to open the transistor of SGD line
Unit (for example, C32) applies program voltage Vpgm.At this point, in order to select storage unit (such as: it is C32), practical to bit line B L0
OV applies program voltage V to wordline WL3pgm, as a result, the channel in grid 10 and semiconductor active layer 40 (not shown) it
Between, pass through sufficient voltage difference VpgmC32 is programmed.At this point, applying Vbl voltage, Xiang Feixuan to non-selected bit line BL1
Wordline WL1, WL2 selected applies VpassVoltage.Wherein, apply V to non-selection wordline WL1, WL2passVoltage reduces storage unit
The obstruction (disturb) of C31, as a result, the wordline WL4 between storage unit C12 and wordline WL3 and SGS line in order to avoid with deposit
The unnecessary obstruction of storage unit C41 and C42 and be grounded.In Fig. 5 b, work is programmed to a storage unit C32, it is additional
Ground can also carry out programing work to storage unit C32 and other at least more than one storage unit.
Referring to Fig. 5 c, after the programing work of the storage unit for Fig. 5 b, a select storage unit C22 is executed
Read work.Specifically, apply to the wordline W L2 of select storage unit C22 and read voltage Vread, to non-selection multiple wordline
WL1, WL3, WL4 apply Vp assVoltage.This means that the storage unit for opening shared select storage unit C22 and bit line
C21, C23, C24 apply flowing voltage VpassTo open non-selected cells C21, C23, C24.The flowing voltage of read work
VpassWith the flowing voltage V of the programing work of Fig. 5 bpassIt can have identical or different value.
Other non-choosings in NAND chain structure, because storing the cascaded structure of OSFET, in addition to select storage unit C22
It selects storage unit C21, C23, C24 needs to open during read work, this necessarily interferes with the closed state of FeFET.Cause
This is stored in the data degradation of the FeFET of closed state when being read out work to select storage unit C22, so as to cause
Serious problem.This baneful influence is substantially in flowing voltage VpassWhen applying to non-selected cells C21, C23, C24, it can cause
Iron electric polarization reversion from from+P (positive polarized state is in close state) to-P (opening state with negative polarized state).
In general, ferroelectric memory show with as the flash-type by previous clockwise hysteresis curve work
Id-Vg curve is lagged, still, as shown in Fig. 6 or Fig. 9, ferroelectric storage cell 100, can by anticlockwise hysteresis curve
Execute reading and programing work.Flash memory different from the past, the closed state of ferroelectric storage cell 100 is by sufficiently big negative grid
Pole tension Vg induction, can cause positive polarization (+P) state of the ferroelectric layer 20 of grid pair.Therefore, ferroelectric storage cell 100
Elimination state is corresponding to closed state, and the grid voltage Vg of sufficiently big amount is anti-from positive polarization (+P) to negative polarization (- P)
Turn, as a result, openable ferroelectric memory device 100.This is corresponding with programming state (opening state), therefore, lags Id-Vg curve
With rotating counterclockwise direction.
As described above, when the read work of select storage unit, even if ferroelectric memory cell array 110 of the invention will
Non-selected cells are opened from closed state to opening state, that is, are inverted, needed from positive polarized state to negative polarized state
Inhibit the reading driving method for the data corruption of non-selected cells.It is bent by the lag Id-Vg of aftermentioned Fig. 6
Line, using the negative capacity effect of ferroelectricity, even if being inverted from positive polarized state to negative polarized state, when not applying reading work
The flowing voltage V of workpassWhen, by depolarising, polarized state before returning to, data corruption is suppressed, or by aftermentioned
The lag Id-Vg curve of Fig. 9 dominate the polarization shape of ferroelectricity even if not inverting from positive polarized state to negative polarized state
In multiple domains of state, by a part of domain, ferroelectric memory device 100 is opened, to inhibit data corruption.
Fig. 6 a and Fig. 6 b are the storage unit shown in the NAND ferroelectric memory cell array of one embodiment of the invention
Lag Id-Vg curve figure.It is shown in Fig. 6 a to Fig. 6 b when the SS value of storage unit is 60mV/dec or less, it is preferable that when
Lag Id-Vg curve when 50mV/dec.
Referring to Fig. 6 a, as the negative elimination voltage V big to the application of the grid of ferroelectric memory cell array 110ersWhen, in iron
Electric layer 20 forms positive polarization, at this point, ferroelectric memory cell array 110 can be at closed state (zero).Also, in ferroelectric layer
20 positive polarization can interfere the charge of channel C H to flow, therefore, first threshold Vth1It is likely to increase, first threshold Vth1It can be with
For be used to open elimination state storage unit threshold value.
Later, as positive program voltage VPGMWhen applying to the grid of ferroelectric memory cell array 110, in 20 shape of ferroelectric layer
At negative polarization, at this point, ferroelectric memory cell array 110 can be at opening state (=" 1 ").Also, in the negative of ferroelectric layer 20
Polarization improve channel C H charge flowing, therefore, be lower than first threshold Vth1Second threshold Vth2It can reduce.Second threshold
Vth2It can be the threshold value for being used to open storage unit.
As described above, ferroelectric memory cell array 110 is by eliminating voltage VersElimination state is maintained, or passes through programming
Voltage VPGMProgramming state is maintained, memory cell is can be used as a result, and works.At this point, by being defined as first threshold Vth1
With second threshold Vth2Between reading voltage Vr, elimination state in ferroelectric memory cell array 110 or programming shape can be read
State.Specifically, by control circuit, it is " O " value in the case where detection electric current corresponding with the state of elimination, in detection and compiles
It is " 1 " value in the case where the corresponding electric current of journey state, is " 1 " in the case where detection electric current corresponding with the state of elimination
Value is " 0 " value in the case where detecting electric current corresponding with programming state.
Alternatively, being less than program voltage VPGMAnd it is greater than first threshold Vth1Voltage, that is, be defined as program voltage VPGM
With first threshold Vth1Between voltage flowing voltage VpassThe feelings applied to the ferroelectric memory cell array 110 of the state of elimination
Under condition, the polarized state of ferroelectric layer 20 is inverted, so that ferroelectric storage cell 110 is opened, as flowing voltage VpassIt disconnects or is gone
Except when, polarized state before can returning to.This depends on the charge-trapping point CTS of the negative capacity effect of above-mentioned ferroelectric layer 20.Phase
Instead, in flowing voltage VpassIn the case where applying to the ferroelectric memory cell array 110 of programming state, ferroelectric memory cell array
110 will not occur the polarization power generation of ferroelectric layer 20 after opening state.
In Fig. 6 a, first threshold Vth1For be used to open elimination state ERS storage unit threshold value, be lower than the first threshold
Value Vth1Second threshold Vth2For the threshold value for closing storage unit.In another embodiment, as shown in Figure 6 b, first threshold
Vth1For be used to open programming state storage unit threshold value, be lower than first threshold Vth1Second threshold Vth2For for closing
The threshold value of the storage unit of elimination state.
Referring to Fig. 6 b, as the negative program voltage V big to the application of the grid of ferroelectric memory cell array 110PGMWhen, in iron
Electric layer 20 forms positive polarization, at this point, iron memory cell array 110 is in close state.Also, in the positive pole of ferroelectric layer 20
Change the charge flowing for interfering channel C H, therefore, first threshold Vth1It is likely to increase.First threshold Vth1It can be to be used to open volume
The threshold value of the storage unit of journey state.
Later, as positive program voltage VPGMWhen applying to the grid of ferroelectric memory cell array 110, in 20 shape of ferroelectric layer
At negative polarization, at this point, iron memory cell array 110 can be at opening state (=" 1 ").Also, in the negative of ferroelectric layer 20
Therefore the charge flowing that polarization improves channel C H is lower than first threshold Vth1Second threshold Vth2It can reduce.Second threshold
Vth2It can be the threshold value for being used to open storage unit.
As described above, ferroelectric memory cell array 110 is by eliminating voltage VersElimination state is maintained, or passes through programming
Voltage VPGMProgramming state is maintained, memory cell is can be used as a result, and works.At this point, by being defined as first threshold Vth1
With second threshold Vth2Between reading voltage Vr, elimination state in ferroelectric memory cell array 110 or programming shape can be read
State.Specifically, by control circuit, it is " 0 " value in the case where detection electric current corresponding with the state of elimination, in detection and compiles
It is " 1 " value in the case where the corresponding electric current of journey state, is " 1 " in the case where detection electric current corresponding with the state of elimination
Value is " 0 " value in the case where detecting electric current corresponding with programming state.
Alternatively, being less than program voltage VPGMAnd it is greater than first threshold Vth1Voltage, that is, be defined as program voltage VPGM
With first threshold Vth1Between voltage flowing voltage VpassThe feelings applied to the ferroelectric memory cell array 110 of the state of elimination
Under condition, the polarized state of ferroelectric layer 20 is inverted, so that ferroelectric memory cell array 110 is opened, as flowing voltage VpassDisconnect or
When being removed, polarized state before can returning to.This depends on the charge-trapping point of the negative capacity effect of above-mentioned ferroelectric layer 20
CTS.On the contrary, in flowing voltage VpassIn the case where applying to the ferroelectric memory cell array 110 of programming state, ferroelectricity storage is single
The polarization power generation of ferroelectric layer 20 will not occur after opening state for element array 110.
Fig. 7 a is the elimination work for illustrating the storage unit in the ferroelectric memory cell array of one embodiment of the invention
The figure of work, Fig. 7 b be select storage unit for illustrate to be shared in the ferroelectric memory cell array of one embodiment of the invention with
The opening work of the non-selected cells of bit line, Fig. 7 c are the ferroelectric memory cell array for illustrating one embodiment of the invention
The figure of the programing work of interior storage unit, Fig. 7 d and Fig. 7 c are in the ferroelectric memory cell array of one embodiment of the invention
The figure of the read work of storage unit.Wherein, storage unit can have the lag Id-Vg curve (Fig. 6) of the SS value of 50mV/d ec
Transmission characteristic, the gate structure of storage unit is the stepped construction of ferroelectric layer FE, para-electric layer DE, semiconductor layer SE.
Negative elimination voltage V is being applied by grid FG referring to Fig. 7 aersIn the case where, pass through the negative more of grid FG
A charge generates positive charge on the first joint surface (for example, face that grid FG and ferroelectric layer FE connect) of ferroelectric layer FE, with
Opposite the second joint surface (face that ferroelectric layer FE and para-electric layer DE connect) in the first joint surface of ferroelectric layer FE generates negative charge,
Ferroelectric layer FE has positive polarized state as a result,.In the present invention, the positive polarization direction of ferroelectric layer FE can be for from above-mentioned the
Towards the direction on the first joint surface in two joint surfaces.
Also, applying negative elimination voltage VersIn the case where, in the channel between source region S and drain region D
Multiple holes (+) can be formed, still, this can cause the depolarisation effect of ferroelectric layer FE, it is accordingly changed into unstable state, therefore,
In order to maintain to stabilize in elimination state, as shown in a-quadrant, multiple holes (+) in channel can be to ferroelectric layer FE and along bed course DE
Between Interface Moving.A part of hole in channel passes through the one of channel to the Interface Moving between ferroelectric layer FE and para-electric layer DE
Part residual pores, storage unit can remain off state.
After the elimination work of Fig. 7 a, as shown in Figure 7 c, programing work is executed to said memory cells and is offseted later
Except state or the storage unit of programming state, as shown in Fig. 7 d or Fig. 7 e, read work can be performed.As described above, when selection is deposited
When the read work of storage unit, to the non-selected cells of shared select storage unit and bit line, as shown in Figure 7b, it can be performed
Apply the work of flowing voltage.
Referring to Fig. 7 b, by the grid FG of the non-selected cells with positive polarized state, voltage is flowed applying
VpassIn the case where, the variable polarized state being negative of the positive polarized state of the ferroelectric layer FE of non-selected cells.In this hair
In bright, the negative polarization direction of ferroelectric layer FE can be the direction from above-mentioned first joint surface towards the second joint surface.Above-mentioned stream
Dynamic voltage VpassLess than program voltage VPGM, maintained under negative capacitor operating condition, than first threshold Vth1It greatly can be from positive
Polarized state becomes the polarized degree of ferroelectric layer FE.
In the case, channel is opened, and supplies sufficient electric current C, and above-mentioned non-selected cells can not as a result,
The read work for interfering select storage unit, the polarized state for data storage can invert, and therefore, it is broken that data can occur
It is bad.In the present invention, make the stable polarization of above-mentioned reversion, can inhibit this data corruption as a result,.Specifically, when in removal
State flowing voltage VpassWhen, the polarization of the reversion of ferroelectric layer FE in B area can be by being configured at the first joint surface of ferroelectricity FE
Positive charge (+) and the interface positive charge (+) of pre-induction occur the depolarisation effect of strength, pole is gone by this strength
Change effect, the polarization of reversion polarizes before can reverting to.For example, the negative polarized state in ferroelectric layer FE becomes positive polarization shape
State is applying flowing voltage V as a result,passLater, data will not be destroyed, but can be maintained.That is, in flowing voltage VpassIt applies
Add in section, as long as maintaining para-electric layer DE, the interface charge between semiconductor layer SE, because of external voltage and interface charge effect,
It can be increased substantially in the electric field of para-electric layer DE entirety.This effect is because passing through the ferroelectric layer FE and para-electric layer of para-electric layer DE
The charge-exchange time between interface and channel between DE is greater than read access time (reading time) and presents.It is handed in charge
The time is changed less than in the case where read access time, the interface charge between para-electric layer DE/ semiconductor layer SE will not maintain, still, iron
The first projected state in electric layer FE, which is possible without, is restored to the second polarized state.
Flowing voltage V is being applied more than by the grid FG of corresponding selection storage unit referring to Fig. 7 cpassProgramming electricity
Press VPGMIn the case where, by positive multiple charges of grid FG, the first joint surface of ferroelectric layer FE is (for example, grid FG and ferroelectricity
The face that connects layer FE) generate negative charge, second joint surface opposite with the first joint surface of ferroelectric layer FE (ferroelectric layer FE and
The face that para-electric layer DE connects) positive charge is generated, ferroelectric layer FE has negative polarized state as a result, and is referred to as becoming shape
State.Because of program voltage VPGMIt is higher than very much flowing voltage Vpass, therefore, the electric field at the both ends of para-electric layer DE can be with by tunnel
Induced charge exchange, negative polarized state can stabilize.Also, it (is about counted in general, becoming time non-often greater than read access time
Ten μ s), therefore, sufficient charge-exchange is occurred to polarization reversal (to programming and elimination work).This dependent on ferroelectric layer FE,
The tunnel switch effect of para-electric layer DE structure.Therefore, above-mentioned tunnel can be used in the reversible exchange between elimination state and programming state
Road switching effect is realized.
Referring to Fig. 7 d, by the grid FG of the select storage unit with elimination state, voltage V is read applyingread's
In the case of, above-mentioned select storage unit can be read as electric current because of the positive polarization by eliminating the ferroelectric layer FE that voltage is formed
Flowing is by the closed state interfered.
Referring to Fig. 7 e, by the grid FG of the select storage unit with programming state, voltage V is read applyingread's
In the case of, above-mentioned select storage unit is read as the stream of electric current because of the negative polarization of the ferroelectric layer FE formed by program voltage
The dynamic opening state improved.
Fig. 7 a to Fig. 7 e is shown in the memory unit, para-electric layer DE be configured at ferroelectric layer FE and semiconductor active layer SE it
Between, thus in the case that charge-trapping point CTS forms the interface between semiconductor active layer SE and para-electric layer DE, such as Fig. 8 a to figure
Shown in 8e, in the memory unit, para-electric layer DE is configured between grid FG and ferroelectric layer FE, thus, charge-trapping point can be formed
Interface between ferroelectric layer FE and para-electric layer DE.In another embodiment, in the memory unit, the first para-electric layer DE is configured at
Ferroelectric layer FE and semiconductor active layer S diester linkage, the second para-electric layer DE are configured between grid FG and ferroelectric layer FE, thus, it can
The interface between interface and ferroelectric layer FE and para-electric layer DE between semiconductor active layer SE and the first para-electric layer DE forms electricity
Lotus capture point.
Fig. 8 a is the elimination for illustrating the storage unit in the ferroelectric memory cell array of one more embodiment of the present invention
The figure of work, Fig. 8 b are for illustrating to share selection storage list in the ferroelectric memory cell array of another embodiment of the present invention
The figure of the opening work of the non-selected cells of member and bit line, Fig. 8 c is for illustrating in a further embodiment of the invention
The figure of the programing work of storage unit in ferroelectric memory cell array, Fig. 8 d and Fig. 8 e are for illustrating in another reality of the invention
Apply the figure of the read work of storage unit in the ferroelectric memory cell array of example.
Referring to Fig. 8 a, voltage V is eliminated when applying to bearersWhen, the content that positive polarization is formed in ferroelectric layer FE does not generate contradiction
In the case where, it is referred to Fig. 7 a.But in Fig. 7 a, in channel at least multiple holes+to ferroelectric layer FE with it is suitable
Interface Moving and capture between electric layer DE is at its interface, still, in the case where Fig. 8 a, as shown in A ', multiple electricity of grid
Son-is mobile to the section between ferroelectric layer FE and para-electric layer DE and can capture at its interface.Similarly with Fig. 7 a, storage unit can
State is remained off by multiple holes in channel.
Referring to Fig. 8 b, when the grid FG by the non-selected cells with positive polarization state applies flowing voltage Vpass
When, contradictory feelings are not generated in the content that the positive polarization state of the ferroelectric layer FE of non-selected cells is reversed to negative polarization state
Under condition, it is referred to Fig. 7 b.
Similarly with Fig. 7 b, in the case, channel is opened, and supplies sufficient electric current C, above-mentioned non-selection as a result,
Storage unit can not interfere the read work of select storage unit, and the polarized state for data storage can invert, therefore,
Data corruption can occur.In the present invention, make the stable polarization of above-mentioned reversion, can inhibit this data corruption as a result,.Specifically
Ground, as the above-mentioned flowing voltage V of removalpassWhen, the polarization of the reversion of ferroelectric layer FE can be by being configured at ferroelectricity FE in the region B '
The interface negative electrical charge-of negative electrical charge-sum pre-induction on the second joint surface the depolarisation effect of strength occurs, by this strong
The depolarisation effect of power, as the above-mentioned flowing voltage V of removalpassWhen, the polarization of the reversion of ferroelectric layer FE polarizes before can reverting to.
For example, the negative polarization state in ferroelectric layer FE reverts to positive polarization state, applying flowing voltage V as a result,passLater, data
It will not be destroyed, but can maintain.That is, in flowing voltage VpassApply in section, as long as maintaining para-electric layer DE, semiconductor layer
Interface charge between SE can be increased substantially because of external voltage and interface charge effect in the electric field of para-electric layer DE entirety.
By the grid FG of the select storage unit as shown in Figure 8 c, than flowing voltage VpassHigh program voltage
VPGMThe programing work applied does not generate in contradictory situation, is referred to Fig. 7 c, in the read work phase with Fig. 8 d and Fig. 8 e
The content of pass does not generate in contradictory situation, is referred to Fig. 7 d and Fig. 7 e.
Fig. 9 is the sluggishness for showing the storage unit in the NAND ferroelectric memory cell array of another embodiment of the present invention
The figure of Id-Vg curve.Fig. 9 is shown when the SS value of storage unit is 60mV/dec or more, it is therefore preferable to when 200mV/dec or more
Sluggish Id-Vg curve.SS value increases the thickness of para-electric layer DE, or divides the coercive voltage Vc of polycrystalline ferroelectric layer FE sufficiently
It dissipates, to can ensure that about 200mV/dec.
The case where the explanation of the transmission characteristic of the storage unit based on sluggish Id-Vg curve to Fig. 9 does not generate contradiction
Under, can refer to in the relevant explanation of the transmission characteristic of storage unit illustrated in fig. 6 based on sluggish Id-Vg curve.
But the SS value of the storage unit in the 200mV/dec of the SS value using the storage unit greater than Fig. 6 a to Fig. 6 b
In the case where, the opening mechanism of storage unit can be different.Specifically, single in order to open storage in the case where Fig. 6 a to Fig. 6 b
Member and invert the polarization of ferroelectric layer FE, later, can be with the mechanism works of polarized state before being restored by negative capacitance effect.
On the contrary, in the case where Fig. 9, it can be by for determining multiple domain areas of polarized state or polarization direction in ferroelectric layer FE
A small number of inverse domain regions in domain and the mechanism works for being inverted the polarization of ferroelectric layer FE not and opening storage unit.
In the case where domain region has positive polarization, inverse domain region can have negative polarization, on the contrary, domain region has negative polarization
In the case where, inverse domain region can have positive polarization.
In the case where SS value is big, as the parameter of storage unit work, in order to ensure to fill in programming time appropriate
The reversion for the ferroelectric layer polarization divided, and the program voltage V higher than Fig. 6 can be neededPGMProgram voltage VPGM.For example, program voltage
VPGMIt can be about 15V.Also, the grid voltage Vg for being equivalent to the coercive voltage Vc of ferroelectric layer can be 8V.In the case,
It can will flow voltage VpassIt is set as the value than the 8V high as the elimination data for interfering non-selected cells.Therefore, it flows
Voltage VpassThere can be the value lower than 8V, for example, flowing voltage VpassIt can be above-mentioned for that can not be fully opened on eliminating work
The about 7V of non-selected cells.It is electric when reading referring to the widened region of institute of Id-Vg curve but in the low region Vg
Pressure Vr is substantially low 2V, flows voltage VpassIn closed state ERS electric current Ioffrp than select storage unit reading
Circuit is high.If in the case where non-selected cells are in an open state PGM, electric current Ionrp need it is higher than electric current Ioffrp,
Therefore, above-mentioned select storage unit read work can not be interfered.When reading voltage Vr select storage unit for example, the reading of Vr1
Circuit, that is, when Ionr and Ioffr is lower than Ioffpass, reading current range can be Ionr-Ioffr, and value range will not be abundant
Greatly.Due to the non-linearity of Id-Vg curve, the increase of Vr2 can make to read current range increase.But if Vr is increased to
Ionr is higher than the value of Ioffpass, and reading current range is Ioffpass-Ioffr, and reading current range can be close with Vr
VpassAnd become 0 (zero).At this time, it may be necessary to make V as far as possiblepass(V still is below with high valuePGM), however, this is because of ferroelectric layer
(FE) partial inversion and the problem of interfering the elimination data of non-selected cells can be caused.
In other embodiments, as shown in Figure 6 b, in Fig. 9, first threshold Vth1As for making the storage of programming state
The threshold value that unit is opened is lower than first threshold Vth1Second threshold Vth2It can be for closing the storage unit of elimination state
Threshold value driven.
Figure 10 a is the elimination for illustrating the storage unit in the ferroelectric memory cell array of another embodiment of the present invention
The figure of work, Figure 10 b are for illustrating to share selection storage in the ferroelectric memory cell array of another embodiment of the present invention
The figure of the opening work of the non-selected cells of unit and bit line, Figure 10 c are for illustrating in another embodiment of the present invention
Ferroelectric memory cell array in storage unit programing work figure, Figure 10 d and Figure 10 e be for illustrate it is of the invention again
The figure of the read work of storage unit in the ferroelectric memory cell array of one embodiment.
0a referring to Fig.1 eliminates voltage V when applying to bearersWhen, the content that positive polarization is formed in ferroelectric layer FE does not generate lance
In the case where shield, it is referred to Fig. 7 a.But in Fig. 7 a, anode is only indicated with multiple domain regions in ferroelectric layer FE
In change+P, Figure 10 a, when the state of elimination, polarized state can be defined with multiple domain regions and a small number of inverse domain region.Specifically,
Above-mentioned multiple domain regions can refer to positive polarization+P, and a small number of inverse domain regions can refer to negative polarization+P.
0b referring to Fig.1, when the grid FG by the non-selected cells with positive polarization state applies flowing voltage
VpassWhen, it differently with Fig. 8 b, can be by a small number of inverse domain although the polarization of the ferroelectric layer FE of select storage unit is not inverted
Negative polarization+the P in region simultaneously passes through electric current by the channel of semiconductor active layer SE.Specifically, the polarization of ferroelectric layer FE not by
Reversion, and non-selected cells can be opened.
0c referring to Fig.1 applies in the grid FG by the select storage unit and is higher than flowing voltage VpassProgram voltage
VPGMIn the case where, negative electricity is generated on the first joint surface (for example, face that grid FG is in contact with ferroelectric layer FE) of ferroelectric layer FE
Lotus generates with opposite the second joint surface (face that ferroelectric layer FE is in contact with para-electric layer DE) in the first joint surface of ferroelectric layer FE
Positive charge can be referred to as programming state so that ferroelectric layer FE has negative polarization state.At this point, the elimination state phase with Figure 10 a
As, ferroelectric layer FE can be defined as polarized state as multiple domain regions and a small number of inverse domain region.Specifically, above-mentioned multiple domains
Region can refer to negative polarization-P, and a small number of inverse domain regions can refer to positive polarization-P.Further, in the reading with Figure 10 d and Figure 10 e
The relevant content that works does not generate in contradictory situation, is referred to Fig. 7 d and Fig. 7 e.
Figure 11 is the block diagram for showing the storage system 500 of one embodiment of the invention.
Referring to Fig.1 1, storage system 500 includes storage control 510 and Nonvolatile Memory Device 520.Storage control
510 can execute error correcting code to Nonvolatile Memory Device 520.Storage control 510, which can be instructed from outer non-economic with address, to be pressed down
Nonvolatile Memory Device 520 processed.
If storage control 510 receives write request from host, error correction can be executed to the data being requested to be written in
Coding.Also, storage control 510 can inhibit Nonvolatile Memory Device 520, with to above-mentioned data encoded is provided
The corresponding storage area in address is programmed.Also, when being read out work, storage control 510 can be to from non-volatile
The data that memory device 520 exports execute error corrected code.It can be compiled by above-mentioned error correction come to being included in output data
Mistake be modified.In order to execute being detected and corrected for above-mentioned mistake, storage control 510 may include correction block 515.
Nonvolatile Memory Device 520 may include memory cell array 521 and page buffer 523.Memory cell array
521 may include the multilayered memory cellular array of single-layer memory cell or more than two bits.If storage control 510 receives just
Beginningization request, then according to above-mentioned multiple implementation columns, by the programming or cancellation using time-varying elimination voltage signal with each
There is multiple character string select transistors of storage layer the mode of defined state to be initialized.
Figure 12 is the block diagram for showing the data memory device 3000 of another embodiment of the present invention.
Referring to Fig.1 2, data memory device 3000 of the invention may include non-volatility ferroelectric memory device 3100 and flash memory
Controller 3200.Flash controller 3200 can be based on the received multiple control signal of external circuit from data memory device 3000
To control non-volatility ferroelectric memory device 3100.The three-dimensional storage array structure of non-volatility ferroelectric memory device 3100 can be
Such as flowering structure, for example, channel laminated type structure, linear type BICs structure (straight-shaped Bit Cost Scalable
Structure) and cast BICs (pipe-shaped Bit Cost Scalable) structure, above structure is only illustrative, and this
It's not limited to that for invention.
Data memory device 3000 of the invention may make up memory card device, solid-state hard disk SSD device, multimedia memory card
Device, SD card, memory card device, hard disk drive, mixed power plant or with universal serial bus flash memory device.For example, this hair
Bright data memory device 3000 can be satisfaction for the standard using such as digital camera or personal computer electronic device
Or the memory card of specification.
Figure 13 is the non-volatility ferroelectric memory device 4100 for showing one embodiment of the invention and the computing system including it
4000 block diagram.
Referring to Fig.1 3, computing system 4000 of the invention may include the non-volatility ferroelectric storage being electrically connected with bus 4400
Device 4100, storage control 4200, such as baseband chip group (base band chipset) modem 4300, Wei Chu
Reason machine 4500 and user interface 4600.
Non-volatility ferroelectric memory device 4100 shown in Figure 13 can be Nonvolatile Memory Device as described above.This
The computing system 4000 of invention can may also include the work for supplying computing system 4000 in the case for mobile device
Make the battery 4700 of voltage.Although it is not shown, computing system of the invention may also include application chip group (application
Chipset), camera image processor (Camera Image Processor:CIS) or mobile dynamic random memory chip.Example
Such as, storage control 4200 and non-volatility ferroelectric memory device 4100 may make up using the non-volatile iron for storing data
The solid state hard disk (SSD, Solid State Drive/Disk) of electrical storage device.
Non-volatile storage and/or storage control of the invention can be built using a variety of packaged types.Example
Such as, non-volatility ferroelectric memory device of the invention and/or storage control are using such as stacked package (Package on
Package, PoP), BGA Package (Ball grid arrays, BGAs), chip-size package (Chip scale
Packages, CSPs), plastic leaded chip carrier (Plastic Leaded Chip Carrier, PLCC), plastics biserial it is straight
Formula shell (Plastic Dual In-Line Package, PDIP), forging are inserted in Waffle pack (Die in Waffle
Pack), forging is in wafer model (Die in Wafer Form), chip on board (Chip On Board, COB), ceramic double-row
Inline package (Ceramic Dual In-Line Package, CERDIP), plastics metric system quad flat package (Plastic
Metric Quad Flat Pack, MQFP), slim quad flat package (Thin Quad Flatpack, TQFP), small shape
(Small Outline, SOIC) is encapsulated, tightens small outline packages (Shrink Small Outline Package, SSOP), is more
Chip package (Multi Chip Package, MCP), wafer scale manufacture (Wafer-level Fabricated Package,
WFP) or encapsulation wafer level stack encapsulation (Wafer-Level Processed Stack Package, WSP) etc. packaged types and
It is built.
It is discussed above the present invention is not limited to embodiment as described above and appended attached drawing, for belonging to the present invention
For the those of ordinary skill in field, be no more than technical idea of the invention in the range of, can carry out it is a variety of displacement, deformation and
Change is obvious.
Claims (19)
1. a kind of non-volatility ferroelectric memory device, as Nonvolatile Memory Device, including semiconductor active layer, multiple storages
Unit and control circuit, above-mentioned multiple storage units series combination on above-mentioned semiconductor active layer, above-mentioned control circuit pair
Select storage unit in above-mentioned multiple storage units executes read work and programing work, above-mentioned non-volatility ferroelectric memory
Part is characterized in that each storage unit has gate structure, and above-mentioned gate structure includes:
Para-electric layer on above-mentioned semiconductor active layer；
Dielectric stack has ferroelectric layer and charge-trapping point, and above-mentioned ferroelectric layer is laminated on above-mentioned para-electric layer, and above-mentioned charge is caught
It obtains and a little generates above-mentioned iron and the interface being configured between above-mentioned para-electric layer and above-mentioned ferroelectric layer is come by the charge captured
The negative capacitance effect of electric layer；And
Control grid on above-mentioned ferroelectric layer.
2. non-volatility ferroelectric memory device according to claim 1, which is characterized in that the subthreshold value of said memory cells
The size of amplitude of oscillation value is in 60nmV/dec or less.
3. non-volatility ferroelectric memory device according to claim 1, which is characterized in that above-mentioned control circuit with respectively with
It is distributed in elimination state and programming state in the corresponding mode of two kinds of polarity for the charge that above-mentioned charge-trapping point is captured
It is a kind of.
4. non-volatility ferroelectric memory device according to claim 1, which is characterized in that when above-mentioned control circuit is to above-mentioned
When select storage unit executes read work, the polarization in the ferroelectric layer of above-mentioned non-selected cells is made to generate reversion, so as to
At least one non-selected cells with above-mentioned select storage unit share bit lines are opened, so that above-mentioned non-selected cells
Charge-trapping point in multiple charges maintain capture.
5. non-volatility ferroelectric memory device according to claim 4, which is characterized in that by above-mentioned charge-trapping point
The polarization of the multiple charges and above-mentioned ferroelectric layer of interior capture being inverted, to induce the depolarization phenomenon of above-mentioned ferroelectric layer.
6. non-volatility ferroelectric memory device according to claim 5, which is characterized in that when above-mentioned control circuit is to above-mentioned
When select storage unit terminates read work, multiple charges in charge-trapping point maintain capture, pass through going for above-mentioned ferroelectric layer
Polarization phenomena are come the polarization before arriving the repolarization being inverted in above-mentioned ferroelectric layer.
7. non-volatility ferroelectric memory device according to claim 3, which is characterized in that when above-mentioned control circuit is to above-mentioned
When select storage unit executes programing work, the polarization in the ferroelectric layer of above-mentioned select storage unit is set to generate reversion, and make
State semiconductor active layer from multiple charges in the charge-trapping point of select storage unit to above-mentioned select storage unit channel
It is mobile, make other multiple charges in the channel of the semiconductor active layer of above-mentioned select storage unit in above-mentioned charge-trapping point quilt
Capture.
8. non-volatility ferroelectric memory device according to claim 1, which is characterized in that
The transmission characteristic of said memory cells passes through the first voltage current curve of elimination state and the second voltage of programming state
Current curve shows,
During above-mentioned read work, above-mentioned control circuit applies to the control grid of above-mentioned select storage unit reads electricity
Pressure applies flowing electricity to the control grid of at least one non-selected cells with above-mentioned select storage unit share bit lines
Pressure,
Above-mentioned reading voltage determines by the voltage between first threshold voltage and second threshold voltage, above-mentioned first threshold voltage
It is defined with above-mentioned first voltage current curve, above-mentioned second threshold voltage is defined with above-mentioned second voltage current curve, and small
In above-mentioned first threshold voltage,
The voltage in overlapping region that above-mentioned flowing voltage is overlapped by above-mentioned second i-v curve determines.
9. non-volatility ferroelectric memory device according to claim 8, which is characterized in that
When executing above-mentioned programing work, above-mentioned control circuit applies programming electricity to the control grid of above-mentioned select storage unit
Pressure,
Above-mentioned program voltage is determined by the voltage greater than above-mentioned flowing voltage in above-mentioned overlapping region.
10. non-volatility ferroelectric memory device according to claim 1, which is characterized in that above-mentioned ferroelectric layer includes oxidation
Object ferroelectricity, fluoride ferroelectricity, Ferro-Electric Semiconductor, macromolecule ferroelectricity or their mixture.
11. non-volatility ferroelectric memory device according to claim 1, which is characterized in that above-mentioned para-electric layer and above-mentioned iron
Electric layer crystalline texture having the same.
12. non-volatility ferroelectric memory device according to claim 11, which is characterized in that above-mentioned crystalline texture is calcium titanium
Mine structure, fluorite structure or layer structure.
13. non-volatility ferroelectric memory device according to claim 1, which is characterized in that produced by above-mentioned para-electric layer
The time of charge-exchange time between raw above-mentioned charge-trapping point and the channel of above-mentioned semiconductor active layer than read work
It is long.
14. non-volatility ferroelectric memory device according to claim 1, which is characterized in that the thickness of above-mentioned ferroelectric layer exists
The range of 1nm to 100nm.
15. non-volatility ferroelectric memory device according to claim 1, which is characterized in that the thickness of above-mentioned para-electric layer exists
The range of 1nm to 100nm.
16. a kind of driving method of non-volatility ferroelectric memory device, wherein above-mentioned non-volatility ferroelectric memory device includes more
A storage unit, above-mentioned multiple storage units include: the para-electric layer on semiconductor active layer；Dielectric stack has ferroelectric layer
And charge-trapping point, above-mentioned ferroelectric layer are laminated on above-mentioned para-electric layer, above-mentioned charge-trapping point is by being configured at above-mentioned para-electric layer
Interface between above-mentioned ferroelectric layer generates the negative capacitance effect of above-mentioned ferroelectric layer by the charge captured；And it is above-mentioned
The driving method of control grid on ferroelectric layer, above-mentioned non-volatility ferroelectric memory device is characterised by comprising:
A step of storage unit is selected in above-mentioned multiple storage units；
So that in the charge-trapping point of at least one non-selected cells of above-mentioned select storage unit share bit lines
The step of multiple charges maintain the mode of capture to be controlled；And
Generate the polarization in the ferroelectric layer of above-mentioned non-selected cells in a manner of opening above-mentioned non-selected cells anti-
The step of turning.
17. the driving method of non-volatility ferroelectric memory device according to claim 16, which is characterized in that further include leading to
The polarization of the multiple charges and above-mentioned ferroelectric layer that capture in above-mentioned charge-trapping point being inverted is crossed to induce above-mentioned ferroelectric layer
Depolarization phenomenon the step of.
18. the driving method of non-volatility ferroelectric memory device according to claim 17, which is characterized in that on further including
Stating multiple charges in charge-trapping point maintains capture and the depolarization phenomenon by inducing in above-mentioned ferroelectric layer to make above-mentioned iron
The repolarization being inverted in electric layer arrive before polarization the step of.
19. the driving method of non-volatility ferroelectric memory device according to claim 16, which is characterized in that further include:
The step of making the polarization in the ferroelectric layer of above-mentioned select storage unit generate reversion；And
Make semiconductor active of the multiple charges in the charge-trapping point of above-mentioned select storage unit to above-mentioned select storage unit
The channel of layer is mobile and makes other multiple charges in the channel of the semiconductor active layer of above-mentioned select storage unit in above-mentioned electricity
The captured step of lotus capture point, i.e. tunnel switch step.
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| TWI783256B (en) * | 2020-07-03 | 2022-11-11 | 大陸商長江存儲科技有限責任公司 | Reading and writing method for three-dimensional feram storage units |
| US11721377B2 (en) | 2020-07-03 | 2023-08-08 | Yangtze Memory Technologies Co., Ltd. | Method for reading and writing memory cells in three-dimensional FeRAM |
| TWI822345B (en) * | 2020-07-03 | 2023-11-11 | 大陸商長江存儲科技有限責任公司 | Reading and writing method for three-dimensional feram storage units |
| CN112909168A (en) * | 2021-03-23 | 2021-06-04 | 湖北大学 | Multifunctional storage device based on lithium-doped niobium oxide and preparation method thereof |
| CN112909168B (en) * | 2021-03-23 | 2024-01-30 | 湖北大学 | Multifunctional storage device based on lithium doped niobium oxide and preparation method thereof |
Also Published As
| Publication number | Publication date |
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| KR20190105179A (en) | 2019-09-16 |
| KR102025007B9 (en) | 2022-09-06 |
| CN110189777B (en) | 2024-02-27 |
| US10210921B1 (en) | 2019-02-19 |
| KR102025007B1 (en) | 2019-09-24 |
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