CN102403268A - 用于在芯片封装装置中填充接触孔的方法以及芯片封装装置 - Google Patents

用于在芯片封装装置中填充接触孔的方法以及芯片封装装置 Download PDF

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CN102403268A
CN102403268A CN2011103319975A CN201110331997A CN102403268A CN 102403268 A CN102403268 A CN 102403268A CN 2011103319975 A CN2011103319975 A CN 2011103319975A CN 201110331997 A CN201110331997 A CN 201110331997A CN 102403268 A CN102403268 A CN 102403268A
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chip
contact hole
contact
chip packaging
discrete particle
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B·阿勒斯
E·富尔古特
J·马勒
I·尼基廷
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及用于在芯片封装装置中填充接触孔的方法以及芯片封装装置。在各个实施例中，提供了一种用于在芯片封装装置中填充接触孔的方法。所述方法可以包括：向芯片封装的接触孔中引入导电离散颗粒；以及在导电颗粒和芯片的正面和/或反面的接触端子之间形成电接触。

Description

用于在芯片封装装置中填充接触孔的方法以及芯片封装装置
技术领域
各种实施例通常涉及用于在芯片封装装置(arrangement)中填充接触孔的方法以及芯片封装装置。
背景技术
在芯片封装中，芯片通常由芯片封装来包封。为了从芯片封装的外部接触芯片，通常在芯片封装中提供接触孔。通常在接触孔的化学活化(activation)之后，接触孔通常使用电填充工艺(galvanic filling process)而被填充有金属。使用电填充工艺经常导致在填充有金属的接触孔中的相当大的空洞并且对设计强制实施限制。这可能导致电阻和热阻的显著增加。更甚至，芯片封装装置的可靠性可能受损。
当使用金属棒来填充接触孔时，金属棒在接触孔内的接合可能成问题，原因在于由此产生的界面可能提供用于分层的许多种晶(seed)。此外，金属棒将必须几乎精确地适合接触孔。
发明内容
在各个实施例中，提供了一种用于在芯片封装装置中填充接触孔的方法。所述方法可以包含：在芯片封装的接触孔中引入导电离散颗粒，并且形成导电颗粒与芯片正面和/或反面的接触端子之间的电接触。
附图说明
在附图中，贯穿不同的视图，同样的附图标记通常指代相同的部件。附图并非必须依比例绘制，相反重点通常在于图示各个实施例的原理。在以下的说明中，参考以下的附图来说明各个实施例，其中：
图1是图示根据一实施例的用于在芯片封装装置中填充接触孔的方法的流程图；
图2是图示根据一实施例的用于在芯片封装装置中形成到芯片的接触的方法的流程图；
图3示出根据一实施例的单一化之前的在其制造第一阶段的多个芯片封装装置；
图4示出根据一实施例的单一化之前的在其制造第二阶段的多个芯片封装装置；
图5示出根据一实施例的单一化之前的在其制造第三阶段的多个芯片封装装置；
图6示出根据另一实施例的单一化之前的在其制造第二阶段的多个芯片封装装置；以及
图7示出根据再一实施例的单一化之前的在其制造第二阶段的多个芯片封装装置。
具体实施方式
以下的详细说明参考附图，其通过图示方式示出其中可以实施本发明的具体细节和实施例。
在此使用词语“示例性”来意指“用作例子、实例或图示”。在此作为“示例性”说明的任何实施例或设计都不是必须解释为相对其他实施例或设计来说是优选的或有利的。
在权利要求书中和在以下的说明书中，用于填充接触孔和用于形成接触的方法的不同实施例例如以流程图被描述为工艺或测量的特定顺序。要注意的是，实施例不应当限于描述的特定顺序。特定一些或全部的不同工艺或测量也可以同时地或以任何其它有用的和合适的顺序进行。
在各个实施例中，利用导电离散颗粒(例如微颗粒)以在芯片或多个芯片的后段制程(back-end-of-line)处理中填充芯片封装中的接触孔。导电离散颗粒用于例如经由芯片接触端子而产生与芯片的(直接或间接)电接触。所述方法可以包含多个工艺阶段，例如对预先填充有颗粒的(一个或多个)接触孔的额外电填充、或者对填充到(一个或多个)接触孔中的颗粒的部分熔化或烧结或固化。在各个实施例中，相同或不同的颗粒(由相同材料制成或由不同材料制成)可以用来减少芯片封装接触孔中的空洞。
各个实施例可以使用各种类型的芯片，例如半导体芯片或半导体衬底，其中有逻辑集成电路、模拟集成电路、混合信号集成电路、传感器电路、MEMS(微机电系统)、功率集成电路、具有集成无源器件的芯片、分立无源器件等等。通常，如本申请中所使用的术语“半导体芯片”可以有不同的含义，其中一种含义是包含电路的半导体衬底或半导体管芯。
在各个实施例中，芯片可以包含多个芯片，其可以一起位于一个单一芯片封装装置中并且假如同时形成多个封装装置则即使在单一化晶片之后也可以封装在一起。芯片在芯片封装装置中可以定位为彼此相邻和/或可以一个层叠在另一个上以形成多芯片封装(在这种情况下根据各个实施例的电接触可以被提供在多芯片封装的两个相应芯片之间并且被提供用于两个相应芯片之间的电连接；因而，说明性地，根据各个实施例的电接触可以提供在多芯片封装中的芯片到芯片互连中)。此外，在各个实施例中，该芯片或这些芯片可以由芯片载体诸如例如引线框架来承载。
在几个实施例中，层被相互涂敷或者材料被涂敷或沉积到层上。应当认识到如“涂敷”或“沉积”的任何此类术语旨在字面上涵盖向彼此上涂敷层的所有种类和技术。在一个实施例中，它们旨在涵盖其中层作为整体同时(at once)被涂敷的技术(如同例如层压技术)以及其中按顺序方式沉积层的技术(如同例如溅射、电镀、模制、化学汽相沉积(CVD)等等)。
半导体芯片在其一个或多个外表面上可以包含接触元件(在以下中也被称作接触端子)或接触焊盘，其中接触元件用来电接触(半导体)芯片。接触元件可以由任何导电材料制成，例如由金属例如如铝、金或铜，或者金属合金例如焊料合金，或导电有机材料，或导电半导体材料制成。
图1示出了流程图100，其图示了根据一实施例的用于在芯片封装装置中填充接触孔的方法。所述方法可以包括：在102中，向芯片封装的接触孔中引入导电离散颗粒；以及在104中，形成导电颗粒与芯片正面和/或反面的接触端子之间的电接触。
术语“导电离散颗粒”在各个实施例中可以理解为通常任何种类材料的任何种类的单独小块。颗粒的尺寸可以在微米或纳米范围内。在各个实施例中，导电离散颗粒的直径在从约1nm到约50μm的范围内，例如在从约5nm到约3μm的范围内。颗粒可以具有任何形状，例如球形、(规则的或不规则的)多边形、棒形等等。应该提到的是，对所有颗粒来说颗粒的形状不必是相同的。举例来说，假使颗粒具有近似球形，球的直径可以在从约5nm到约3μm的范围内，例如在从约10nm到约2μm的范围内，例如在从约50nm到约500nm的范围内，例如在从约100nm到约200nm的范围内。颗粒可以由导电材料诸如例如金属(例如铜和/或银)或本征导电聚合物(ICP)制成，或者由半导体材料或甚至电绝缘材料(例如陶瓷)制成。为提供导电性，颗粒可以涂布有导电材料，例如涂布有金属(例如铜和/或银)或本征导电聚合物。在各个实施例中，导电离散颗粒是导电离散微颗粒或纳米颗粒。在各个实施例中，本征导电聚合物(ICP)可以被理解为是一种在不添加导电(无机)物质的情况下传导电流的聚合物。可以用于各个实施例中的本征导电聚合物的例子是聚苯胺(PAni)、聚吡咯(PPY)、聚3，4-乙烯二氧噻吩(PEDOT)、聚噻吩。
所述方法在各个实施例中还可以包含在芯片封装的上表面上形成一个或多个金属化层，使得金属化层与接触孔中的导电离散颗粒电接触，由此经由导电离散颗粒形成金属化层与芯片正面和/或反面的接触端子之间的电接触。
为了形成电接触，在各个实施例中，导电颗粒可以被部分熔化(例如以提供颗粒的一些外部区域材料的回流)，其方式使得充分地完全填充接触孔。
此外，在各个实施例中，所述方法还可以包括在向芯片封装的接触孔中引入导电离散颗粒之后电填充接触孔。这可以确保空洞减少的填充并且因而确保电导率增加的接触孔填充。此外，可以提供：在实施电填充之前，接触孔可以以本身已知的方式被化学活化。
在各个实施例中，任何形状的接触孔的直径/半径可以在从约1μm到约500μm的范围内，例如在从约25μm到约200μm的范围内，例如在从约50μm到约100μm的范围内。
此外，在各个实施例中，芯片封装装置可以在芯片封装中包含多个或多重接触孔。接触孔可以具有相同或不同的深度。举例来说，如下面将更详细说明的，一个或多个接触孔可以被提供来直接接触在芯片的正面上提供的一个或多个相应接触端子，并且一个或多个接触孔可以被提供来直接接触在所要接触的芯片外部的导电结构，诸如芯片载体例如引线框架的导电部分，由此间接(例如经由导电结构)电接触可以例如提供在芯片的背面上的一个或多个相应接触端子。
在各个实施例中，所述方法还可以包括：形成芯片载体，例如引线框架；在引线框架上形成芯片封装；在芯片封装中形成接触孔，使得接触孔暴露芯片载体的至少一部分。
图2示出了流程图200，其图示根据一实施例的用于在芯片封装装置中形成到芯片的接触的方法。所述方法可以包括：在202中，形成芯片封装以至少部分地设置在芯片上，该芯片包含接触端子。所述方法还可以包括：在204中，在芯片封装中形成接触孔；以及，在206中，向接触孔中引入导电离散颗粒。所述方法还可以包括：在208中，在导电颗粒与芯片正面和/或反面的接触端子之间形成电接触。
在各个实施例中，所述方法还可以包括在芯片封装的上表面上形成金属化层，使得金属化层与接触孔中的导电离散颗粒电接触，由此经由导电离散颗粒形成金属化层与芯片正面和/或反面的接触端子之间的电接触。
为了形成电接触，在各个实施例中，导电颗粒可以被部分熔化(例如以提供颗粒的一些外部区域材料的回流)，其方式使得充分地完全填充接触孔。
此外，在各个实施例中，所述方法还可以包括在向芯片封装的接触孔中引入导电离散颗粒之后电填充接触孔。这可以确保空洞减少的填充并且因而确保电导率增加的接触孔填充。此外，可以提供：在实施电填充之前，接触孔可以以本身已知的方式被化学活化。
在各个实施例中，任何形状的接触孔的直径/半径可以在从约1μm到约500μm的范围内，例如在从约25μm到约200μm的范围内，例如在从约50μm到约100μm的范围内。
此外，在各个实施例中，芯片封装装置可以在芯片封装中包含多个或多重接触孔。接触孔可以具有相同或不同的深度。举例来说，如下面将更详细说明的，一个或多个接触孔可以被提供来直接接触在芯片的正面或反面上提供的一个或多个相应接触端子，并且一个或多个接触孔可以被提供来直接接触在所要接触的芯片外部的导电结构，诸如芯片载体例如引线框架的导电部分，由此间接(例如经由导电结构)电接触可以例如提供在芯片的背面上的一个或多个相应接触端子。
在各个实施例中，所述方法还可以包括：形成芯片载体，例如引线框架；在引线框架上形成芯片封装；在芯片封装中形成接触孔，使得接触孔暴露芯片载体的至少一部分。
图3在第一图形300中示出了根据一实施例的单一化之前的在其制造第一阶段的芯片封装装置的多个例子。
如图3中所示的，多个芯片封装装置可以包含芯片载体302诸如例如引线框架，其可以包含金属诸如铜或由金属诸如铜制成。在各个实施例中，芯片载体可以被实施为板，例如由金属诸如例如铜制成或包含金属诸如例如铜。此外，多个芯片304，诸如上面所述的那些，可以放置在芯片载体302上并且可以例如借助于固定结构306诸如粘合剂306(其可以是导电或非导电的(例如假使芯片和芯片载体302之间没有必要存在直接电连接))或者借助于焊膏306而例如固定(例如粘结)到芯片载体302。假使芯片304例如提供有一个或多个背面接触(诸如例如背面金属化)，固定结构306可以提供芯片304的(一个或多个)背面接触与芯片载体302之间的导电路径。在各个实施例中，芯片304可以具有在从约40μm到约80μm的范围内的芯片厚度，例如在从约50μm到约70μm的范围内的芯片厚度，例如约60μm的芯片厚度。
此外，在各个实施例中，芯片封装308(例如由芯片封装材料(在以下中也称作灌封材料)制成)可以至少部分地设置在每个芯片304上。在各个实施例中，芯片封装308可以包含或被形成为叠层。在各个实施例中，芯片封装308可以被形成在每个芯片304的顶面和/或侧面上或之上。因而，在各个实施例中，芯片304可以至少部分地被芯片封装308包封。在某些实施例中，(半导体)芯片304可以用灌封材料覆盖。灌封材料可以包含任何电绝缘材料，比如例如任何种类的模制材料、任何种类的环氧材料或任何种类的树脂材料(具有或不具有任何种类的填充材料)。在特殊情况下，可以提供使用导电灌封材料。在各个实施例中，灌封材料可以包含玻璃纤维以加强灌封材料。在各个实施例中，芯片封装308可以在芯片载体302和芯片304上形成一层。在各个实施例中，芯片封装308可以具有在从约50μm到约200μm的范围内的层厚度，例如在从约75μm到约150μm的范围内的层厚度，例如约100μm的层厚度。
此外，在各个实施例中，要形成的每个芯片封装装置可以包含形成在芯片封装308中的多个接触孔310、312，其中多个第一接触孔310可以被布置成使得它们暴露芯片304的正面接触端子(例如芯片焊盘)。此外，多个第二接触孔312可以被布置成使得它们暴露芯片载体302的一部分，由此例如间接接触例如芯片304的背面接触端子(例如芯片焊盘)。如图3中所示的，第一接触孔310可以具有第一深度，其看做为从芯片封装308的上表面开始并向下延伸到(一个或多个)芯片304的上表面。此外，第二接触孔312可以具有第二深度，其看做为从芯片封装308的上表面开始并向下延伸到芯片载体302的上表面。第二深度可以比第一深度大。因而，在各个实施例中，容易地填充具有不同深度的接触孔是可能的。在各个实施例中，第一深度可以在从约20μm到约60μm的范围内，例如在从约30μm到约50μm的范围内的层厚度，例如约40μm的层厚度。在各个实施例中，第二深度可以在从约50μm到约500μm的范围内，例如在从约75μm到约150μm的范围内的层厚度，例如约100μm的层厚度。
在各个实施例中，第一接触孔310和/或第二接触孔312可以具有在从约1μm到约200μm的范围内的直径(例如假使芯片304实施为逻辑芯片304)。在各个实施例中，第一接触孔310和/或第二接触孔312可以具有在从约25μm到约200μm的范围内的直径(例如假使芯片304实施为功率半导体芯片304)。
接触孔310、312在各个实施例中可以根据需要以各种方式形成，诸如例如借助于钻孔、激光或铣削。其他形成接触孔310、312的方式可以在替代实施例中提供。
在各个实施例中，芯片304可以被提供为功率半导体芯片，其具有三个接触端子(例如针对功率(例如MOS)场效应晶体管的漏极端子、源极端子和栅极端子；或例如针对功率双极型晶体管的发射极端子、集电极端子和基极端子)。然而，根据替代实施例，可能向芯片提供两个或甚至超过三个接触端子。在各个实施例中，接触孔的数目可以与待单独接触的接触端子的数目相对应。此外，在各个实施例中，接触端子的一个或多个可以包含多个分别分离的部分接触端子。所述部分接触端子可以被看做为导线阵列。这可以导致更可靠的连接。
此外，在各个实施例中，可以以预定的方式图案化的金属化层314(例如由导电材料诸如例如金属(例如铜)制成)可以被提供在芯片封装308的上表面上或之上。金属化层314可以被提供为具有在从约5μm到约40μm的范围内的层厚度，例如在从约5μm到约20μm的范围内的层厚度。
图4在第二图形400中示出了根据一实施例的单一化之前的在其制造第二阶段的芯片封装装置的多个例子。
如图4中所示的，导电离散颗粒402，诸如如上面所述的那些，可以被引入到接触孔301、312中。如上面所述的，导电离散颗粒402可以是导电离散球402，其可以具有例如几个微米下到几个纳米的直径。
图5在第三图形500中示出了根据一实施例的单一化之前的在其制造第三阶段的芯片封装装置的多个例子。
然后在各个实施例中，如图5中所示的，接触孔310、312可以例如在接触孔310、312的化学活化之后被完全电填充，由此形成电停止填充(galvanic restfilling)502。
图6在第二图形600中示出了根据另一实施例的单一化之前的在其制造第二阶段的芯片封装装置的多个例子。
在这些实施例中，可以提供使用导电离散颗粒602，其中至少某些导电离散颗粒602可以分别包含颗粒核心604和至少部分或完全覆盖颗粒核心604表面的颗粒涂层606。颗粒核心604可以由导电材料和/或非导电材料诸如陶瓷制成或者包含导电材料和/或非导电材料诸如陶瓷。颗粒涂层606可以由导电材料制成或者可以包含导电材料。在各个实施例中，颗粒涂层606可以由本征导电聚合物(ICP)制成或者可以包含本征导电聚合物(ICP)。在这些实施例中，可以提供：可以由于聚合物颗粒涂层606的弹性变形而形成一方面是导电离散颗粒602与另一方面是接触孔310、312的底部和接触孔壁之间的电接触。因而，在这些实施例中，接触孔310、312的额外电(停止)填充可以被完全省去。此外，由于使用柔软(例如弹性)颗粒涂层606诸如聚合物基颗粒涂层606，这些实施例可以提供芯片载体302的导电材料(例如金属)和芯片封装308之间经由接触孔填充的增加的解耦。
在各个实施例中，在导电离散颗粒602被填充到接触孔310、312中之后，聚合物基颗粒涂层606可以被熔化并且再次冷却，由此在一方面是接触孔310、312的底部和接触孔壁与另一方面是导电离散颗粒602之间形成粘结接合。
在各个实施例中，作为纯金属填料球的替代物，例如可以使用金属化的陶瓷颗粒或涂布有本征导电聚合物(ICP)的陶瓷颗粒。这些实施例可以提供如下效果：一方面是金属化的陶瓷颗粒或涂布有本征导电聚合物(ICP)的陶瓷颗粒与另一方面是芯片的材料(例如硅(Si))的CTE之间热膨胀系数(CTE)的差异可能非常小。根据各个实施例，这可以导致芯片封装装置的可靠性的显著改善。
图7在第二图形700中示出了根据再一实施例的单一化之前的在其制造第二阶段的芯片封装装置的多个例子。
在这些实施例中，可以提供使用导电离散颗粒702，其中至少某些导电离散颗粒702可以分别包含颗粒核心704和至少部分或完全覆盖颗粒核心704表面的颗粒涂层706。颗粒核心704可以由导电材料诸如例如第一金属或第一金属体系(system)制成或者可以包含导电材料诸如例如第一金属或第一金属体系。颗粒涂层706可以由导电材料诸如例如第二金属或第二金属体系制成或者可以包含导电材料诸如例如第二金属或第二金属体系。在各个实施例中，第一金属或第一金属体系可以包含铜(Cu)。此外，在各个实施例中，第二金属或第二金属体系可以包含锡(Sn)。
在各个实施例中，在导电离散颗粒702被填充到接触孔310、312中之后，可以实施温度为约231℃或更高的退火工艺，其可以例如通过使用一个或多个激光来局部地实施。在退火工艺中，颗粒涂层706例如第二金属或第二金属体系可以被熔化，由此例如(至少部分地)形成热力学稳定的CuSn3且也形成中间的热力学不稳定的Cu6Sn5。热力学稳定的CuSn3具有高于600℃的熔点。
在各个实施例中，作为纯金属填料球的替代物，例如可以使用金属化的陶瓷颗粒或涂布有本征导电聚合物(ICP)的陶瓷颗粒。这些实施例可以提供如下效果：一方面是金属化的陶瓷颗粒或涂布有本征导电聚合物(ICP)的陶瓷颗粒与另一方面是芯片的材料(例如硅(Si))的CTE之间热膨胀系数(CTE)的差异可能非常小。根据各个实施例，这可以导致芯片封装装置的可靠性的显著改善。
在各个实施例中，可以以针对的(targeted)方式引入(弹性)(例如非导电)聚合物颗粒(例如总球体积的约5～20体积％)到导电离散颗粒(用于补偿或消除(cure)填充中的破裂或裂痕的材料)。这可以导致芯片封装装置的可靠性的增加。这可以作为球栅阵列(BGA)的焊球中例如所谓的涂布聚合物核心球(SOL球)的模拟而说明性地理解。
在各个实施例中，如例如在上面所述的实施例中，可以提供一种用于多个或多重芯片的并行即同步封装，接着是在封装工艺末端的芯片封装装置的单一化，其中所述多个或多重芯片可以都被一个单一芯片载体承载。
在各个实施例中，可以提供使用不同材料的颗粒来在封装工艺中填充不同的孔。这可以甚至实现不同类型芯片(例如逻辑芯片连同半导体功率芯片或存储芯片等等)的并行或同步封装。
在各个实施例中，在接触孔310、312被填充和接触之后，相应芯片封装装置例如沿如图5、6和7中所示的切割线504、608、708被单一化(例如借助于锯割、打断，通过化学方式，通过激光，通过暴露于等离子体或以其它任何合适的方式)。
在各个实施例中，接触孔或通孔可以用一种借助于两步工艺而实现电接触的方式来填充，以便避免在接触孔或通孔金属化中的大空洞。
-在工艺的第一步中，颗粒诸如例如球(例如金属球)可以被插入或引入到要填充的接触孔或通孔中，所述颗粒可以具有例如几个微米下至几个纳米的直径。
-在工艺的第二步中，接触孔或通孔然后可以例如在化学活化之后完全电填充。
在各个实施例中，可以提供：不同颗粒(诸如如上面所述的颗粒)的混合物，例如基于铜或银的金属微颗粒，被引入到接触孔(也被称作接触通孔)中并且随后被退火或回火(temper)以使得接触孔被(完全)填充。在各个实施例中，退火或回火可以以局部的方式提供，例如借助于一个或多个激光或者借助于等离子体辐射。
虽然本发明已参考具体实施例被特别地示出和说明，但是本领域技术人员应当理解可以对其做出形式和细节上的各种变化而不背离如所附权利要求限定的本发明的精神和范围。因而本发明的范围由所附权利要求指示，并且因此落入权利要求的等效意义和范围内的所有变化都旨在被涵盖。

Claims (26)

1.一种用于填充芯片封装装置中的接触孔的方法，所述方法包括：
向芯片封装的接触孔中引入导电离散颗粒；以及
在所述导电颗粒和所述芯片的正面和反面中的至少一个的接触端子之间形成电接触。
2.权利要求1的方法，
其中所述导电离散颗粒被涂布有导电材料。
3.权利要求1的方法，
其中所述导电离散颗粒被涂布有金属和本征导电聚合物材料中的至少一个。
4.权利要求1的方法，
其中所述导电离散颗粒是金属颗粒。
5.权利要求1的方法，
其中所述导电离散颗粒的直径在从约1nm到约50μm的范围内。
6.权利要求1的方法，还包括：
在所述芯片封装的上表面上形成金属化层，使得所述金属化层与所述接触孔中的所述导电离散颗粒电接触，由此在所述金属化层和所述芯片的正面和反面中的至少一个的接触端子之间经由所述导电离散颗粒形成电接触。
7.权利要求1的方法，还包括：
以使得充分地完全填充所述接触孔的方式部分地熔化或烧结或固化所述导电颗粒。
8.权利要求1的方法，还包括：
在向所述芯片封装的所述接触孔中引入所述导电离散颗粒之后，电填充所述接触孔。
9.权利要求1的方法，
其中所述接触孔的直径/半径在从约1μm到约500μm的范围内。
10.权利要求1的方法，
其中所述接触孔包括多个接触孔。
11.权利要求10的方法，
其中所述多个接触孔中的至少某些接触孔具有不同的深度。
12.权利要求1的方法，还包括：
形成芯片载体；
在引线框架上形成芯片封装；
在所述芯片封装中形成接触孔，使得所述接触孔暴露所述芯片载体的至少一部分。
13.一种形成到芯片封装装置中的芯片的接触的方法，所述方法包括：
形成芯片封装以至少部分地设置在芯片上，所述芯片包括接触端子；
在所述芯片封装中形成接触孔；
向所述接触孔中引入导电离散颗粒；以及
在所述导电颗粒和所述芯片的正面和反面中的至少一个的接触端子之间形成电接触。
14.权利要求13的方法，还包括：
以使得充分地完全填充所述接触孔的方式部分地熔化或烧结或固化所述导电颗粒。
15.权利要求13的方法，还包括：
在向所述芯片封装的所述接触孔中引入所述导电离散颗粒之后，电填充所述接触孔。
16.权利要求15的方法，还包括：
在电填充所述接触孔之前，化学活化所述接触孔中的所述导电离散颗粒。
17.权利要求13的方法，
其中所述接触孔的直径/半径在从约1μm到约500μm的范围内。
18.权利要求13的方法，还包括：
在所述导电颗粒和所述芯片封装中提供的另一芯片的接触端子之间形成电接触。
19.一种芯片封装装置，包括：
包括接触端子的芯片；
至少部分地设置在所述芯片上的芯片封装，所述芯片封装包括接触孔；
在所述接触孔中的导电离散颗粒；以及
其中所述导电离散颗粒形成在所述接触孔中，使得提供在所述导电颗粒和所述芯片的正面和反面中的至少一个的接触端子之间的电接触。
20.权利要求19所述的芯片封装装置，
其中所述导电离散颗粒被涂布有导电材料。
21.权利要求19所述的芯片封装装置，
其中所述导电离散颗粒被涂布有金属和本征导电聚合物材料中的至少一个。
22.权利要求19所述的芯片封装装置，
其中所述导电离散颗粒的直径在从约1nm到约50μm的范围内。
23.权利要求19所述的芯片封装装置，还包括：
芯片载体；
其中所述芯片由所述芯片载体承载。
24.一种芯片封装装置，包括：
包括焊盘的芯片；
至少部分地设置在所述芯片上的芯片封装，所述芯片封装包括用于电接触所述焊盘的通孔；
在所述通孔中的导电离散颗粒；以及
其中所述导电离散颗粒形成在所述通孔中，使得提供在所述导电颗粒和所述芯片的正面和反面中的至少一个的焊盘之间的电接触。
25.权利要求24的芯片封装装置，
其中所述导电离散颗粒被涂布有金属和本征导电聚合物材料中的至少一个。
26.权利要求24的芯片封装装置，
其中所述通孔包括多个通孔；
其中所述多个通孔中的至少某些通孔具有不同的深度。
CN2011103319975A 2010-09-10 2011-09-09 用于在芯片封装装置中填充接触孔的方法以及芯片封装装置 Pending CN102403268A (zh)

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