CN102361028A - 具有多重凸块结构的半导体封装结构 - Google Patents

具有多重凸块结构的半导体封装结构 Download PDF

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CN102361028A
CN102361028A CN2011103056005A CN201110305600A CN102361028A CN 102361028 A CN102361028 A CN 102361028A CN 2011103056005 A CN2011103056005 A CN 2011103056005A CN 201110305600 A CN201110305600 A CN 201110305600A CN 102361028 A CN102361028 A CN 102361028A
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semiconductor element
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黄东鸿
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开一种具有多重凸块结构的半导体封装结构，由多个半导体元件堆叠而成，其中在两半导体元件接面的角落上具有由多个相互导通的凸块所构成的多重凸块结构，用以增加元件接面上的裂缝扩展路径。如此，当多重凸块结构中的部分凸块受到应力破坏而失效时，多重凸块结构中的其他凸块仍可维持正常的功能，以避免元件之间的电连接路径遭受应力破坏而失效，进而确保封装结构的可靠度。

Description

具有多重凸块结构的半导体封装结构
技术领域
本发明涉及一种半导体封装结构，且特别是涉及一种堆叠式封装的多重凸块结构。 
背景技术
在现今资讯社会的时代，电子产品已成为不可或缺的生活必须品之一，琳琅满目的电子产品充斥于市面上。随着电子科技的进步，许多功能性强、运算速度快及记忆容量大的电子产品便研发出来，但是体积不但没有增加，反而却朝向轻、薄、短、小的趋势迈进。为达到缩小体积及重量的目的，就电路设计而言，是融入整合的概念，如此仅须利用一芯片便可以达到许多功能，且芯片内已能够制作出纳米等级线宽的集成电路，故即使芯片整合了许多功能，还是可以制作出体积甚小的芯片。 
就半导体封装而言，为达到上述轻、薄、短、小的设计理念，许多厂商便开发出许多符合此理念的芯片封装，比如是多芯片模块(MCM)、芯片尺寸构装(CSP)及堆叠型多芯片封装等。 
在堆叠型的半导体封装中，不同的芯片或基板通过凸块相互接合，而由于各种芯片与基板的热膨胀系数差异，因此位于接面上的凸块必须承受相当大的应力。特别是，随着凸块尺寸的缩小，位于元件接面角落的凸块受到应力破坏而失效的风险大幅增加，使得半导体封装的可靠度受到严峻考验。 
发明内容
为解决上述问题，本发明提供一种半导体封装结构，包括一第一半导体元件、一第二半导体元件、多个第一凸块以及多个第二凸块。第一半导体元件具有一上表面以及一下表面。第二半导体元件接合至第一半导体元件的下表面。第一凸块以及第二凸块配置于第一半导体元件的下表面，用以连接第一半导体元件以及第二半导体元件，其中第二导电凸块位于第一半导体元件 与第二半导体元件的接面的至少一角落，且位于同一角落的第二导电凸块相互电连接，以传递相同的信号。 
本发明还提供一种半导体封装结构，包括相互堆叠的多个半导体元件、多个第一凸块、多个第二凸块、多个第一导电路径和多个第二导电路径。第一凸块和第二凸块配置于任两相邻的半导体元件之间，用以连接所述多个半导体元件。第二凸块并且位于所述两相邻的半导体元件的接面的至少一角落。第一半导体元件中集成电路的一金属层为第一导电路径，用以电连接所述多个第二凸块，以传递相同的信号。第二半导体元件中集成电路的一金属层为第二导电路径，用以电连接所述多个第二凸块，以传递相同的信号。 
基于上述，本发明在元件接面的角落上形成多重凸块结构，以相互电连接的多个凸块提供相同的电性功能，例如传输同一个电信号。此相互电连接的多个凸块可以增加元件接面上的裂缝扩展路径(crack propagation path)，即可避免因元件翘曲，造成部分位于角落的凸块受到应力破坏而失效时，仍有与其电连接的其他凸块维持正常的功能，因而可有效避免元件之间的电连接路径遭受应力破坏而失效，以确保半导体封装结构的可靠度。 
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。 
附图说明
图1绘示依照本发明的一实施例的一种半导体封装结构； 
图2A-图2C还绘示图1的多重凸块结构可能采用的几种设计； 
图3绘示依照本发明的另一实施例的一种半导体封装结构； 
图4还绘示图3的多重凸块结构的局部放大图； 
图5绘示依照本发明的又一实施例的一种半导体封装结构； 
图6还绘示图5的多重凸块结构的局部放大图； 
图7绘示依照本发明的再一实施例的一种半导体封装结构； 
图8还绘示图7的多重凸块结构的局部放大图。 
具体实施方式
参照图1，其绘示依照本发明的一实施例的一种半导体封装结构100。此半导体封装结构100是由半导体元件110～140堆叠而成。 
半导体元件110，在本实施例中，例如是芯片，具有一上表面110a及一下表面110b，该下表面110b具有多个焊垫112，及多个底下金属层114配置于焊垫112上。半导体元件110可通过配置于该底下金属层114上的第一凸块152a及第二凸块152b，接合至半导体元件120。该第一凸块152a配置于该半导体元件110的下表面110b的中间区域，该第二凸块152b配置于该半导体元件110的下表面110b的角落区域，该第二凸块152b围绕该第一凸块152而设置，且该第二凸块152b为一多重凸块结构160，亦即至少两个凸块相互电连接并提供相同的电性功能，可避免因元件翘曲，造成部分位于角落的凸块受到应力破坏而失效时，仍有与其电连接的其他凸块维持正常的功能。 
半导体元件120，在本实施例中，例如是中介基板，具有一上表面120a及一下表面120b，通过第三凸块154接合至线路基板130，配置于该第四表面120b的角落区域的第三凸块154，如上所述，可为一多重凸块结构。 
线路基板130，具有一上表面130a及一下表面130b，通过第四凸块156接合至电路板140，配置于该下表面130b的角落区域的第四凸块156，如上所述，可为一多重凸块结构。 
多重凸块结构160，例如是由至少两个凸块152所构成，图1中的粗体线段代表通过此多重凸块结构160的导电路径172。通过位于半导体元件110上的导电路径172以及位于半导体元件120上的导电路径174来连接多重凸块结构160中的凸块152。 
以下通过图2A-图2C来举例说明几种导电路径可能的设计。 
参照图2A，其更绘示图1的多重凸块结构160的局部放大图。所述导电路径172例如是位于半导体元件110中集成电路的一金属层118，而所述导电路径174例如是位于半导体元件120中集成电路的一金属层128。 
多重凸块结构经由半导体元件所提供的导电路径并不限于半导体元件中集成电路的一金属层。举凡半导体元件表层线路，皆可作为连接本申请的多重凸块结构的导电路径。 
如图2B所示，本实施例绘示该多重凸块结构160配置于该半导体元件110的底下金属层114上以及该半导体元件120的底下金属层124上，可经由该底下金属层114、124形成的导电路径，将所述多个第二凸块152b相互电连接。 
另一实施例，如图2C所示，绘示该多重凸块结构160配置于该半导体元件110的焊垫112上以及该半导体元件120的焊垫122，可经由相同焊垫形成的一导电路径，将所述多个第二凸块152b相互电连接。 
参考图3，其绘示依照本发明的另一实施例的一半导体封装结构300。此半导体封装结构300是由半导体元件310～320、线路基板330及电路板340堆叠而成，其中半导体元件310，例如是芯片，通过凸块352接合至半导体元件320，半导体元件320，例如是中介基板，通过凸块354接合至线路基板330，而线路基板330通过凸块356接合至电路板340。 
本实施例选择将半导体元件320与330的接面角落的凸块354形成多重凸块结构360。本实施例的多重凸块结构360例如是由两个凸块354所构成，而图3中的粗体线段代表通过此多重凸块结构360的导电路径。如图3所示，本实施例通过半导体元件320所提供的导电路径372以及半导体元件330所提供的导电路径374来连接多重凸块结构360中的凸块354。 
参考图4，其还绘示图3的多重凸块结构360的局部放大图。如图4所示，所述导电路径372例如是位于半导体元件320中集成电路的一金属层322。此外，导电路径374例如是位于线路基板330内部的线路332。多重凸块结构360的凸块354分别通过相应的导电通孔334连接到重布线路332。 
当然，本实施例也可以如图2B与2C所示，选择通过半导体元件的底下金属层以及焊垫来连接凸块354，此处不再赘述。 
参考图5，其绘示依照本发明的又一实施例的一种半半导体封装结构500。此半导体封装结构500是由半导体元件510～520、线路基板530和电路板540堆叠而成，其中半导体元件510，例如是芯片，通过凸块552接合至半导体元件520，半导体元件520，例如是中介基板，通过凸块554接合至线路基板530，而线路基板530通过凸块556接合至电路板540。本实施例选择将半导体元件520与线路基板530的接面角落的凸块554形成多重凸块结构560。本实施例的多重凸块结构560例如是由两个凸块552所构成，而图5中的粗体线段代表通过此多重凸块结构560的导电路径。如图5所示，本实施例通过位于半导体元件520所提供的导电路径572以及位于半导体元件530所提供的导电路径574来连接多重凸块结构560中的凸块554。 
图6还绘示图5的多重凸块结构560的局部放大图。如图6所示，所述导电路径572例如是位于半导体元件520中集成电路的一金属层522。此外， 导电路径574例如是位于半导体元件530内部的基板线路532。在此，半导体元件520为中介基板，且具有多个导电通孔(conductive via)524，以提供一垂直导电路径。多重凸块结构560的凸块554分别通过相应的导电通孔524向上连接到半导体元件520中集成电路的一金属层522。 
当然，本实施例也可以如图2B与2C所示，选择通过半导体元件的底下金属层以及焊垫来连接凸块554，此处不再赘述。 
图7绘示依照本发明的再一实施例的一种半导体封装结构700。此半导体封装结构700是由半导体元件710～720、线路基板730和电路板740堆叠而成，其中半导体元件710，例如是芯片，通过凸块752接合至半导体元件720，半导体元件720，例如是中介基板，通过凸块754接合至线路基板730，而线路基板730通过凸块756接合至电路板740。 
本实施例在两处元件接面上分别形成多重凸块结构，包括选择将半导体元件710与720的接面角落的凸块752形成多重凸块结构760，以及，将半导体元件720与730的接面角落的凸块754形成多重凸块结构770。本实施例的多重凸块结构762例如是由两个凸块752所构成，多重凸块结构764例如是由两个凸块754所构成，而图7中的粗体线段代表通过多重凸块结构762与764的导电路径。如图7所示，本实施例通过位于半导体元件710上的导电路径772以及位于半导体元件720上的导电路径774来连接多重凸块结构762中的凸块752，并且，通过位于半导体元件720上的导电路径776以及位于半导体元件730上的导电路径778来连接多重凸块结构764中的凸块754。 
图8还绘示图7的多重凸块结构762与764的局部放大图。如图8所示，所述导电路径772例如是位于半导体元件710中集成电路的一金属层712。此外，导电路径774例如是位于半导体元件720中集成电路的一金属层722。此外，导电路径776例如是位于半导体元件720中集成电路的一金属层724。此外，导电路径778例如是位于半导体元件730内部的基板线路732。在此，半导体元件720为中介基板，具有导电通孔726，用以连接半导体元件720中集成电路的一金属层722与724。 
当然，本实施例也可以如图2B与2C所示，选择通过半导体元件的底下金属层以及焊垫来连接凸块752与754，此处不再赘述。 
综上所述，本申请通过在元件接面的角落上形成多重凸块结构可以增加 元件接面上的裂缝扩展路径。如此，当多重凸块结构中的部分凸块受到应力破坏而失效时，多重凸块结构中的其他凸块仍可维持正常的功能，以避免元件之间的电连接路径遭受应力破坏而失效，进而确保封装结构的可靠度。 
此外，本申请提出的多重凸块结构可以应用于堆叠式封装的任两相邻的元件之间，且随着半导体封装结构的元件组成的不同，所选元件可能是芯片、中介基板、线路基板以及电路板等常见的半导体封装组成元件中的任两者。因此，上述多个实施例的封装结构仅是用来说明本发明的技术方案，并非用以限制此技术方案的应用范畴。本技术领域的技术人员当可依据实际状况对本申请提出的各个设计概念与变化进行组合、调整或省略，并且将其应用于各类封装结构的元件接面上，以达到类似的技术效果。 
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。 

Claims (10)

1.一种半导体封装结构，包括：
第一半导体元件，具有第一表面；
第二半导体元件，接合至所述第一半导体元件的所述第一表面，所述第二半导体具有第二表面，面向所述第一表面；
多个第一凸块，配置于所述第一表面与所述第二表面之间；以及
多个第二凸块，配置于所述第一表面与所述第二表面之间，所述多个第二凸块位于所述第一半导体元件的一角落，且所述多个第二凸块相互电连接。
2.如权利要求1所述的半导体封装结构，其中所述第一半导体元件内部具有至少一第一金属层电连接至多个焊垫，所述多个焊垫分别电连接至多个底下金属层，所述多个底下金属层分别电连接所述多个第二凸块。
3.如权利要求1所述的半导体封装结构，其中所述第二半导体元件具有多个导电穿孔，分别连接所述多个第一凸块和第二凸块。
4.如权利要求1所述的半导体封装结构，其中所述多个第二凸块是用来传递同一个电信号。
5.如权利要求1所述的半导体封装结构，还包含线路基板，其中所述线路基板具有多个第三凸块，配置于所述第二半导体元件与所述线路基板之间，所述多个第三凸块位于所述第二半导体元件的一角落，且所述多个第三凸块相互电连接。
6.如权利要求4所述的半导体封装结构，还包含电路板，电连接至该线路基板。
7.一种半导体元件，包括：
表面；
多个焊垫配置于所述表面上；
多个底下金属层配置于所述多个焊垫上；
多个第一凸块配置于所述第一半导体元件上；以及
多个第二凸块配置于所述第一半导体元件的一角落，且所述多个第二凸块相互电连接。
8.如权利要求7所述的半导体元件，其中所述第一半导体元件内部具有至少一第一金属层电连接至所述多个焊垫，所述多个焊垫分别电连接至所述多个底下金属层，所述多个底下金属层分别电连接所述多个第二凸块。
9.如权利要求7所述的半导体元件，其中所述多个焊垫电连接所述多个第二凸块，且所述多个第二凸块是用来传递同一个电信号。
10.如权利要求7所述的半导体元件，其中所述多个底下金属层电连接所述多个第二凸块，且所述多个第二凸块是用来传递同一个电信号。
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