CN102347288A - 集成电路装置 - Google Patents

集成电路装置 Download PDF

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Publication number
CN102347288A
CN102347288A CN2010105976905A CN201010597690A CN102347288A CN 102347288 A CN102347288 A CN 102347288A CN 2010105976905 A CN2010105976905 A CN 2010105976905A CN 201010597690 A CN201010597690 A CN 201010597690A CN 102347288 A CN102347288 A CN 102347288A
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buffer layer
patterned buffer
layer
integrated circuit
separating parts
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CN2010105976905A
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CN102347288B (zh
Inventor
杨庆荣
黄章斌
刘醇鸿
唐修敏
陈英儒
邵栋梁
陈宪伟
蔡豪益
李明机
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种集成电路装置，包括一裸片，其包括一金属垫；一保护层；以及一图案化缓冲层，位于上述保护层的上方，其中上述图案化缓冲层包括彼此隔开的多个分离部分；一焊球下金属层，位于上述图案化缓冲层的一开口和上述保护层的一开口中；一金属凸块，位于上述焊球下金属层的上方且电性耦合至上述焊球下金属层。本发明可提升接合强度。

Description

集成电路装置
技术领域
本发明涉及一种集成电路装置，尤其涉及一种倒装芯片接合结构及其形成方法。
背景技术
在芯片工艺中，首先于半导体基板的表面上形成例如晶体管的集成电路元件。然后，于上述集成电路元件的上方形成内连线结构。于半导体晶片的表面上形成金属凸块，且电性耦接至上述集成电路元件。切割上述半导体晶片成为半导体芯片，上述半导体芯片也可视为常见的裸片。
在封装半导体芯片工艺中，通常利用倒装芯片接合工艺(flip-chip bonding)将上述半导体芯片与其他芯片接合。使用焊锡凸块以接合上述半导体芯片中的金属凸块(bump)至封装基板中的接合垫。使用底部填充物(underfill)以保护上述焊锡凸块。
图1显示公知技术范例中用于接合芯片202和封装基板204的接合结构。微凸块210用以将芯片202中的接合金属物212(例如为焊球下金属层(UnderBump Metallurgy，UBM))接合至封装基板204的接合垫214。聚酰亚胺(polyimide)层220形成于芯片202的表面上。底部填充物(underfill)216填充介于芯片202和封装基板204之间，且与聚酰亚胺(polyimide)层220接触。如图1所示的公知接合结构会遭受底部填充物216和聚酰亚胺层220之间的分层现象(delamination)的不良影响。由于例如因为接近底部填充物216和聚酰亚胺层220之间界面的高应力而产生翘曲的工艺问题会导致上述分层现象的发生。上述应力也会导致在上述分层现象沿着横向扩展。
因此，在此技术领域中，有需要一种接合结构及其形成方法，以提升接合强度。
发明内容
有鉴于此，本发明一实施例提供一种集成电路装置，包括一裸片，其包括一金属垫；一保护层；以及一图案化缓冲层，位于上述保护层的上方，其中上述图案化缓冲层包括彼此隔开的多个分离部分；一焊球下金属层，位于上述图案化缓冲层的一开口和上述保护层的一开口中；一金属凸块，位于上述焊球下金属层的上方且电性耦合至上述焊球下金属层。
一种集成电路装置，包括：一第一工件，包括一图案化缓冲层，其中该图案化缓冲层包括彼此隔开的多个分离部分；一第二工件，位于该第一工件的上方；一金属凸块，接合该第一工件和该第二工件；以及一底部填充物，介于于该图案化缓冲层和该介电层之间，且接触该图案化缓冲层和该介电层，其中该底部填充物将该图案化缓冲层的所述多个分离部分彼此隔开。
本发明可提升接合强度。
本发明其他实施例揭示如下。
附图说明
图1为公知接合结构的剖面示意图。
图2至图7A为依据本发明不同实施例的接合结构的形成方法的工艺剖面图。
图7B至图7F为图7A的俯视图。
其中，附图标记说明如下：
2～芯片；
10～基板；
12～内连线结构；
14～半导体元件；
16～顶层金属介电质；
18～保护层；
28～金属垫；
30～保护层；
34～缓冲层；
38～光刻光掩模；
38A～不透明部分；
38B～透明部分；
38C、38D～半透明部分；
40～阶面；
42、44～顶面；
46～开口；
50～焊球下金属层；
54～焊锡凸块；
56～第一工件；
100～第二工件；
60、216～底部填充物；
202～芯片；
204～封装基板；
210～微凸块；
212～接合金属物；
214～接合垫；
220～聚酰亚胺层；
T～厚度；
H1、H2、H4～高度；
a1、a2～水平尺寸；
H3、H5～阶高；
E1～长边；
E2～短边；
L1、L2～长度。
具体实施方式
以下以各实施例详细说明并伴随着附图说明的范例，做为本发明的参考依据。在附图或说明书描述中，相似或相同的部分均使用相同的附图标记。且在附图中，实施例的形状或是厚度可扩大，并以简化或是方便标示。此外，附图中各元件的部分将以分别描述说明，值得注意的是，图中未示出或描述的元件，为本领域普通技术人员所知的形式，另外，特定的实施例仅为揭示本发明使用的特定方式，其并非用以限定本发明。
本发明实施例提供一种新颖的接合结构。以下以各实施例详细说明并伴随着附图说明的范例，做为本发明的参考依据。在附图或说明书描述中，相似或相同的部分均使用相同的附图标记。
请参考图2，提供一芯片2，其包括一基板10。芯片2可为一元件裸片(device die)，其内部包括例如晶体管的有源元件(active device)，然而，芯片2也可为其内部没有有源元件的一封装基板或一中介物(interposer)。在本发明一实施例中，芯片2可为一元件裸片(device die)，而基板10可为例如硅基板的一半导体基板，然而基板10也可包括其他半导体材料。例如晶体管的半导体元件14可形成于基板10的一表面。内连线结构12，其包括形成于其中且连接至半导体元件14的金属线和介层孔插塞(图未显示)，形成于基板10的上方。上述金属线和介层孔插塞可由铜或铜合金形成，且可利用常用的镶嵌工艺形成上述金属线和介层孔插塞。内连线结构12可包括常用的层间介电质(ILD)和金属层间介电质(IMD)。上述金属层间介电质(IMD)可包括顶层金属介电质16，可做为一最顶层，且例如金属线的顶层金属物形成于其中。上述层间介电质(ILD)和金属层间介电质(IMD)可由低介电常数介电材料形成，举例来说，低介电常数介电材料的介电常数约低于3.0或甚至约低于2.5。
保护层18(也可视为保护层1)形成于顶层金属介电质16的上方。金属垫28形成于保护层18的上方。金属垫28可包括铝(Al)、铜(Cu)、银(Ag)、金(Au)、镍(Ni)、钨(W)、上述合金及/或上述多层结构。金属垫28可电性耦接至半导体元件14，举例来说，金属垫28可借由其下的内连线结构12电性耦接至半导体元件14。可形成保护层30(也可视为保护层2)以覆盖金属垫28的边缘部分。在本发明一实施例中，可由例如氮化硅、氧化硅、聚酰亚胺(polyimide)或上述复合层的介电材料形成保护层18和30。
请参考图3，缓冲层34形成于保护层30的上方，且接触保护层30。缓冲层34和保护层30由不同的介电材料形成。可由较保护层30软或弹性较保护层30大的材料形成缓冲层34。在本发明一实施例中，可由聚酰亚胺(polyimide)、有机材料或类似的材料形成缓冲层34。缓冲层34的厚度T例如可约介于2.5μm至20μm之间。
图4A至图4C显示图案化缓冲层34的步骤。请参考图4A，提供一光刻光掩模38，其包括用以挡光的不透明部分38A和允许光通过的透明部分38B。此外，光刻光掩模38可包括透明层38E，其可为一玻璃基板。使用光刻光掩模38可图案化缓冲层34，移除缓冲层34的一些部分，且留下缓冲层34的一些部分。当缓冲层34由聚酰亚胺(polyimide)的一光致抗蚀剂形成时，可使用将曝光光致抗蚀剂显影的常用方法，来移除受光的部分缓冲层34。下方的保护层30和金属垫28从缓冲层34中的开口暴露出来。可以知道的是，在本实施例中，显示的缓冲层(聚酰亚胺)34可为一正光致抗蚀剂，其中缓冲层34的曝光部分被移除，而缓冲层34的未曝光部分被保留且不被移除。然而，缓冲层(聚酰亚胺)34也可由一负光致抗蚀剂形成，且缓冲层34的未曝光部分被移除，而缓冲层34的曝光部分被保留且不被移除。
图4B显示具有阶面40的图案化缓冲层34的形成方式。阶面40，其为实质上平坦的表面，低于缓冲层34的顶面42，且高于保护层30的顶面44(其中上述顶面44也和缓冲层34的底面位于同一层)。在本发明一实施例中，光刻光掩模38为一半穿透光掩模，其包括用以挡光的不透明部分38A、透明部分38B和半透明部分38C，上述不透明部分38A、透明部分38B和半透明部分38C具有不同的透光率，且半透明部分38C的透光率介于不透明部分38A和透明部分38B之间。因此，部分缓冲层34会接收穿过半透明部分38C的光，且因而形成阶面40。在本发明一实施例中，高度H2对高度H1的比值可约介于1至5之间，其中水平尺寸a1为开口46延伸至保护层30的顶面44的尺寸，而水平尺寸a2为阶面40的水平尺寸。
图4C显示的缓冲层34的两个阶面40和48的形成方式，且阶面40和48分别具有不同的阶高H3和H5。缓冲层34的整体高度表示为H4。可使用光刻光掩模38进行形成上述结构，而光刻光掩模38包括具有不同透光率的半透明部分38C和38D，其中半透明部分38C和38D的透光率介于不透明部分38A和透明部分38B之间。此外，于同一光刻步骤中图案化缓冲层34且暴露出金属垫28。
请参考图5，焊球下金属层(Under Bump Metallurgy，UBM)50形成于金属垫28上且电性连接至金属垫28。焊球下金属层50可包括一钛层和位于钛层上方的一铜层(图未显示)。本发明一实施例的焊球下金属层50的工艺可包括于保护层30和图案化缓冲层34上形成一掩模(图未显示)，图案化上述掩模以形成一开口，金属垫28从上述开口暴露出来。然后进行一电镀步骤以于上述掩模的上述开口中形成焊球下金属层50。之后移除上述掩模。接着，如图6所示，于焊球下金属层50上形成焊锡凸块54，且可回焊(re-flow)上述焊锡凸块54为一锡球(solder ball)。在本发明一实施例中，可利用无电电镀法形成上述焊锡凸块54，以使焊锡仅会电镀于焊球下金属层50上，而不会电镀于保护层30和图案化缓冲层34上。
可将切割芯片2为裸片(也可视为说明书中的第一工件)。请参考图7A，第一工件56，其为从芯片2切割下来的一部分，与第二工件100结合，第二工件100可为一元件裸片(device die)、一封装基板或一中介物(interposer)。在本发明一实施例中，焊锡凸块54接合至第二工件100的接合垫110。接合垫110可由铜(Cu)(举例来说，纯铜或大体上为纯铜)、铝(Al)、银(Ag)、钯(Pa)上述合金及/或上述多层结构形成。
底部填充物(underfill)60可填充于第一工件56和第二工件100之间的间隙中。因此，底部填充物60包围和保护焊锡凸块54不受应力影响。可以了解的是，上述底部填充物60包括位于缓冲层34上方的一部分，以及延伸进入缓冲层34的部分之间的间隙中的一部分。此外，底部填充物60接触缓冲层34的部分的侧壁，缓冲层34的顶面40和42，以及保护层30的顶面44。
图7B至图7F为依据图7A所示的本发明不同实施例的俯视图，其中上述俯视图为图7A的切线7-7的切平面的俯视图。在图7B至图7F中，每一个缓冲层34的剩余部分可具有如图4A所示的均一的高度，或可如图4B和图4C所示，每一个缓冲层34的剩余部分可包括一中间部分，其高度大于边缘部分的高度。
请参考图7B，缓冲层34的剩余部分形成借由底部填充物60彼此隔绝的分离柱状物(也可使用元件符号34标示)。在图7C至图7D中，缓冲层34的剩余部分形成借由底部填充物60彼此隔绝的分离条状物(也可使用元件符号34标示)。在本发明一实施例中，假设第一工件56具有一长边E1和一短边E2，且上述长边E1的长度L1大于上述短边E2的长度L2，所以分离条状物34的长轴方向可与长边E1平行。此外，在图7C中，分离条状物34形成一阵列。在图7D中，在每一行和每一列中，分离条状物34以交错位置方式排列。
在图7E中，缓冲层34的剩余部分可形成环状物包围焊锡凸块54，其中上述环状物的形状可为方形，圆形或上述组合。包围不同焊锡凸块54的上述环状物借由底部填充物60彼此隔绝。图7F显示每一个焊锡凸块54可被多于一个的环状物包围，上述环状物可借由缓冲层34的额外部分彼此连接。
在本发明实施例中，图案化上述缓冲层34，且因而上述底部填充物60延伸至缓冲层34的剩余部分之间的间隙中。上述图案化缓冲层34可避免底部填充物60和缓冲层34之间的分层现象沿着横向扩展，如果有的话。因此可以提升最终封装结构的可靠度。此外，也可增加底部填充物60和包括缓冲层34和保护层30的位于底部填充物60下方的层之间界面的面积，而导致底部填充物60和其下方的层之间具有较佳的粘合力。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (10)

1.一种集成电路装置，包括：
一裸片，包括：
一金属垫；
一保护层，覆盖该金属垫的边缘部分；
一图案化缓冲层，位于该保护层的上方，其中该图案化缓冲层包括彼此隔开的多个分离部分；
一焊球下金属层，位于该图案化缓冲层的一开口中和该保护层的一开口中；以及
一金属凸块，位于该焊球下金属层的上方且电性耦合至该焊球下金属层。
2.如权利要求1所述的集成电路装置，还包括一底部填充物，其包括一第一部分，位于该图案化缓冲层的上方，以及一第二部分，延伸进入该图案化缓冲层的所述多个分离部分之间的间隙，且其中该底部填充物接触该保护层。
3.如权利要求1所述的集成电路装置，其中该图案化缓冲层的所述多个分离部分包括一中间部分和一边缘部分，且该中间部分的高度大于该边缘部分的高度。
4.如权利要求1所述的集成电路装置，其中每一个该图案化缓冲层的所述多个分离部分为一圆柱状物，或其中该图案化缓冲层的所述多个分离部分形成彼此平行的条状物。
5.如权利要求4所述的集成电路装置，其中该裸片包括一长边和一短边，且其中所述条状物的长轴方向平行于该长边。
6.如权利要求1所述的集成电路装置，其中该图案化缓冲层的所述多个分离部分的第一个形成一第一环状物，包围该金属凸块。
7.如权利要求6所述的集成电路装置，其中该图案化缓冲层的所述多个分离部分的第二个形成一第二环状物，包围该第一环状物和该金属凸块。
8.如权利要求7所述的集成电路装置，其中该图案化缓冲层还包括实际上连接至该第一环状物和该第二环状物。
9.一种集成电路装置，包括：
一第一工件，包括一图案化缓冲层，其中该图案化缓冲层包括彼此隔开的多个分离部分；
一第二工件，位于该第一工件的上方；
一金属凸块，接合该第一工件和该第二工件；以及
一底部填充物，介于于该图案化缓冲层和该介电层之间，且接触该图案化缓冲层和该介电层，其中该底部填充物将该图案化缓冲层的所述多个分离部分彼此隔开。
10.如权利要求9所述的集成电路装置，其中该底部填充物接触该图案化缓冲层的所述多个分离部分的侧壁。
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