CN103855124B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN103855124B
CN103855124B CN201310597577.0A CN201310597577A CN103855124B CN 103855124 B CN103855124 B CN 103855124B CN 201310597577 A CN201310597577 A CN 201310597577A CN 103855124 B CN103855124 B CN 103855124B
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conductive
pattern
conductive layer
semiconductor structure
conductive pattern
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CN103855124A (zh
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金钟薰
裴弼淳
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明公开了一种半导体装置及其制造方法。该半导体装置包括:半导体结构,在其一个表面上形成有用于暴露焊盘的开口;第一导电层,形成在开口中以使半导体结构的一个表面更加均匀;以及导电图案,形成在半导体结构的部分的一个表面上,该一个表面包括第一导电层。

Description

半导体装置及其制造方法
技术领域
本发明大体上涉及半导体装置及其制造方法,更具体涉及具有诸如凸块和重分布线等的导电图案的半导体装置及其制造方法。
背景技术
电子工业的当前趋势涉及制造产品以实现重量减轻、装置小型化、高速运行、多功能性、高性能、高可靠性和制造成本降低。封装组装技术看作是实现许多上述产品设计中的特征的重要方面。
封装组装技术用于保护形成有集成电路的半导体芯片不受外部环境的影响且允许半导体芯片易于安装在基板上,从而保持半导体芯片的可靠运行。为了在封装体中组装半导体芯片,诸如凸块和重分布线等导电图案形成在半导体芯片上。
光刻工艺通常用于形成诸如凸块和重分布线等导电图案,并且包括在半导体芯片的其上设置焊盘的有源表面上顺序形成粘合剂层和籽层,在籽层上涂覆光致抗蚀剂,采用曝光和显影工艺图案化光致抗蚀剂以部分地曝光籽层,采用电镀工艺在籽层由图案化光致抗蚀剂暴露的部分上形成诸如凸块和重分布线等导电图案,去除光致抗蚀剂,并且采用导电图案作为掩模蚀刻籽层和粘合剂层。
然而,用光刻工艺形成导电图案的问题包括复杂的制造步骤和高制造成本,因为它要求许多工艺步骤,例如,如上所述的形成粘合剂层和籽层、光致抗蚀剂施加、曝光、显影、电镀、光致抗蚀剂去除以及粘合剂层和籽层的蚀刻。
发明内容
各种实施例大体上涉及可通过较简单工艺制造且具有改善的机械和电可靠性的半导体装置及其制造方法。
在一个实施例中,半导体装置包括:半导体结构,在其一个表面上形成有用于暴露焊盘的开口;形成在开口中的第一导电层;以及形成在半导体结构的部分的一个表面上的导电图案,该一个表面包括第一导电层,其中半导体结构的一个表面和第一导电层基本上共面。
导电图案可为凸块和重分布线中的任何一种。
半导体结构包括半导体芯片和印刷电路板中的任何一种。
半导体装置还可包括形成在导电图案上的第二导电层。
第二导电层可形成为包围导电图案。
第二导电层可仅形成在导电图案的一部分上。
半导体装置还可包括附加半导体结构,具有与第二导电层电连接的连接电极。
附加半导体结构可包括半导体芯片和印刷电路板中的任何一种。
半导体装置还可包括导电连接构件,电连接第二导电层和附加半导体结构的连接电极。
在另一个实施例中,制造半导体装置的方法包括:制备在其一个表面上形成有开口的半导体结构,该开口用于暴露焊盘;在开口中形成第一导电层以使半导体结构的一个表面更加均匀;以及采用滚动印刷工艺在半导体结构的部分的一个表面上形成导电图案,该一个表面包括第一导电层。
形成第一导电层可包括:在包括开口的一个表面上方形成导电层以填充开口,并且研磨导电层使得仅在开口中保留导电层。
可替换地,形成第一导电层可包括在开口中填充导电膏,并且烧结填充在开口中的导电膏。
第一导电层可包括Ni、Ni合金、Au、Au合金、Pt和Pt合金中的至少一种。
形成导电图案可包括:单元循环工艺,包括在版模的其上对应于导电图案的图案是凹陷的凹陷部分中形成导电墨成分的图案,接合辊与版模以转移版模上的导电墨成分的图案到辊上,并且将辊上的导电墨成分的图案转移到半导体结构的包括第一导电层的一个表面上,其中该单元循环工艺重复至少一次。
形成导电图案可包括:由以下步骤构成的单元循环工艺:在辊上涂覆导电墨成分,接合其上对应于导电图案的图案是凹陷的版模与辊以在辊上形成对应于辊上的导电图案的导电墨成分的图案,并且将辊上的导电墨成分的图案转移到半导体结构的包括第一导电层的一个表面上,其中该单元循环工艺重复至少一次。
该方法可进一步包括在形成导电图案后烧结导电图案。
导电图案包括凸块和重分布线中的任何一种。
导电图案包括Ag膏、包括Ag和聚合物的材料以及包括Cu膏和聚合物的材料中的任何一种。
该方法还可包括:在形成导电图案后在导电图案上形成第二导电层。
形成第二导电层可采用无电镀镀覆工艺执行。
形成第二导电层可以以第二导电层形成在导电图案的整个表面上的方式执行。可替换地,形成第二导电层可以以第二导电层形成在导电图案的一部分上的方式执行。
附图说明
图1A和1B是示出根据实施例的半导体装置的截面图。
图2是示出根据另一个实施例的半导体装置的截面图。
图3至9是示出根据本发明实施例的形成半导体装置的工艺步骤的截面图。
图10是示出根据各种实施例的具有半导体装置的电子设备的立体图。
图11是示出应用根据各种实施例的半导体装置的电子系统的系统方框图。
具体实施方式
在下文,将参考附图详细描述本发明的各种实施例。
图1A和1B是示出根据实施例的半导体装置的截面图。
根据实施例的半导体装置包括半导体结构100、第一导电层200和导电图案300。半导体装置还包括第二导电层400、附加半导体结构500和导电连接构件600。
半导体结构100具有一个表面110和与一个表面110相反的另一个表面120。暴露焊盘130的开口140形成在半导体结构100的一个表面110上。附图标记150表示无源层。在本实施例中,半导体结构100可由半导体芯片形成。可替换地,半导体结构100可由印刷电路板(PCB)形成。
导电图案300可通过滚动印刷工艺形成。滚动印刷工艺是指一种通过接合辊与基底而形成图案的方法,辊上形成有对应于所希望图案的墨成分的图案,墨成分的图案要转移基底上。滚动印刷工艺的优点包括工艺较简单以及制造成本低,其中通过将辊上的墨成分的图案直接转移到基底上而形成图案。然而,在滚动印刷工艺期间可能发生诸如图案抬起和剥落等机械缺陷,除非图案要转移到其上的基底执行为保持平坦表面。然而,因为半导体结构100在其一个表面110上形成有用于暴露焊盘130的开口140,所以不能保证平坦表面,当应用滚动印刷工艺以形成导电图案300时不能保证机械可靠性。
根据本实施例,第一导电层200形成在开口140中以使半导体结构100的一个表面110更加均匀。换言之,第一导电层200形成为填充开口140,从而去除了半导体结构100的一个表面110中由于开口140产生的高度差,因此允许半导体结构100的一个表面110更加均匀。结果,半导体结构的一个表面和第一导电层基本上共面。
第一导电层200可包括Ni、Ni合金、Au、Au合金、Pt和Pt合金中的至少一种。
导电图案300采用滚动印刷工艺形成在半导体结构100的包括第一导电层200的一个表面110的某些部分之上。在本实施例中,导电图案300形成为凸块。尽管导电图案300的宽度示出且描述为基本上与图1A和1B所示的开口140的宽度类似,但是导电图案300的宽度可大于或小于开口140的宽度。
此外,导电图案300可为通过如图1A所示的一次滚动印刷工艺形成的单一印刷层,或者导电图案300可具有其中多个这样的单一印刷层堆叠成至少两层的结构,如图1B所示。
导电图案300可包括Ag膏、包括Ag膏和聚合物的导电材料以及包括Cu膏和聚合物的导电材料中的任何一种。通过一次滚动印刷工艺形成的单一印刷层的厚度在采用具有聚合物的导电材料形成单一印刷层时是在采用没有聚合物的导电材料形成单一印刷层时的两倍至十倍厚。因此,可采用包括聚合物的导电材料以形成较厚的导电图案300。
因为通过滚动印刷工艺形成的导电图案300对焊料显示出差的粘合性,所以第二导电层400可通过无电镀覆工艺形成在导电图案300之上。在本实施例中,第二导电层400形成在导电图案300的整个表面之上以包围导电图案300。第二导电层400可包括Ni、Ni合金、Au、Au合金、Pt和Pt合金中的至少一种。
附加半导体结构500具有面对半导体结构100的一个表面510和与一个表面510相反的另一个表面520。附加半导体结构500在其一个表面510上具有连接电极530,其形成为与第二导电层400电连接。附加半导体结构500可由印刷电路板形成。附图标记540和550分别表示球焊盘和焊料球。
尽管附加半导体结构500在本实施例中示出且描述为印刷电路板,但是附加半导体结构500可为半导体芯片。
导电连接构件600形成在第二导电层400和附加半导体结构500的连接电极530之间以电连接第二导电层400和连接电极530。导电连接构件600可包括焊料。
图2是示出根据另一个实施例的半导体装置的截面图。
根据另一个实施例的半导体装置包括半导体结构100、第一导电层200和导电图案300。半导体装置还包括第二导电层400、附加半导体结构500、导电连接构件600和粘合剂构件700。
半导体结构100具有一个表面110和与一个表面110相反的另一个表面120,半导体结构100在其一个表面110上形成有开口140用于暴露焊盘130。附图标记150表示无源层。
在本实施例中,半导体结构100由半导体芯片形成,或者可替换地为印刷电路板。
第一导电层200形成为填充开口140使得半导体结构100的一个表面110由于开口140产生的高度差被去除,因此允许半导体结构100的一个表面110更加均匀。第一导电层200可包括Ni、Ni合金、Au、Au合金、Pt和Pt合金中的至少一种。
导电图案300采用滚动印刷工艺形成在半导体结构100的包括第一导电层200的一个表面110的某些部分之上。在本实施例中,导电图案300形成为重分布线。导电图案300的一端310与第一导电层200连接,并且与一端310相反的另一端320设置在半导体结构100的一个表面110的边缘上。此外,暴露导电图案300的另一端320的绝缘层800形成在半导体结构100的包括导电图案300的一个表面110之上。
导电图案300可为通过一次滚动印刷工艺形成的单一印刷层,或者可具有其中多个这样的单一印刷层堆叠成至少两层的结构。
导电图案300可包括Ag膏、包括Ag膏和聚合物的导电材料以及包括Cu膏和聚合物的导电材料中的至少一种。通过一次滚动印刷工艺形成的单一印刷层的厚度在采用具有聚合物的导电材料形成单一印刷层时是在采用没有聚合物的导电材料形成单一印刷层时的两倍到十倍厚。因此,可采用包括聚合物的导电材料以形成较厚的导电图案300。
在本实施例中,第二导电层400形成在导电图案300由绝缘层800暴露的另一端320之上。第二导电层400可为无电镀覆层,从导电图案300的由绝缘层800暴露的另一端320的表面生长,并且可包括Ni、Ni合金、Au、Au合金、Pt和Pt合金中的至少一种。
此外,半导体结构100的另一个表面120借助于粘合剂构件700附着到附加半导体结构500。
附加半导体结构500具有面对半导体结构100的一个表面510和与一个表面510相反的另一个表面520,并且在其一个表面510上形成有与第二导电层400电连接的连接电极530。在本实施例中,附加半导体结构500可由印刷电路板形成。附图标记540和550分别表示球焊盘和焊料球。尽管附加半导体结构500在本实施例中示出且描述为印刷电路板,但是附加半导体结构500可为半导体芯片。
导电连接构件600形成在第二导电层400和附加半导体结构500的连接电极530之间以电连接第二导电层400和连接电极530。在本实施例中,导电连接构件600可包括配线。
在下文,将描述形成上述半导体装置的方法。
图3至9是示出形成根据实施例的半导体装置的工艺步骤的截面图。
在图3中,半导体结构100的一个表面110上形成有暴露焊盘130的开口,第一导电层200形成为填充半导体结构100的开口140,从而去除半导体结构100的一个表面110中由于开口140产生的高度差,因此允许半导体结构100的一个表面110更加均匀。
第一导电层200可以以图4所示的方式形成,采用电镀工艺或无电镀覆工艺在半导体结构的包括开口140的一个表面110之上形成导电层200A以填充开口140,然后通过化学机械研磨(CMP)研磨导电层200A从而将导电层200限制在开口140的内部。附图标记PAD表示CMP机械的研磨板。
可替换地,如图5所示,第一导电层200可以这样的方式形成:采用填充机SQ在半导体结构100的一个表面110上涂覆导电膏200B以填充开口140然后烧结填充在开口140中的导电膏。
第一导电层200可包括Ni、Ni合金、Au、Au合金、Pt和Pt合金中的至少一种。
参见图6和7,导电图案300采用滚动印刷工艺形成在半导体结构100的包括第一导电层200的一个表面110的某些部分之上。
滚动印刷工艺可以以这样的方式执行:在版模30的凹陷部分中填充导电墨成分,版模30上对应于导电图案的图案是凹陷的,以形成导电墨成分的图案40,接合辊20的外表面上的毯层(blanket)21与版模30以将形成在版模30的凹陷部分中的导电墨成分的图案40转移到毯层21上,然后接合毯层21与半导体结构100以转移毯层21上的导电墨成分的图案40到半导体结构100上。
可替换地,如图8所示,滚动印刷工艺可执行为:在辊20的毯层21上涂覆导电墨成分40A,接合版模30(其上对应于导电图案的图案是凹陷的)与毯层21以选择性去除导电墨成分40A的对于形成导电图案不必要的部分,从而形成对应于毯层21上的导电图案的导电墨成分的图案40,然后接合毯层21与半导体结构100以转移毯层21上的导电墨成分的图案40到半导体结构100上。
接下来,滚动印刷工艺重复至少一次,直到转移到半导体结构100上的图案厚度达到所希望的厚度,因此形成导电图案300。
由于滚动印刷工艺在由于开口140引起的高度差通过第一导电层200被去除的表面上执行,诸如抬高和剥落等缺陷很少发生。
导电图案300可包括Ag膏、包括Ag膏和聚合物的导电材料和包括Cu膏和聚合物的导电材料中的任何一种。
在形成导电图案300的步骤后,可在大约250℃的温度下执行烧结工艺10至40分钟。
参见图9,第二导电层400形成在导电图案300之上以包围导电图案300。第二导电层400可采用无电镀覆工艺通过从导电图案300的表面生长无电镀覆层而形成。第二导电层400可包括Ni、Ni合金、Au、Au合金、Pt和Pt合金中的至少一种,但是为了防止氧化优选由例如Ni/Au的堆叠层形成。
此后,诸如图1A和1B所描述的焊料的导电连接构件600形成在第二导电层400之上,并且半导体结构100安装到附加半导体装置500使得第二导电层400借助于导电连接构件600与附加半导体装置500的连接电极530电连接,从而形成图1A和1B所示的半导体装置。
尽管本实施例示出且描述为当导电图案300形成为凸块时,第二导电层400可形成为包围导电图案300,并且第二导电层400和附加半导体结构500的连接电极530可借助于焊料制成的导电连接构件600电连接。也可形成图2所示的半导体装置,其中导电图案300形成为重分布线,第二导电层400仅形成在导电图案300的某些部分之上,并且第二导电层400和附加半导体结构500的连接电极530借助于配线制成的导电连接构件600电连接。
根据上述实施例,由于用于形成导电图案300的滚动印刷工艺施加在通过第一导电层200制作得均匀的表面之上,防止了诸如图案抬高和剥落等的缺陷发生,因此改善了机械可靠性。另外,由于与焊料具有良好粘合性的第二导电层400形成在导电图案300之上以改善与焊料的粘合性,改善了电可靠性。此外,由于能够有利地使用滚动印刷工艺(滚动印刷工艺由于其差的机械和电可靠性导致其使用困难)以形成诸如凸块和重分布线等导电图案300,所以与传统采用的光刻工艺相比,实现了简化工艺和降低制造成本。
根据各种实施例的半导体装置可应用于各种电子设备。
图10是示出具有根据各种实施例的半导体装置的电子设备的透视图。
在图10中,根据各种实施例的半导体装置可应用于诸如移动电话的电子设备1000,这可通过改善电子设备1000的价格竞争力和可靠性被证明是有利的,这是因为它可以以较低成本和较简单工艺制造为具有改善的机械和电可靠性。电子设备1000不限于图10所示的移动电话,而是可包括各种电子应用,例如移动电子应用、膝上计算机、笔记本电脑、便携式多媒体游戏机(PMP)、MP3游戏机、可携式摄像机、网络写字板、无线电话、导航仪、个人数字助理(PDA),等等。
图11是示出可包括根据各种实施例的半导体封装的电子设备的方块图。
在图11中,电子系统1300可包括控制器1310、输入/输出单元1320、和存储器1330,其可共同通过总线1350彼此耦合。总线1350用作数据通过其移动的通道,并且可包括微处理器、数字信号处理器、微控制器和能基本上实现与这些部件类似功能的逻辑装置中的至少任何一种。控制器1310和存储器1330可包括根据本发明各种实施例的半导体装置。输入/输出单元1320可包括至少一个键板、键盘、显示装置,等等。存储器1330是用于存储数据的装置,并且可存储控制器1310等也要执行的指令和/或数据。存储器1330可包括易失性存储器装置和/或非易失性存储器装置。另外,存储器1330可由闪存构成。例如,应用本发明技术的闪存存储器可安装到诸如移动终端或膝上计算机的信息处理系统。闪存存储器可由固态驱动器(SSD)构成,在固态驱动器上电子系统1300可稳定地存储大量的数据在闪存存储器系统中。电子系统1300还可包括接口1340,构造为输送数据到通讯网络以及从其接收数据。接口1340可为有线或无线形式,并且可包括天线或有线或无线收发器。此外,尽管没有示出,但是本领域的技术人员应容易理解,电子系统1300可附加地提供有应用芯片集、相机图像处理器(CIS)等。
尽管为了示出的目的描述了本发明的具体实施例,但是本领域的技术人员应理解,在不脱离如所附权利要求所公开的范围和精神的情况下,可进行各种变型、添加和替代。
本申请要求2012年11月29日提交韩国知识产权局的韩国专利申请第10-2012-0136907号的优先权,其全文通过引用结合于此。

Claims (9)

1.一种制造半导体装置的方法,包括如下步骤:
制备在其一个表面上形成有开口的半导体结构,该开口用于暴露焊盘;
在该开口中形成第一导电层以使该半导体结构的该一个表面更加均匀;以及
在该半导体结构的包括该第一导电层的部分的该一个表面上用滚动印刷工艺形成导电图案,
其中所述形成第一导电层的步骤包括如下步骤:
在包括所述开口的所述一个表面上方形成导电层以填充所述开口,并且
研磨所述导电层使得仅在所述开口中保留所述导电层。
2.根据权利要求1所述的方法,其中所述形成导电图案的步骤包括单元循环工艺,所述单元循环工艺包括如下步骤:
在版模的其上对应于所述导电图案的图案是凹陷的凹陷部分中形成导电墨成分的图案,
接合辊与所述版模以转移所述版模上的所述导电墨成分的图案到所述辊上,并且
将所述辊上的所述导电墨成分的图案转移到所述半导体结构的包括所述第一导电层的所述一个表面上,
其中所述单元循环工艺重复至少一次。
3.根据权利要求1所述的方法,其中所述形成导电图案的步骤包括由以下步骤构成的单元循环工艺:
在辊上涂覆导电墨成分,
接合其上对应于所述导电图案的图案是凹陷的版模与所述辊以在所述辊上形成对应于所述辊上的导电图案的所述导电墨成分的图案,并且
将所述辊上的所述导电墨成分的图案转移到所述半导体结构的包括所述第一导电层的所述一个表面上,
其中该单元循环工艺重复至少一次。
4.根据权利要求1所述的方法,还包括:在形成所述导电图案后,烧结所述导电图案的步骤。
5.根据权利要求1所述的方法,其中所述导电图案包括凸块和重分布线中的任何一种。
6.根据权利要求1所述的方法,还包括:在形成所述导电图案的步骤后,在所述导电图案上形成第二导电层的步骤。
7.根据权利要求6所述的方法,其中所述形成第二导电层的步骤采用无电镀镀覆工艺执行。
8.根据权利要求6所述的方法,其中所述形成第二导电层的步骤以所述第二导电层形成在所述导电图案的整个表面上的方式执行。
9.根据权利要求6所述的方法,其中所述形成第二导电层的步骤以所述第二导电层形成在所述导电图案的一部分上的方式执行。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101144610B1 (ko) * 2011-08-02 2012-05-11 한국기계연구원 투명 전극의 전도성 메쉬 매설 방법
TWI550525B (zh) * 2015-05-22 2016-09-21 南茂科技股份有限公司 導線圖案形成方法、指紋感測電路板及其製作方法
US9859241B1 (en) * 2016-09-01 2018-01-02 International Business Machines Corporation Method of forming a solder bump structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200414475A (en) * 2003-01-30 2004-08-01 Yu-Nung Shen Semiconductor chip package structure and method
CN101621045A (zh) * 2008-06-30 2010-01-06 海力士半导体有限公司 电路基板及其形成方法以及半导体封装
CN101728362A (zh) * 2008-10-28 2010-06-09 台湾积体电路制造股份有限公司 三维集成电路的堆叠接合界面结构
CN101874296A (zh) * 2007-09-28 2010-10-27 泰塞拉公司 利用成对凸柱进行倒装芯片互连
CN102299086A (zh) * 2010-06-28 2011-12-28 三星电子株式会社 半导体封装件及其制造方法和系统
CN102347288A (zh) * 2010-07-21 2012-02-08 台湾积体电路制造股份有限公司 集成电路装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08187927A (ja) * 1994-11-09 1996-07-23 Nippon Oil Co Ltd 印刷による転写方法
JP2008235555A (ja) * 2007-03-20 2008-10-02 Shinko Electric Ind Co Ltd 電子装置の製造方法及び基板及び半導体装置
TWI347643B (en) 2007-06-13 2011-08-21 Advanced Semiconductor Eng Under bump metallurgy structure and die structure using the same and method of manufacturing die structure
JP5372346B2 (ja) * 2007-07-18 2013-12-18 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
JP2013503234A (ja) * 2009-08-28 2013-01-31 エルジー・ケム・リミテッド 導電性金属インク組成物および導電性パターンの形成方法
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
KR101151255B1 (ko) * 2010-11-22 2012-06-15 앰코 테크놀로지 코리아 주식회사 반도체 칩의 재배선층 형성 장치 및 방법
KR101906408B1 (ko) * 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200414475A (en) * 2003-01-30 2004-08-01 Yu-Nung Shen Semiconductor chip package structure and method
CN101874296A (zh) * 2007-09-28 2010-10-27 泰塞拉公司 利用成对凸柱进行倒装芯片互连
CN101621045A (zh) * 2008-06-30 2010-01-06 海力士半导体有限公司 电路基板及其形成方法以及半导体封装
CN101728362A (zh) * 2008-10-28 2010-06-09 台湾积体电路制造股份有限公司 三维集成电路的堆叠接合界面结构
CN102299086A (zh) * 2010-06-28 2011-12-28 三星电子株式会社 半导体封装件及其制造方法和系统
CN102347288A (zh) * 2010-07-21 2012-02-08 台湾积体电路制造股份有限公司 集成电路装置

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CN103855124A (zh) 2014-06-11

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