CN102332410A - 一种芯片的封装方法及其封装结构 - Google Patents

一种芯片的封装方法及其封装结构 Download PDF

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Publication number
CN102332410A
CN102332410A CN201110293473A CN201110293473A CN102332410A CN 102332410 A CN102332410 A CN 102332410A CN 201110293473 A CN201110293473 A CN 201110293473A CN 201110293473 A CN201110293473 A CN 201110293473A CN 102332410 A CN102332410 A CN 102332410A
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Prior art keywords
substrate
chip
lead frame
outer enclosure
chip lead
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CN201110293473A
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Chinese (zh)
Inventor
濮必得
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong Sinochip Semiconductors Co Ltd
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Shandong Sinochip Semiconductors Co Ltd
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Priority to CN201110293473A priority Critical patent/CN102332410A/zh
Priority to PCT/CN2011/084993 priority patent/WO2013044566A1/fr
Publication of CN102332410A publication Critical patent/CN102332410A/zh
Pending legal-status Critical Current

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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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    • H01L2224/732—Location after the connecting process
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
CN201110293473A 2011-09-29 2011-09-29 一种芯片的封装方法及其封装结构 Pending CN102332410A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201110293473A CN102332410A (zh) 2011-09-29 2011-09-29 一种芯片的封装方法及其封装结构
PCT/CN2011/084993 WO2013044566A1 (fr) 2011-09-29 2011-12-30 Procédé d'encapsulation de puce et structure d'encapsulation associée

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110293473A CN102332410A (zh) 2011-09-29 2011-09-29 一种芯片的封装方法及其封装结构

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CN102332410A true CN102332410A (zh) 2012-01-25

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WO (1) WO2013044566A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105390477A (zh) * 2015-12-11 2016-03-09 苏州捷研芯纳米科技有限公司 一种多芯片3d二次封装半导体器件及其封装方法
CN106128964A (zh) * 2016-07-17 2016-11-16 王培培 一种叠层集成电路封装结构的封装方法
CN106206458A (zh) * 2016-07-17 2016-12-07 王培培 一种叠层集成电路封装结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1287382A (zh) * 1999-06-24 2001-03-14 三菱电机株式会社 半导体装置及其安装结构
CN1301903A (zh) * 1999-12-30 2001-07-04 王榕生 自攻式钢筋连接件
CN102148224A (zh) * 2010-02-08 2011-08-10 株式会社东芝 Led模块

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Publication number Priority date Publication date Assignee Title
JPH05198722A (ja) * 1992-01-21 1993-08-06 Mitsubishi Electric Corp 半導体装置
JPH09107047A (ja) * 1995-10-13 1997-04-22 Hitachi Ltd 半導体装置およびその製造方法ならびに電子装置
KR20030019439A (ko) * 2000-07-19 2003-03-06 신도 덴시 고교 가부시키가이샤 반도체장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1287382A (zh) * 1999-06-24 2001-03-14 三菱电机株式会社 半导体装置及其安装结构
CN1301903A (zh) * 1999-12-30 2001-07-04 王榕生 自攻式钢筋连接件
CN102148224A (zh) * 2010-02-08 2011-08-10 株式会社东芝 Led模块

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105390477A (zh) * 2015-12-11 2016-03-09 苏州捷研芯纳米科技有限公司 一种多芯片3d二次封装半导体器件及其封装方法
CN105390477B (zh) * 2015-12-11 2018-08-17 苏州捷研芯纳米科技有限公司 一种多芯片3d二次封装半导体器件及其封装方法
CN106128964A (zh) * 2016-07-17 2016-11-16 王培培 一种叠层集成电路封装结构的封装方法
CN106206458A (zh) * 2016-07-17 2016-12-07 王培培 一种叠层集成电路封装结构
CN106206458B (zh) * 2016-07-17 2018-09-25 高燕妮 一种叠层集成电路封装结构
CN106128964B (zh) * 2016-07-17 2018-10-02 高燕妮 一种叠层集成电路封装结构的封装方法

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Application publication date: 20120125