CN102332410A - Packaging method and structure of chip - Google Patents

Packaging method and structure of chip Download PDF

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Publication number
CN102332410A
CN102332410A CN201110293473A CN201110293473A CN102332410A CN 102332410 A CN102332410 A CN 102332410A CN 201110293473 A CN201110293473 A CN 201110293473A CN 201110293473 A CN201110293473 A CN 201110293473A CN 102332410 A CN102332410 A CN 102332410A
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China
Prior art keywords
substrate
chip
lead frame
outer enclosure
chip lead
Prior art date
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Pending
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CN201110293473A
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Chinese (zh)
Inventor
濮必得
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong Sinochip Semiconductors Co Ltd
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Shandong Sinochip Semiconductors Co Ltd
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Publication date
Application filed by Shandong Sinochip Semiconductors Co Ltd filed Critical Shandong Sinochip Semiconductors Co Ltd
Priority to CN201110293473A priority Critical patent/CN102332410A/en
Priority to PCT/CN2011/084993 priority patent/WO2013044566A1/en
Publication of CN102332410A publication Critical patent/CN102332410A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention relates to a packaging method and structure of a chip. The method comprises the following steps of: 1, installing the chip in an independent chip lead frame or substrate; and 2, connecting one side of the obtained chip lead frame or substrate to an external packaging substrate. By using the packaging method and structure of the chip, the packaging deformation can be avoided, the packaging stability is high, the electric property is good, and the application scope is wide.

Description

A kind of method for packing of chip and encapsulating structure thereof
Technical field
The invention belongs to the electronic devices and components field; The packaged type that relates to a kind of chip; Relate in particular to a kind of method for packing and encapsulating structure thereof of highly reliable, superchip; This Chip Packaging can be applied to can realize the high-density packages of memory or other semiconductor chip, promptly littler pin, better stability and more outstanding hot property in the electronic application product of any computer, notebook, work station and other use semiconductor device.
Background technology
Present computer system is used independent Chip Packaging, i.e. single semiconductor chip encapsulation or the encapsulation of so-called multicore sheet.Wherein a kind of of following dual mode all adopted in multicore sheet of today encapsulation: 1) semiconductor chip is installed on the shared substrate; And they are not overlapping on vertical direction, and this is a kind of arrangement mode with respect to traditional PCB plate (printed circuit board printed circuit board (PCB)); 2) the mutual range upon range of placement of semiconductor chip, with respect to the horizontal plane long-pending whole welded encapsulation perhaps is placed on the application circuit board.In this case, place four chips usually in vertical direction.
There is very big shortcoming in this above-mentioned dual mode: the arrangement form of any similar 1) sharing same substrate needs very large-area pin.The cost of substrate is very high, the characteristic of signal is very poor, because signal demand is connected to package outside below semiconductor chip.The stability of this encapsulation neither be very high, because the area of chip substrate is very big, the temperature coefficient of chip and substrate does not match, and makes easily to encapsulate the (see figure 1) that distorts.
Based on 2) layout similar shortcoming is also arranged.Though but the distortion of the little encapsulation of pin area easy deformation, and because the stack and the adhesion stability of multilayer are poorer.The outside that pad is connected to single chip is used to the bonding connection.Because middle chip is isolated, and connect, good thermal conductivity can not be arranged, so its temperature performance can very poor (see figure 2) with very little lead-in wire.
Summary of the invention
In order to solve the problems referred to above that exist in the background technology, the invention provides and a kind ofly avoid encapsulating that distortion, packaged stability are high, the method for packing and the encapsulating structure thereof of the chip of good electric property and applied range.
A kind of method for packing of chip may further comprise the steps:
1) chip is installed on independent the chip lead frame or substrate;
2) one side with resulting chip lead frame of step 1) or substrate is connected to the outer enclosure substrate.
Above-mentioned steps 2) concrete implementation is:
Chip lead frame or substrate pass and are arranged on the base plate for packaging pin bores and directly use as the outer enclosure pin through being arranged on metal pins on chip lead frame or the substrate.
Above-mentioned steps 2) concrete implementation is:
Chip lead frame or substrate are connected on the soldered ball of outer enclosure substrate through line.
Said chip lead frame or substrate are one or more.
Above-mentioned lead frame or substrate are vertically connected on the plane of outer enclosure substrate.
When said chip lead frame or substrate were a plurality of, said a plurality of lead frames or substrate were arranged in parallel.
Carrying out compound between above-mentioned lead frame or the substrate fills.
A kind of encapsulating structure of chip, its special character is: the encapsulating structure of said chip comprises chip, chip lead frame or substrate and outer enclosure substrate; Said chip is installed on chip lead frame or the substrate; One side of said chip lead frame or substrate is connected to the outer enclosure substrate.
Said chip lead frame or substrate are to be connected through circular distal or non-circular end with the outer enclosure substrate.
When the part that said chip lead frame or substrate are connected with the outer enclosure substrate is non-circular distal, saidly passes and be arranged on the base plate for packaging pin bores and directly use as the outer enclosure pin through being arranged on metal pins on chip lead frame or the substrate.
When the part that said chip lead frame or substrate are connected with the outer enclosure substrate was circular distal, said circular distal was connected on the soldered ball of outer enclosure substrate through the line on the base plate for packaging.
Said chip lead frame or substrate are vertically connected on the outer enclosure substrate; Said chip lead frame or substrate are one or more, when said chip lead frame or substrate are a plurality of, are parallel to each other between said a plurality of chip lead frames or the substrate.
Advantage of the present invention is:
1, can avoid the encapsulation distortion, packaged stability is high.Chip packaging method provided by the present invention; Be on the connection bottom substrate that chip is vertical and chip itself does not have vertical overlapping; Each chip all is to be directly connected on the outer enclosure substrate through lead frame or metal pins; Very firm can avoid the encapsulation distortion, and reliable fully, packaged stability is high.
2, good electric property.The method for packing of this chip that the present invention is mentioned is the top that the another one base plate for packaging can be placed on this encapsulation, this will be better symmetry and have no distortion, heat radiation protection is better.Simultaneously, single chip is installed on independent the chip lead frame or substrate, and these lead frames or substrate directly are connected on the bottom substrate; Do not need line to be connected on the bottom substrate, chip lead frame or substrate are very simple, and line is also very short; It is with low cost, good electric property.
3, applied range.The mentioned chip packaging method of the present invention can be applied in the electronic application product of any computer, notebook, work station and other use semiconductor device; Can realize high reliability, the high-density packages of memory or other semiconductor chip, range of application is boundless.
Description of drawings
Fig. 1 is that the prior art chips is at the schematic layout pattern of sharing on the substrate;
Fig. 2 is the overlapping schematic layout pattern of prior art chips level;
Fig. 3 is that the prior art chips is placed in the structural representation on the lead frame;
Fig. 4 is based on the chip mount of method for packing provided by the present invention at the structural representation with monolateral lead frame first embodiment of non-circular end;
Fig. 5 is based on the structural representation of the chip mount of method for packing provided by the present invention at monolateral lead frame second embodiment with circular distal;
Fig. 6 is that the prior art chips is placed in the structural representation on the substrate;
The chip mount that Fig. 7 is based on method for packing provided by the present invention has the first example structure sketch map on the monolateral substrate of non-circular end;
The chip mount that Fig. 8 is based on method for packing provided by the present invention has the second example structure sketch map on the monolateral substrate of circular distal;
Fig. 9 is based on Fig. 4 or Fig. 7 and realizes the example structure sketch map of the high-density packages of chip;
Figure 10 is based on Fig. 5 or Fig. 8 and realizes the example structure sketch map of the high-density packages of chip.
Wherein:
The 1-chip; The 2-lead-in wire; The 3-lead frame; The 4-substrate; The 5-soldered ball; 6-outer enclosure substrate; The 7-packaging solder ball; Line on the 8-base plate for packaging; The 9-encapsulating shell; The pin bores of 10-base plate for packaging.
Embodiment
The invention provides a kind of method for packing of chip, this method may further comprise the steps:
1) chip 1 is installed on independent chip lead frame or the substrate (lead frame 3 or substrate 4);
2) one side with resulting chip lead frame of step 1) or substrate is connected to outer enclosure substrate 6, and chip lead frame or substrate are one or more.
Chip lead frame or substrate pass and are arranged on the base plate for packaging pin bores and directly use as the outer enclosure pin through being arranged on metal pins on chip lead frame or the substrate, and perhaps chip lead frame or substrate are connected on the soldered ball 5 of outer enclosure through line.
3) to step 2) in chip lead frame or substrate carry out compound and fill.
When chip lead frame or substrate are a plurality of, on the plane that is placed in outer enclosure that chip lead frame or substrate are vertical; Be arranged in parallel between a plurality of chip lead frames or the substrate.
A kind of encapsulating structure of chip, the encapsulating structure of this chip comprise chip 1, chip lead frame 3 or substrate 4 and outer enclosure substrate 6; Chip 1 is arranged on chip lead frame 3 or the substrate 4 and is connected with the metal pins of chip lead frame 3 or substrate 4 through lead-in wire 2; One side of chip lead frame 3 or substrate 4 is connected to outer enclosure substrate 6.
Chip lead frame 3 or substrate 4 pass and are arranged on the base plate for packaging pin bores and directly use as the outer enclosure pin through being arranged on metal pins on chip lead frame 3 or the substrate 4.
When chip lead frame 3 or substrate 4 are connected with the packaging solder ball 7 of outer enclosure substrate 6, the rounded end of part that chip lead frame 3 or substrate 4 are connected with outer enclosure substrate 6.
The part that lead frame 3 or substrate 4 are connected with outer enclosure substrate 6 is circular distal or non-circular end; When the part that is connected with outer enclosure substrate 6 when lead frame 3 or substrate 4 was non-circular distal, the pin of lead frame 3 or substrate 4 directly used as the pin of outer enclosure; The pin of lead frame 3 or substrate 4 directly uses as the outer enclosure pin through the pin bores 10 that is arranged on the base plate for packaging on the outer enclosure substrate 6.When the part that is connected with outer enclosure substrate 6 when lead frame 3 or substrate 4 metal pins was circular distal, circular distal was connected on the packaging solder ball 7 through the line on the outer enclosure substrate 8.
Chip lead frame 3 or substrate 4 are one or more, and chip lead frame 3 or substrate 4 are vertically set on the outer enclosure substrate 6; When chip lead frame 3 or substrate 4 were a plurality of, a plurality of chip lead frames 3 or substrate 4 were parallel to each other.
In order to realize above-mentioned packing forms, chip 1 at first need be installed on independent the chip lead frame or substrate, the technology before this is similar to.The layout of technology before Fig. 3 and Fig. 6 have shown.Chip 1 be installed on the lead frame 3 or substrate 4 on (chip lead frame or substrate).Previous technology can not realize the high density that is proposed, the encapsulation of high reliability, and this is conspicuous.For new packing forms, the pin of all chips 1 all is connected to one side of outside base plate for packaging 6.Chip lead frame or substrate layout through using Fig. 4, Fig. 5, Fig. 7 and Fig. 8 can realize new packing forms.If leadframe metal and other pin can be connected to the pin of outer enclosure, two kinds of structures all are possible: the metal pins of lead frame 3 or substrate 4 passes the pin bores that is arranged on the base plate for packaging and directly uses as the outer enclosure pin.In this case, the metal pins of lead frame 3 or substrate 4 directly uses as the outer enclosure pin, and is shown in figure 10.A kind of in addition structure is as shown in Figure 9.External pin is positioned on the outer enclosure substrate 6, promptly typical packaging solder ball 7 forms.
Above-mentioned two kinds of situation, the mould of the vertical layout of chip lead frame or substrate can insert in the mould of Chip Packaging, can be used as the superchip module like this and uses.For example, a plurality of semiconductor memory chips can be put in the high density storage construct, encapsulate through encapsulating shell 9 at last.With respect to existing technology, this method also has the another one advantage, because chip is mounted on single the chip lead frame or substrate, before finally being installed in outer enclosure substrate and mould, they can be by single processing and test.Defective like this chip is discovery and the replacement of morning more.
Fig. 9 and Figure 10 have shown whole structures of new encapsulation.Chip be vertical be placed on the bottom package substrate but chip 1 does not have itself vertical overlapping.This has good heat-conductive characteristic, because each chip all is to be directly connected on the bottom package substrate 6 through lead frame 3 or substrate 4.In addition, this layout is that the very firm encapsulation of can avoiding is out of shape, fully reliably.For better symmetry and better heat radiation protection, the another one base plate for packaging can be placed on the top of this encapsulation, and this will be better symmetrical and have no distortion.Single chip is installed on independent the chip lead frame or substrate; These lead frames or substrate directly are connected on the bottom package substrate 6; Do not need the line on the substrate to be connected on the bottom package substrate, chip lead frame or substrate are very simple, and line is also very short.Such result is that cost is very low, electric property is fine.

Claims (10)

1. the method for packing of a chip is characterized in that: said method comprising the steps of:
1) chip is installed on independent the chip lead frame or substrate;
2) one side with resulting chip lead frame of step 1) or substrate is connected to the outer enclosure substrate.
2. the method for packing of chip according to claim 1, it is characterized in that: concrete implementation said step 2) is:
Chip lead frame or substrate pass and are arranged on the base plate for packaging pin bores and directly use as the outer enclosure pin through being arranged on metal pins on chip lead frame or the substrate.
3. the method for packing of chip according to claim 1, it is characterized in that: concrete implementation said step 2) is:
Said chip lead frame or substrate are connected on the soldered ball of outer enclosure substrate through line.
4. according to the method for packing of claim 2 or 3 described chips, it is characterized in that: said chip lead frame or substrate are one or more; When said chip lead frame or substrate were a plurality of, said a plurality of lead frames or substrate were arranged in parallel; Said lead frame or substrate are vertically connected on the plane of outer enclosure substrate.
5. the method for packing of chip according to claim 4, it is characterized in that: the method for packing of said chip also comprises:
3) carrying out compound between lead frame or the substrate fills.
6. the encapsulating structure of a chip, it is characterized in that: the encapsulating structure of said chip comprises chip, chip lead frame or substrate and outer enclosure substrate; Said chip is installed on chip lead frame or the substrate; One side of said chip lead frame or substrate is connected to the outer enclosure substrate.
7. the encapsulating structure of chip according to claim 6, it is characterized in that: said chip lead frame or substrate are to be connected through circular distal or non-circular end with the outer enclosure substrate.
8. the encapsulating structure of chip according to claim 7; It is characterized in that: when the part that said chip lead frame or substrate are connected with the outer enclosure substrate is non-circular distal, saidly passes and be arranged on the base plate for packaging pin bores and directly use as the outer enclosure pin through being arranged on metal pins on chip lead frame or the substrate.
9. according to the encapsulating structure of claim 7 or 8 described chips; It is characterized in that: when the part that said chip lead frame or substrate are connected with the outer enclosure substrate was circular distal, said circular distal was connected on the soldered ball of outer enclosure substrate through the line on the base plate for packaging.
10. the encapsulating structure of chip according to claim 9, it is characterized in that: said chip lead frame or substrate are vertically connected on the outer enclosure substrate; Said chip lead frame or substrate are one or more, when said chip lead frame or substrate are a plurality of, are parallel to each other between said a plurality of chip lead frames or the substrate.
CN201110293473A 2011-09-29 2011-09-29 Packaging method and structure of chip Pending CN102332410A (en)

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PCT/CN2011/084993 WO2013044566A1 (en) 2011-09-29 2011-12-30 Chip encapsulation method and encapsulation structure thereof

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CN106128964A (en) * 2016-07-17 2016-11-16 王培培 A kind of method for packing of stacked integrated circuit encapsulating structure
CN106206458A (en) * 2016-07-17 2016-12-07 王培培 A kind of stacked integrated circuit encapsulating structure

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CN1287382A (en) * 1999-06-24 2001-03-14 三菱电机株式会社 Semiconductor apparatus and its mounting structure
CN1301903A (en) * 1999-12-30 2001-07-04 王榕生 Self tapping steel bar connector
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CN106128964A (en) * 2016-07-17 2016-11-16 王培培 A kind of method for packing of stacked integrated circuit encapsulating structure
CN106206458A (en) * 2016-07-17 2016-12-07 王培培 A kind of stacked integrated circuit encapsulating structure
CN106206458B (en) * 2016-07-17 2018-09-25 高燕妮 A kind of stacked integrated circuit encapsulating structure
CN106128964B (en) * 2016-07-17 2018-10-02 高燕妮 A kind of packaging method of stacked integrated circuit encapsulating structure

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