CN202259245U - Packaging structure for chip - Google Patents

Packaging structure for chip Download PDF

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Publication number
CN202259245U
CN202259245U CN2011203770683U CN201120377068U CN202259245U CN 202259245 U CN202259245 U CN 202259245U CN 2011203770683 U CN2011203770683 U CN 2011203770683U CN 201120377068 U CN201120377068 U CN 201120377068U CN 202259245 U CN202259245 U CN 202259245U
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CN
China
Prior art keywords
substrate
chip
lead frame
outer enclosure
packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2011203770683U
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Chinese (zh)
Inventor
濮必得
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xian Unilc Semiconductors Co Ltd
Original Assignee
Xian Sinochip Semiconductors Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to CN2011203770683U priority Critical patent/CN202259245U/en
Application granted granted Critical
Publication of CN202259245U publication Critical patent/CN202259245U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model relates to a packaging structure for a chip. The packaging structure for the chip comprises the chip, a chip lead frame or substrate and an external packaging substrate. The chip is arranged on the chip lead frame or substrate. One side of the chip lead frame or substrate is connected to the external packaging substrate. The utility model provides the packaging structure for the chip, which can be used for avoiding packaging deformation and has high packaging stability, good electrical performance and wide application range.

Description

A kind of encapsulating structure of chip
Technical field
The utility model belongs to the electronic devices and components field; The packaged type that relates to a kind of chip; Relate in particular to a kind of encapsulating structure of highly reliable, superchip; This Chip Packaging can be applied to can realize the high-density packages of memory or other semiconductor chip, promptly littler pin, better stability and more outstanding hot property in the electronic application product of any computer, notebook, work station and other use semiconductor device.
Background technology
Present computer system is used independent Chip Packaging, i.e. single semiconductor chip encapsulation or the encapsulation of so-called multicore sheet.Wherein a kind of of following dual mode all adopted in multicore sheet of today encapsulation: 1) semiconductor chip is installed on the shared substrate; And they are not overlapping on vertical direction, and this is a kind of arrangement mode with respect to traditional PCB plate (printed circuit board printed circuit board (PCB)); 2) the mutual range upon range of placement of semiconductor chip, with respect to the horizontal plane long-pending whole welded encapsulation perhaps is placed on the application circuit board.In this case, place four chips usually in vertical direction.
There is very big shortcoming in this above-mentioned dual mode: the arrangement form of any similar 1) sharing same substrate needs very large-area pin.The cost of substrate is very high, the characteristic of signal is very poor, because signal demand is connected to package outside below semiconductor chip.The stability of this encapsulation neither be very high, because the area of chip substrate is very big, the temperature coefficient of chip and substrate does not match, and makes easily to encapsulate the (see figure 1) that distorts.
Based on 2) layout similar shortcoming is also arranged.Though but the distortion of the little encapsulation of pin area easy deformation, and because the stack and the adhesion stability of multilayer are poorer.The outside that pad is connected to single chip is used to the bonding connection.Because middle chip is isolated, and connect, good thermal conductivity can not be arranged, so its temperature performance can very poor (see figure 2) with very little lead-in wire.
The utility model content
In order to solve the problems referred to above that exist in the background technology, the utility model provides a kind of and has avoided encapsulating that distortion, packaged stability are high, the encapsulating structure of the chip of good electric property and applied range.
A kind of encapsulating structure of chip, the encapsulating structure of said chip comprise chip, chip lead frame or substrate and outer enclosure substrate; Said chip is installed on chip lead frame or the substrate; One side of said chip lead frame or substrate is connected to the outer enclosure substrate.
Said chip lead frame or substrate are to be connected through circular distal or non-circular end with the outer enclosure substrate.
When the part that said chip lead frame or substrate are connected with the outer enclosure substrate is non-circular distal, saidly passes and be arranged on the base plate for packaging pin bores and directly use as the outer enclosure pin through being arranged on metal pins on chip lead frame or the substrate.
When the part that said chip lead frame or substrate are connected with the outer enclosure substrate was circular distal, said circular distal was connected on the soldered ball of outer enclosure substrate through the line on the base plate for packaging.
Said chip lead frame or substrate are vertically connected on the outer enclosure substrate; Said chip lead frame or substrate are one or more, when said chip lead frame or substrate are a plurality of, are parallel to each other between said a plurality of chip lead frames or the substrate.
The utility model has the advantages that:
1, can avoid the encapsulation distortion, packaged stability is high.The chip-packaging structure that the utility model provided is on the connection bottom substrate that chip is vertical and chip itself does not have vertical overlapping; Each chip all is to be directly connected on the outer enclosure substrate through lead frame or metal pins; Very firm can avoid the encapsulation distortion; Reliable fully, packaged stability is high.
2, good electric property.The encapsulating structure of this chip that the utility model is mentioned is the top that the another one base plate for packaging can be placed on this encapsulation, this will be better symmetry and have no distortion, heat radiation protection is better.Simultaneously, single chip is installed on independent the chip lead frame or substrate, and these lead frames or substrate directly are connected on the bottom substrate; Do not need line to be connected on the bottom substrate, chip lead frame or substrate are very simple, and line is also very short; It is with low cost, good electric property.
3, applied range.The mentioned chip-packaging structure of the utility model can be applied in the electronic application product of any computer, notebook, work station and other use semiconductor device; Can realize high reliability, the high-density packages of memory or other semiconductor chip, range of application is boundless.
Description of drawings
Fig. 1 is that the prior art chips is at the schematic layout pattern of sharing on the substrate;
Fig. 2 is the overlapping schematic layout pattern of prior art chips level;
Fig. 3 is that the prior art chips is placed in the structural representation on the lead frame;
Fig. 4 is based on the chip mount of encapsulating structure that the utility model provides at the structural representation with monolateral lead frame first embodiment of non-circular end;
Fig. 5 is based on the structural representation of the chip mount of encapsulating structure that the utility model provides at monolateral lead frame second embodiment with circular distal;
Fig. 6 is that the prior art chips is placed in the structural representation on the substrate;
The chip mount that Fig. 7 is based on encapsulating structure that the utility model provides has the first example structure sketch map on the monolateral substrate of non-circular end;
The chip mount that Fig. 8 is based on encapsulating structure that the utility model provides has the second example structure sketch map on the monolateral substrate of circular distal;
Fig. 9 is based on Fig. 4 or Fig. 7 and realizes the example structure sketch map of the high-density packages of chip;
Figure 10 is based on Fig. 5 or Fig. 8 and realizes the example structure sketch map of the high-density packages of chip.
Wherein:
The 1-chip; The 2-lead-in wire; The 3-lead frame; The 4-substrate; The 5-soldered ball; 6-outer enclosure substrate; The 7-packaging solder ball; Line on the 8-base plate for packaging; The 9-encapsulating shell; The pin bores of 10-base plate for packaging.
Embodiment
The utility model provides a kind of encapsulating structure of chip, and the encapsulating structure of this chip comprises chip 1, chip lead frame 3 or substrate 4 and outer enclosure substrate 6; Chip 1 is arranged on chip lead frame 3 or the substrate 4 and is connected with the metal pins of chip lead frame 3 or substrate 4 through lead-in wire 2; One side of chip lead frame 3 or substrate 4 is connected to outer enclosure substrate 6.
Chip lead frame 3 or substrate 4 pass and are arranged on the base plate for packaging pin bores and directly use as the outer enclosure pin through being arranged on metal pins on chip lead frame 3 or the substrate 4.
When chip lead frame 3 or substrate 4 are connected with the packaging solder ball 7 of outer enclosure substrate 6, the rounded end of part that chip lead frame 3 or substrate 4 are connected with outer enclosure substrate 6.
The part that lead frame 3 or substrate 4 are connected with outer enclosure substrate 6 is circular distal or non-circular end; When the part that is connected with outer enclosure substrate 6 when lead frame 3 or substrate 4 was non-circular distal, the pin of lead frame 3 or substrate 4 directly used as the pin of outer enclosure; The pin of lead frame 3 or substrate 4 directly uses as the outer enclosure pin through the pin bores 10 that is arranged on the base plate for packaging on the outer enclosure substrate 6.When the part that is connected with outer enclosure substrate 6 when lead frame 3 or substrate 4 metal pins was circular distal, circular distal was connected on the packaging solder ball 7 through the line on the outer enclosure substrate 8.
Chip lead frame 3 or substrate 4 are one or more, and chip lead frame 3 or substrate 4 are vertically set on the outer enclosure substrate 6; When chip lead frame 3 or substrate 4 were a plurality of, a plurality of chip lead frames 3 or substrate 4 were parallel to each other.
In order to realize above-mentioned packing forms, chip 1 at first need be installed on independent the chip lead frame or substrate, the technology before this is similar to.The layout of technology before Fig. 3 and Fig. 6 have shown.Chip 1 be installed on the lead frame 3 or substrate 4 on (chip lead frame or substrate).Previous technology can not realize the high density that is proposed, the encapsulation of high reliability, and this is conspicuous.For new packing forms, the pin of all chips 1 all is connected to one side of outside base plate for packaging 6.Chip lead frame or substrate layout through using Fig. 4, Fig. 5, Fig. 7 and Fig. 8 can realize new packing forms.If leadframe metal and other pin can be connected to the pin of outer enclosure, two kinds of structures all are possible: the metal pins of lead frame 3 or substrate 4 passes the pin bores that is arranged on the base plate for packaging and directly uses as the outer enclosure pin.In this case, the metal pins of lead frame 3 or substrate 4 directly uses as the outer enclosure pin, and is shown in figure 10.A kind of in addition structure is as shown in Figure 9.External pin is positioned on the outer enclosure substrate 6, promptly typical packaging solder ball 7 forms.
Above-mentioned two kinds of situation, the mould of the vertical layout of chip lead frame or substrate can insert in the mould of Chip Packaging, can be used as the superchip module like this and uses.For example, a plurality of semiconductor memory chips can be put in the high density storage construct, encapsulate through encapsulating shell 9 at last.With respect to existing technology, this structure also has the another one advantage, because chip is mounted on single the chip lead frame or substrate, before finally being installed in outer enclosure substrate and mould, they can be by single processing and test.Defective like this chip is discovery and the replacement of morning more.
Fig. 9 and Figure 10 have shown whole structures of new encapsulation.Chip be vertical be placed on the bottom package substrate but chip 1 does not have itself vertical overlapping.This has good heat-conductive characteristic, because each chip all is to be directly connected on the bottom package substrate 6 through lead frame 3 or substrate 4.In addition, this layout is that the very firm encapsulation of can avoiding is out of shape, fully reliably.For better symmetry and better heat radiation protection, the another one base plate for packaging can be placed on the top of this encapsulation, and this will be better symmetrical and have no distortion.Single chip is installed on independent the chip lead frame or substrate; These lead frames or substrate directly are connected on the bottom package substrate 6; Do not need the line on the substrate to be connected on the bottom package substrate, chip lead frame or substrate are very simple, and line is also very short.Such result is that cost is very low, electric property is fine.

Claims (5)

1. the encapsulating structure of a chip, it is characterized in that: the encapsulating structure of said chip comprises chip, chip lead frame or substrate and outer enclosure substrate; Said chip is installed on chip lead frame or the substrate; One side of said chip lead frame or substrate is connected to the outer enclosure substrate.
2. the encapsulating structure of chip according to claim 1, it is characterized in that: said chip lead frame or substrate are to be connected through circular distal or non-circular end with the outer enclosure substrate.
3. the encapsulating structure of chip according to claim 5; It is characterized in that: when the part that said chip lead frame or substrate are connected with the outer enclosure substrate is non-circular distal, saidly passes and be arranged on the base plate for packaging pin bores and directly use as the outer enclosure pin through being arranged on metal pins on chip lead frame or the substrate.
4. according to the encapsulating structure of claim 2 or 3 described chips; It is characterized in that: when the part that said chip lead frame or substrate are connected with the outer enclosure substrate was circular distal, said circular distal was connected on the soldered ball of outer enclosure substrate through the line on the base plate for packaging.
5. the encapsulating structure of chip according to claim 4, it is characterized in that: said chip lead frame or substrate are vertically connected on the outer enclosure substrate; Said chip lead frame or substrate are one or more, when said chip lead frame or substrate are a plurality of, are parallel to each other between said a plurality of chip lead frames or the substrate.
CN2011203770683U 2011-09-29 2011-09-29 Packaging structure for chip Expired - Lifetime CN202259245U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011203770683U CN202259245U (en) 2011-09-29 2011-09-29 Packaging structure for chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011203770683U CN202259245U (en) 2011-09-29 2011-09-29 Packaging structure for chip

Publications (1)

Publication Number Publication Date
CN202259245U true CN202259245U (en) 2012-05-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011203770683U Expired - Lifetime CN202259245U (en) 2011-09-29 2011-09-29 Packaging structure for chip

Country Status (1)

Country Link
CN (1) CN202259245U (en)

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: 710055 4, A block 38, hi tech six road, hi tech Zone, Xi'an, Shaanxi.

Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd.

Address before: 710055, A, building 4, Tengfei innovation center, 38 hi tech 6 road, Shaanxi, Xi'an

Patentee before: Xi'an Sinochip Semiconductors Co., Ltd.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20120530