CN203118947U - Embedded storage device - Google Patents
Embedded storage device Download PDFInfo
- Publication number
- CN203118947U CN203118947U CN201320055817XU CN201320055817U CN203118947U CN 203118947 U CN203118947 U CN 203118947U CN 201320055817X U CN201320055817X U CN 201320055817XU CN 201320055817 U CN201320055817 U CN 201320055817U CN 203118947 U CN203118947 U CN 203118947U
- Authority
- CN
- China
- Prior art keywords
- circuit board
- printed circuit
- pcb
- components
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
The utility model relates to the technical field of electronics, and provides an embedded storage device. The device comprises a first printed circuit board, at least two components, a packaging body and a second printed circuit board, the components includes a first component arranged on the first printed circuit board and a second component arranged on the first component, the second printed circuit board is arranged on the second component, a surface of the first component which is in contact with the first printed circuit board is provided with a first pad, a surface of the first printed circuit board which is away from the first component is provided with a second pad, the first pad of the first component is connected with a first lead, the first lead passes through the first printed circuit board and is electrically connected with the second pad, and the second printed circuit board is electrically connected with the first printed circuit board and the second component through a second lead and a third lead respectively. In the embodiment, an inner packaging structure of the embedded storage device is optimized through stacking of the components, decreasing the occupied volume of the device, and enabling the embedded storage device to be flexibly applied to more small-sized electronic products.
Description
Technical field
The utility model relates to electronic technology field, more particularly, relates to a kind of embedded memory device.
Background technology
Existing embedded memory device, as eMCP(embedded multi-chip package, embedded internal memory), SDRAM(Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory) encapsulating structure generally as shown in Figure 1.In this enclosed construction, each components and parts 100 ' dispersion be welded on first printed circuit board (PCB) 200 ' on, taken first printed circuit board (PCB) 200 ' bigger area in surface like this, cause adopting packaging body 300 ' whole embedded memory device volume in encapsulation back bigger, thereby also limited its application scenario, in the electronic product internal structure that can not be applied in some small and exquisite exquisitenesses flexibly.And, in this structure, each components and parts 100 ' by lead 400 ' with first printed circuit board (PCB) 200 ' electric connection, generally speaking, used lead 100 ' be the gold thread material is because that it connects span is bigger, cause poor signal easily and be unfavorable for producing the raising production cost.
The utility model content
Technical problem to be solved in the utility model is to overcome the defective of prior art, provide a kind of rationally distributed, take up room little, widely used embedded memory device.
For solving the problems of the technologies described above, the utility model: a kind of embedded memory device is provided, comprise first printed circuit board (PCB), place on described first printed circuit board (PCB) and with the components and parts of its electric connection and the packaging body that described first printed circuit board (PCB) and components and parts is packaged in one, also comprise second printed circuit board (PCB), described components and parts have two at least, and described components and parts comprise that first components and parts that place on described first printed circuit board (PCB) and insulation are stacked and placed on second components and parts on described first components and parts, described second printed circuit board (PCB) is stacked and placed on described second components and parts, described first components and parts are provided with first pad with the surface that described first printed circuit board (PCB) contacts, described first printed circuit board (PCB) is provided with second pad away from the surface of described first components and parts, first pad of described first components and parts connects first lead, described first lead passes described first printed circuit board (PCB) and is electrically connected with described second pad, described second printed circuit board (PCB) is electrically connected with described first printed circuit board (PCB) by second lead, and described second printed circuit board (PCB) is electrically connected with described second components and parts by privates.
Particularly, described first lead is two rows, described two ranked first lead is connected on the different solder joints with the end that first pad of described first components and parts is electrically connected, and described two ranked first lead is connected on the different solder joints with the other end that described second pad is electrically connected.
Further, described first printed circuit board (PCB) is provided with the upper and lower groove that runs through, and described two ranked first lead passes described groove.
Further, on the surface at the described first printed circuit board (PCB) second pad place and corresponding described groove place is provided with colloid, and described colloid is provided with for ccontaining and protect described first lead to be electrically connected the groove of solder joint with described second pad.
Further, the surface at the described first printed circuit board (PCB) second pad place is provided with some soldered balls that can be electrically connected with the external electrical product.
Particularly, described second components and parts are provided with the 3rd pad away from the surface of described first components and parts, another relative with surface, the described second pad place on described first printed circuit board (PCB) surface is provided with the 4th pad, described second printed circuit board (PCB) is provided with the 5th pad away from the surface of described second components and parts, one end of described second lead is electrically connected with the 5th pad of described second printed circuit board (PCB), the other end of described second lead is electrically connected with the 4th pad of described first printed circuit board (PCB), one end of described privates is electrically connected with the 5th pad of described second printed circuit board (PCB), and the other end of described privates is electrically connected with the 3rd pad of described second components and parts.
Further, described second printed circuit board (PCB) has two, and is provided with the gap between two second printed circuit board (PCB)s.
Preferably, described first components and parts and described second components and parts are the DDR memory.
In the utility model, the volume that stacks to reduce inner encapsulating structure by components and parts, optimize the inside encapsulating structure of embedded memory device, make embedded memory device can be applied on the more small-sized electronic product flexibly, and by rational wire laying mode, reduce the production difficulty, improve and produce yield.
Description of drawings
Fig. 1 is the cutaway view of a kind of embedded memory device in the prior art;
Fig. 2 is the cutaway view of the embedded memory device that provides of the utility model.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
With reference to Fig. 2, the utility model provides a kind of embedded memory device, comprise first printed circuit board (PCB) 100, place on first printed circuit board (PCB) 100 and with the components and parts 200 of its electric connection and the packaging body 300 that first printed circuit board (PCB) 100 and components and parts 200 is packaged in one.First printed circuit board (PCB) 100, the basis that provides each components and parts in the embedded storage device to electrically connect, and be close to packaging body 300.Packaging body 300 is coated on components and parts 200 and first printed circuit board (PCB) 100 in the space, makes each parts not be vulnerable to external pollution, destruction.Particularly, in the present embodiment, embedded memory device also comprises second printed circuit board (PCB) 400, components and parts 200 have two at least, and components and parts 200 comprise and place first components and parts 210 on first printed circuit board (PCB) 100 and place second components and parts 220 on first components and parts 210.Wherein, first components and parts 210 and second components and parts, 220 contacted two surfaces all do not arrange pad, be insulating surfaces, be adjacent to placement with insulating surfaces separately when the two is stacked, specifically can adopt glue or viscose glue that the two is fixed, such first components and parts 210 and second components and parts, 220 stacked backs do not have electric connection.The surface that first components and parts 210 contact with first printed circuit board (PCB) 100 is namely by in the orientation shown in Fig. 2, the bottom surface of first yuan of device 210 is provided with the first pad (not shown), be that end face in the orientation shown in Figure 2 is provided with second pad on first surface of printed circuit board (PCB) 100 away from first components and parts 210, connect first lead 500 on first pad of first components and parts 210, first lead 500 passes first printed circuit board (PCB) 100 and is electrically connected with second pad, thereby realizes the electric connection of first components and parts 210 and first printed circuit board (PCB) 100.Here, first pad of first components and parts 210 is close to first printed circuit board (PCB) 100 has effectively simplified wiring between first components and parts 210 and first printed circuit board (PCB) 100, make the lead 500 of winning directly pass first printed circuit board (PCB) 100 from first components and parts 210 and cause on second pad.And second printed circuit board (PCB) 400 is stacked and placed on second components and parts 220, and second printed circuit board (PCB) 400 is electrically connected with first printed circuit board (PCB) 100 by second lead 600, and second printed circuit board (PCB) 400 is electrically connected with second components and parts 220 by privates 700.In the present embodiment, optimize the inner encapsulating structure of embedded storage device by stacking of components and parts, take volume thereby reduce it, make embedded storage device to be applied in flexibly on the more small-sized electronic product.
As the prioritization scheme of present embodiment, first lead 500 is two rows.The end that this two first pad that ranked first lead 500 and first components and parts 210 is electrically connected is connected on the different solder joints, and is same, and two ranked first lead 500 is connected on the different solder joints with the other end of second pad electrical connection.Namely two ranked first the pad of lead 500 on first components and parts 210 and first printed circuit board (PCB) 100 and do not repeat, thereby realize different connection functions.
Particularly, the upper and lower groove that runs through 110, two being set on first printed circuit board (PCB) 100 ranked first lead 500 and from then on passes on second pad that is connected to first printed circuit board (PCB), 100 bottoms in the groove 110 simultaneously.Certainly, two grooves 110 can be set also herein, ranked first lead 500 with two and keep apart, avoid interfering.
As the further prioritization scheme of present embodiment, on the surface at first printed circuit board (PCB), 100 second pad places and 110 places, corresponding groove place are provided with colloid 310, colloid 310 is provided with the solder joint that groove 311, the first leads 500 are electrically connected with second pad and places in the groove 311.The effect that groove 311 plays the solder joint that is electrically connected with second pad of protection first lead 500 is set herein.
Further, in the present embodiment, the surface at first printed circuit board (PCB), 100 second pad places is provided with some soldered balls 320 that can be electrically connected with the external electrical product.Like this, make things convenient for embedded storage devices to be electrically connected with the external electrical product by soldered ball 320, thereby realize the function of embedded storage device.
In the present embodiment, second components and parts 220 away from the surface of first components and parts 210 namely the end face shown in the figure be provided with the 3rd pad, be provided with the 4th pad (not shown) with another surface that namely end face shown in the figure is relative, surface, the second pad place on first printed circuit board (PCB) 100, second printed circuit board (PCB) 400 is provided with the 5th pad (not shown) away from the surface of second components and parts 220, one end of second lead 600 is electrically connected with the 5th pad of second printed circuit board (PCB) 400, the other end of second lead 600 is electrically connected with the 4th pad of first printed circuit board (PCB) 100, one end of privates 700 is electrically connected with the 5th pad of second printed circuit board (PCB) 400, and the other end of privates 700 is electrically connected with the 3rd pad of second components and parts 220.
Further, in the present embodiment, second printed circuit board (PCB) 400 is two, and is provided with the gap between two second printed circuit board (PCB)s 400.This gap is used for privates 700 is set, and realizes the electric connection between two second printed circuit board (PCB)s 400 and second components and parts 220, and then by the electric connection of second lead, 600 realizations with first printed circuit board (PCB) 100.Like this, do not need to be routed on first printed circuit board (PCB) 100 from second components and parts 220, reduce the span that connects up, reduce the production difficulty, improve and produce yield.
In the present embodiment, first components and parts 210 and second components and parts 220 are memory, be specially DDR(Double Data Rate, the Double Data Rate synchronous DRAM), adopt BGA(Ball GridArray, spherical pin grid array encapsulation technology) after the encapsulation, namely constituted SDRAM(SynchronousDynamic Random Access Memory, synchronous DRAM).
To sum up, in the utility model, the volume that stacks to reduce inner encapsulating structure by components and parts, optimize the inside encapsulating structure of embedded memory device, make embedded memory device can be applied on the more small-sized electronic product flexibly, and by rational wire laying mode, reduce the production difficulty, improve and produce yield.
Below only be preferred embodiment of the present utility model, not in order to limiting the utility model, all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (8)
1. embedded memory device, comprise first printed circuit board (PCB), place on described first printed circuit board (PCB) and with the components and parts of its electric connection and the packaging body that described first printed circuit board (PCB) and components and parts is packaged in one, it is characterized in that: also comprise second printed circuit board (PCB), described components and parts have two at least, and described components and parts comprise that first components and parts that place on described first printed circuit board (PCB) and insulation are stacked and placed on second components and parts on described first components and parts, described second printed circuit board (PCB) is stacked and placed on described second components and parts, described first components and parts are provided with first pad with the surface that described first printed circuit board (PCB) contacts, described first printed circuit board (PCB) is provided with second pad away from the surface of described first components and parts, first pad of described first components and parts connects first lead, described first lead passes described first printed circuit board (PCB) and is electrically connected with described second pad, described second printed circuit board (PCB) is electrically connected with described first printed circuit board (PCB) by second lead, and described second printed circuit board (PCB) is electrically connected with described second components and parts by privates.
2. embedded memory device as claimed in claim 1, it is characterized in that: described first lead is two rows, described two ranked first lead is connected on the different solder joints with the end that first pad of described first components and parts is electrically connected, and described two ranked first lead is connected on the different solder joints with the other end that described second pad is electrically connected.
3. embedded memory device as claimed in claim 2, it is characterized in that: described first printed circuit board (PCB) is provided with the upper and lower groove that runs through, and described two ranked first lead passes described groove.
4. embedded memory device as claimed in claim 3; it is characterized in that: on the surface at the described first printed circuit board (PCB) second pad place and corresponding described groove place is provided with colloid, and described colloid is provided with for ccontaining and protect described first lead to be electrically connected the groove of solder joint with described second pad.
5. embedded memory device as claimed in claim 4, it is characterized in that: the surface at the described first printed circuit board (PCB) second pad place is provided with some soldered balls that can be electrically connected with the external electrical product.
6. as each described embedded memory device in the claim 1 to 5, it is characterized in that: described second components and parts are provided with the 3rd pad away from the surface of described first components and parts, another relative with surface, the described second pad place on described first printed circuit board (PCB) surface is provided with the 4th pad, described second printed circuit board (PCB) is provided with the 5th pad away from the surface of described second components and parts, one end of described second lead is electrically connected with the 5th pad of described second printed circuit board (PCB), the other end of described second lead is electrically connected with the 4th pad of described first printed circuit board (PCB), one end of described privates is electrically connected with the 5th pad of described second printed circuit board (PCB), and the other end of described privates is electrically connected with the 3rd pad of described second components and parts.
7. embedded memory device as claimed in claim 6, it is characterized in that: described second printed circuit board (PCB) has two, and is provided with the gap between two second printed circuit board (PCB)s.
8. embedded memory device as claimed in claim 7, it is characterized in that: described first components and parts and described second components and parts are the DDR memory.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320055817XU CN203118947U (en) | 2013-01-31 | 2013-01-31 | Embedded storage device |
| TW102206515U TWM463908U (en) | 2013-01-31 | 2013-04-10 | Embedded storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320055817XU CN203118947U (en) | 2013-01-31 | 2013-01-31 | Embedded storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203118947U true CN203118947U (en) | 2013-08-07 |
Family
ID=48899266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320055817XU Expired - Lifetime CN203118947U (en) | 2013-01-31 | 2013-01-31 | Embedded storage device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN203118947U (en) |
| TW (1) | TWM463908U (en) |
-
2013
- 2013-01-31 CN CN201320055817XU patent/CN203118947U/en not_active Expired - Lifetime
- 2013-04-10 TW TW102206515U patent/TWM463908U/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TWM463908U (en) | 2013-10-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101046394B1 (en) | Stack package | |
| KR100688501B1 (en) | Dual-Inline-Memory-Module mounted stack Board-On-Chip packages with mirroring structure | |
| US9123554B2 (en) | Semiconductor device | |
| US9299685B2 (en) | Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer | |
| US20130037930A1 (en) | Semiconductor chip and semiconductor package having the same | |
| TW201342569A (en) | Interposer for stacked semiconductor devices | |
| CN203721707U (en) | Chip packaging structure | |
| KR20090025908A (en) | Electronic device having a stack-type semiconductor package and method of forming the same | |
| KR20160037846A (en) | Electronic module | |
| JP2009252893A (en) | Semiconductor device | |
| CN203536467U (en) | LED device having transition substrate | |
| CN103035627A (en) | Stack type semiconductor packaging structure | |
| CN202443963U (en) | Semiconductor substrate package structure | |
| CN102222656A (en) | Leadframe package for high-speed data rate applications | |
| CN101193497A (en) | Reinforced shakeproof memory | |
| CN203118947U (en) | Embedded storage device | |
| CN100541643C (en) | Accumulator system | |
| CN203118946U (en) | Embedded storing device | |
| CN105374805A (en) | Multi-chip packaging structure | |
| US20130277801A1 (en) | Chip package | |
| CN105845642A (en) | Laminated packaging unit and mobile terminal | |
| CN211529945U (en) | System-in-package integrating multiple chips and elements | |
| CN104051450A (en) | Semiconductor package assembly | |
| CN216902922U (en) | Lead frame and semiconductor device | |
| CN203225247U (en) | An integrated circuit packaging body |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518057 A, B, C, D, E, F1, 8 Building, Financial Services Technology Innovation Base, No. 8 Kefa Road, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SHENZHEN LONGSYS ELECTRONICS Co.,Ltd. Address before: 518057 A, B, C, D, E, F1, 8 Building, Financial Services Technology Innovation Base, No. 8 Kefa Road, Nanshan District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN NETCOM ELECTRONICS Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130807 |
|
| CX01 | Expiry of patent term |