CN102214684A - 一种具有悬空源漏的半导体结构及其形成方法 - Google Patents

一种具有悬空源漏的半导体结构及其形成方法 Download PDF

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CN102214684A
CN102214684A CN2011101498218A CN201110149821A CN102214684A CN 102214684 A CN102214684 A CN 102214684A CN 2011101498218 A CN2011101498218 A CN 2011101498218A CN 201110149821 A CN201110149821 A CN 201110149821A CN 102214684 A CN102214684 A CN 102214684A
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semiconductor structure
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CN102214684B (zh
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王敬
郭磊
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Tsinghua University
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Tsinghua University
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Abstract

本发明提出一种具有悬空源漏的半导体结构，包括：衬底；形成在衬底之上的多个凸起结构；形成在所述每两个凸起结构之间，且与两个凸起结构顶部相连的悬空薄层，其中，凸起结构为沟道，凸起结构两侧的悬空薄层为源极和漏极，且在所述凸起结构之间填充有绝缘材料以使作为沟道的所述凸起结构产生应变；和形成在所述凸起结构之上的栅堆叠。本发明实施例采用悬空的源漏结构，一方面使得源漏中掺杂杂质向衬底的扩散被抑制，从而易制备超浅结，另一方面由于源漏及衬底之间不存在接触，因此还可以抑制源漏与衬底之间的BTBT漏电。此外，本发明实施例通过在凸起结构之间填充的绝缘材料以使做为沟道的凸起结构产生应变，从而进一步提高器件性能。

Description

一种具有悬空源漏的半导体结构及其形成方法
技术领域
本发明涉及半导体设计及制造技术领域，特别涉及一种具有悬空源漏的半导体结构及其形成方法。
背景技术
长期以来，为了获得更高的芯片密度、更快的工作速度以及更低的功耗。金属-氧化物-半导体场效应晶体管(MOSFET)的特征尺寸一直遵循着所谓的摩尔定律(Moore’slaw)不断按比例缩小，其工作速度越来越快。当前已经进入到了纳米尺度的范围。然而，随之而来的一个严重的挑战是出现了短沟道效应，例如亚阈值电压下跌(Vt roll-off)、漏极引起势垒降低(DIBL)、源漏穿通(punch through)等现象，使得器件的关态泄漏电流显著增大，从而导致性能发生恶化。
此外通过SOI(Silicon On Insulator)结构可以降低漏电，但SOI中的SiO2绝缘层的导热率低，小尺寸器件中沟道内产生的热量不易散出，因此SOI器件的散热受到抑制。
因此，对于目前的器件结构来说，漏电大和散热难是制约器件小型化的关键因素。
发明内容
本发明的目的旨在至少解决上述技术缺陷之一，特别是解决现有技术中器件漏电大的缺陷。
本发明一方面提出了一种具有悬空源漏的半导体结构，包括：衬底；形成在所述衬底之上的多个凸起结构，其中，每两个凸起结构之间具有一定间隙，所述间隙小于50nm；形成在所述每两个凸起结构之间，且与所述两个凸起结构顶部相连的悬空薄层，其中，所述凸起结构为沟道，所述凸起结构两侧的悬空薄层为源极和漏极，且在所述凸起结构之间填充有绝缘材料以使作为沟道的所述凸起结构产生应变；和形成在所述凸起结构之上的栅堆叠。
在本发明的一个实施例中，所述凸起结构从所述凸起结构的中部向顶部逐渐增大以使两个凸起结构顶部之间的间隙小于所述两个凸起结构中部之间的间隙。
在本发明的一个实施例中，所述凸起结构为多层结构。
在本发明的一个实施例中，所述悬空薄层通过对所述多个凸起结构退火形成，所述退火温度为800-1350度，且在退火时气氛中含有氢气。
在本发明的一个实施例中，所述绝缘材料为SixNy、SiO2或SiOxNy中的至少一种。
在本发明的一个实施例中，所述绝缘材料包括：第一绝缘材料；以及位于所述第一绝缘材料及所述凸起结构之间，以及所述第一绝缘材料及所述衬底之间的第二绝缘材料。
在本发明的一个实施例中，所述第一绝缘材料为SixNy或SiOxNy，所述第二绝缘材料为SiO2。
在本发明的一个实施例中，在所述第一绝缘材料中掺杂C。
在本发明的一个实施例中，还包括：形成在所述栅堆叠两侧的一层或多层侧墙。
本发明实施例还提出了一种具有悬空源漏的半导体结构的形成方法，包括以下步骤：提供衬底；在所述衬底之上形成多个凸起结构，所述每两个凸起结构之间具有一定间隙，所述间隙小于50nm；在所述每两个凸起结构之间填充绝缘材料；在所述每两个凸起结构之间及所述绝缘材料之上形成悬空薄层，且所述悬空薄层与所述两个凸起结构顶部相连；在所述凸起结构之上形成栅堆叠；和对所述栅堆叠两侧的悬空薄层进行掺杂以使所述凸起结构形成为沟道，所述凸起结构两侧的悬空薄层形成为源极和漏极。
在本发明的一个实施例中，所述凸起结构从所述凸起结构的中部向顶部逐渐增大以使两个凸起结构顶部之间的间隙小于所述两个凸起结构中部之间的间隙。
在本发明的一个实施例中，所述悬空薄层通过对所述多个凸起结构退火形成，所述退火温度为800-1350度，且在退火时气氛中含有氢气。
在本发明的一个实施例中，还包括：去除位于隔离区域中的悬空薄层以形成隔离结构。
在本发明的一个实施例中，还包括：在所述栅堆叠两侧形成一层或多层侧墙。
在本发明的一个实施例中，所述绝缘材料为SixNy、SiO2或SiOxNy中的至少一种。
在本发明的一个实施例中，所述在每两个凸起结构之间填充绝缘材料进一步包括：对所述凸起结构的两侧及所述衬底的露出部分进行氧化以产生SiO2层；和在所述每两个凸起结构之间及所述SiO2层之上外延SixNy或SiOxNy。
在本发明的一个实施例中，还包括：在所述SixNy或SiOxNy之中掺杂C。
在本发明的一个实施例中，所述悬空薄层通过外延形成。
本发明实施例采用悬空的源漏结构，一方面使得源漏中掺杂杂质向衬底的扩散被抑制，从而易制备超浅结，另一方面由于源漏及衬底之间不存在接触，因此还可以抑制源漏与衬底之间的BTBT漏电。此外，本发明实施例通过在凸起结构之间填充的绝缘材料以使做为沟道的凸起结构产生应变，从而进一步提高器件性能。本发明实施例减小了源漏的寄生结电容，提高了器件的性能。并且通过本发明实施例可以形成Si1-xCx、高Ge组分SiGe、Ge或III-V族化合物半导体材料的悬空薄层，从而改善器件性能。在本发明的实施例中，还可在绝缘材料SixNy或SiOxNy中掺杂C，从而能够极大地提高凸起结构的应变度。
本发明附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本发明一个实施例的具有悬空源漏的半导体结构的结构图；
图2为本发明另一个实施例的具有悬空源漏的半导体结构的结构图；
图3为本发明实施例的多层凸起结构的示意图；
图4为本发明一个实施例形成两个共用源极或漏极的半导体结构示意图；
图5为本发明另一个实施例形成两个共用源极或漏极的半导体结构示意图；
图6为本发明实施例的具有悬空源漏的半导体结构的形成方法流程图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
如图1所示，为本发明实施例的具有悬空源漏的半导体结构的结构图。如图2所示，为本发明另一个实施例的具有悬空源漏的半导体结构的结构图。该具有悬空源漏的半导体结构包括衬底1100，形成在衬底1100之上的多个凸起结构1200，其中，每两个凸起结构1200之间具有一定间隙，该间隙小于50nm，优选地小于30nm。需要说明的是，在本发明的一个实施例之中凸起结构可为垂直结构，而在图2和图3的实施例中，凸起结构1200从凸起结构1200的中部向顶部逐渐增大以使两个凸起结构1200顶部之间的间隙小于两个凸起结构1200中部之间的间隙，从而可以通过退火或外延形成悬空薄层1300。如果对于两个凸起结构1200顶部之间间隙大于中部之间间隙的情况来说，上述预定距离是两个凸起结构1200之间的最近距离，即两个凸起结构1200顶部之间的距离。本发明适于小尺寸器件，特别适于解决小尺寸器件的漏电问题。
该半导体结构还包括形成在每两个凸起结构1200之间，且与两个凸起结构1200顶部相连的悬空薄层1300，其中，凸起结构1200为沟道，凸起结构1200两侧的悬空薄层1300为源极和漏极。该半导体结构还包括形成在凸起结构1200之上的栅堆叠1400。其中，栅堆叠1400包括栅介质层和栅电极，例如为高k栅介质层等。在该实施例中，示出了两个独立的半导体结构，每个半导体结构构成一个器件，两者之间相互隔离，具体地，两个半导体结构之间的悬空薄层1300被刻蚀掉从而形成隔离结构。在该实施例中，每个独立的半导体结构包括三个凸起结构1200，依次包括第一凸起结构至第三凸起结构，其中，第二凸起结构(位于中间)为沟道，第一凸起结构和所述第二凸起结构之间的悬空薄层为源极，第二凸起结构和第三凸起结构之间的悬空薄层为漏极。悬空薄层1300通常都很薄，一般约为10nm以下，从而可以用于制备超浅结。
其中，凸起结构1200为沟道，凸起结构两侧的悬空薄层1300为源极和漏极，且在凸起结构1200之间填充有绝缘材料2000以使做为沟道的凸起结构1200产生应变。具体地，绝缘材料2000可为SixNy、SiO2或SiOxNy中的至少一种，其中，x和y为整数，例如SiN等。在SixNy、SiO2或SiOxNy中掺杂C，优选地，C的浓度低于10％，从而可以极大地提高应变度。
在本发明的优选实施例中，绝缘材料2000包括第一绝缘材料(SixNy或SiOxNy)和第二绝缘材料(SiO2)，其中，第二绝缘材料位于第一绝缘材料及凸起结构之间，以及第一绝缘材料及衬底之间，即第二绝缘材料包围第一绝缘材料。优选地，由于SixNy的活性，因此采用SiO2将其包围。
在本发明的一个实施例中，衬底1100包括Si或低Ge组分SiGe，悬空薄层1300包括Si1-xCx、高Ge组分SiGe、Ge等。
在本发明的一个实施例中，悬空薄层1300可通过对多个凸起结构1200退火形成。本发明实施例通过高温氢气氛退火能使表面原子发生迁移，退火温度一般约在800-1350度，同时在本发明实施例中退火时还需要气氛中含有氢气，氢气能有效地促进表面原子的迁移。优选地，当凸起结构1200包括高Ge组分SiGe或Ge时，在退火时还通入SiH4、GeH4、SiH2Cl2、SiHCl3中的一种或多种气体，通过气体分解在表面沉积少量的Si和/或Ge原子，以使获得的半导体薄层表面更加平整，从而获得更好的效果。在退火之后，两个相邻的多个凸起结构1200的顶部会相互接触从而形成悬空薄层1300。在本发明实施例中对于凸起结构材料不同，其退火温度也不同，例如对于Si材料来说，一般退火温度较高，约1200度左右，而对于Ge材料来说，退火温度较低，约900度左右。
在本发明的另一个实施例中，凸起结构1200为多层结构，其中，多层凸起结构中的最顶层为Si1-xCx、高Ge组分SiGe、Ge。如图2所示，为本发明实施例的多层凸起结构的示意图。其中，所述多层结构中的最顶层为Si1-xCx、高Ge组分SiGe、Ge。例如对图3来说，凸起结构1200的底层为低Ge组分的SiGe层，顶层为Ge层。这样低Ge组分的SiGe层可以作为衬底1100和Ge层之间的过渡层。
在本发明的一个实施例中，该半导体结构还包括形成在栅堆叠1400两侧的一层或多层侧墙，从而可以使得源极和漏极与沟道的界面层延伸至凸起结构材料之中，以改善结的界面特性，进一步提高器件性能。
在本发明的其他实施例中，还可形成两个共用源极或漏极的半导体结构，如图4和5所示。在该实施例中，还包括与第二凸起结构或第三凸起结构相邻的第四凸起结构或第五凸起结构，第二凸起结构或第三凸起结构为沟道以形成共用源极或漏极的器件。
如图6所示，为本发明实施例的具有悬空源漏的半导体结构的形成方法流程图，包括以下步骤：
步骤S601，提供衬底，其中，衬底包括Si或低Ge组分SiGe。
步骤S602，在衬底之上形成多个凸起结构，所述每两个凸起结构之间具有一定间隙，一般该间隙小于50nm，优选地小于30nm。凸起结构从凸起结构的中部向顶部逐渐增大以使两个凸起结构顶部之间的间隙小于两个凸起结构中部之间的间隙，从而可以通过退火或外延形成悬空薄层。具体地，在衬底之上先外延一层或多层半导体材料，例如高Ge组分SiGe、Ge的第一半导体材料层。当然在本发明的其他实施例中，也可以将衬底表层作为第一半导体材料层，即直接在衬底的表面进行刻蚀以形成多个凸起结构。
优选地，为了形成图1所示的凸起结构，需要采用具有各向异性的湿法刻蚀对外延的第一半导体材料层进行刻蚀。
或者，可替换地，在另一个优选实施例中，先向第一半导体材料层之中注入Si或Ge离子以在第一半导体材料层之中形成离子注入层，接着采用干法刻蚀对第一半导体材料层进行选择性刻蚀以形成多个凸起结构，由于离子注入层中损伤严重，晶体结构被打乱，其刻蚀速度大于第一半导体材料层其他部分的刻蚀速度，从而可以形成图2所示的结构。
步骤S603，在每两个凸起结构之间填充绝缘材料，例如SiN或SiO2。优选地，首先对凸起结构的两侧及衬底的露出部分进行氧化以产生SiO2层，接着在每两个凸起结构之间及SiO2层之上外延SixNy或SiOxNy，例如SiN。
在本发明的一个实施例中，在填充了绝缘材料之后，还需要将在凸起结构表面的绝缘材料去除，以及将凸起结构顶部侧面的一些绝缘材料去除。在本发明的实施例中，去除凸起结构顶部侧面的绝缘材料只要在后续工艺能够不影响凸起结构之间的顶部的闭合即可。
步骤S604，在每两个凸起结构之间形成悬空薄层，且悬空薄层与两个凸起结构顶部相连，其中，悬空薄层包括Si1-xCx、高Ge组分SiGe、Ge等。在本发明的一个实施例中，悬空薄层可通过对多个凸起结构退火形成。本发明实施例通过退火能使表面材料发生迁移，退火温度一般约在800-1350度，同时在本发明实施例中退火时还需要气氛中含有氢气。优选地，当凸起结构1200包括高Ge组分SiGe或Ge时，在退火时还通入SiH4、GeH4、SiH2Cl2、SiHCl3中的一种或多种气体，通过气体分解在表面沉积少量的Si和/或Ge原子，以使获得的半导体薄层表面更加平整，从而获得更好的效果。
在本发明的另一个实施例中，还可通过外延的方式形成悬空薄层。包括表面为(100)晶向的Si、Si1-xCx、SiGe、Ge衬底，由于外延材料在顶部的侧向生长速度不小于纵向生长速度，从而可以使得外延的材料很快将两个凸起结构之间顶部的间隙封闭，从而悬空薄层与衬底之间不会直接接触，从而依然能够保持悬空薄层的一部份相对于衬底悬空。在本发明的另一个实施例中，如果悬空薄层通过外延形成，则悬空薄层还可以为III-V族化合物半导体材料。在本发明的一个实施例中，凸起结构为多层结构，其中，多层结构中的最顶层为Si1-xCx、高Ge组分SiGe、Ge。
在本发明的一个优选实施例中，如果退火之后悬空薄层的厚度比较厚的话，则还需要对该悬空薄层进行刻蚀或减薄处理。
步骤S605，在凸起结构之上形成栅堆叠。
步骤S606，在栅堆叠两侧形成一层或多层侧墙。
步骤S607，对栅堆叠两侧的悬空薄层进行掺杂以使凸起结构形成为沟道，凸起结构两侧的悬空薄层形成为源极和漏极。
在本发明的优选实施例中，还需要去除位于隔离区域中的悬空薄层以形成隔离结构。
本发明实施例采用悬空的源漏结构，一方面使得源漏中掺杂杂质向衬底的扩散被抑制，从而易制备超浅结，另一方面由于源漏及衬底之间不存在接触，因此还可以抑制源漏与衬底之间的BTBT漏电。此外，本发明实施例通过在凸起结构之间填充的绝缘材料以使做为沟道的凸起结构产生应变，从而进一步提高器件性能。本发明实施例减小了源漏的寄生结电容，提高了器件的性能。并且通过本发明实施例可以形成Si1-xCx、高Ge组分SiGe、Ge或III-V族化合物半导体材料的悬空薄层，从而改善器件性能。如果采用SOI结构时，沟道的散热会受到绝缘层的阻碍，而本发明通过采用凸起结构作为沟道，可以有效解决SOI结构中绝缘层对散热的抑制问题，同时还可以同SOI结构一样，降低器件的漏电，从而进一步改善器件性能。在本发明的实施例中，还可在绝缘材料中掺杂C，优选地，C的浓度低于10％，从而能够极大地提高凸起结构的应变度。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同限定。

Claims (19)

1.一种具有悬空源漏的半导体结构，其特征在于，包括：
衬底；
形成在所述衬底之上的多个凸起结构，其中，每两个凸起结构之间具有一定间隙，所述间隙小于50nm；
形成在所述每两个凸起结构之间，且与所述两个凸起结构顶部相连的悬空薄层，其中，所述凸起结构为沟道，所述凸起结构两侧的悬空薄层为源极和漏极，且在所述凸起结构之间填充有绝缘材料以使作为沟道的所述凸起结构产生应变；和
形成在所述凸起结构之上的栅堆叠。
2.如权利要求1所述的具有悬空源漏的半导体结构，其特征在于，所述凸起结构从所述凸起结构的中部向顶部逐渐增大以使两个凸起结构顶部之间的间隙小于所述两个凸起结构中部之间的间隙。
3.如权利要求1所述的具有悬空源漏的半导体结构，其特征在于，所述凸起结构为多层结构。
4.如权利要求1所述的具有悬空源漏的半导体结构，其特征在于，所述悬空薄层通过对所述多个凸起结构退火形成，所述退火温度为800-1350度，且在退火时气氛中含有氢气。
5.如权利要求1所述的具有悬空源漏的半导体结构，其特征在于，所述绝缘材料为SixNy、SiO2或SiOxNy中的至少一种。
6.如权利要求1所述的具有悬空源漏的半导体结构，其特征在于，所述绝缘材料包括：
第一绝缘材料；以及
位于所述第一绝缘材料及所述凸起结构之间，以及所述第一绝缘材料及所述衬底之间的第二绝缘材料。
7.如权利要求6所述的具有悬空源漏的半导体结构，其特征在于，所述第一绝缘材料为SixNy或SiOxNy，所述第二绝缘材料为SiO2。
8.如权利要求7所述的具有悬空源漏的半导体结构，其特征在于，在所述第一绝缘材料中掺杂C。
9.如权利要求1所述的具有悬空源漏的半导体结构，其特征在于，还包括：
形成在所述栅堆叠两侧的一层或多层侧墙。
10.一种具有悬空源漏的半导体结构的形成方法，其特征在于，包括以下步骤：
提供衬底；
在所述衬底之上形成多个凸起结构，所述每两个凸起结构之间具有一定间隙，所述间隙小于50nm；
在所述每两个凸起结构之间填充绝缘材料；
在所述每两个凸起结构之间及所述绝缘材料之上形成悬空薄层，且所述悬空薄层与所述两个凸起结构顶部相连；
在所述凸起结构之上形成栅堆叠；和
对所述栅堆叠两侧的悬空薄层进行掺杂以使所述凸起结构形成为沟道，所述凸起结构两侧的悬空薄层形成为源极和漏极。
11.如权利要求10所述的具有悬空源漏的半导体结构的形成方法，其特征在于，所述凸起结构从所述凸起结构的中部向顶部逐渐增大以使两个凸起结构顶部之间的间隙小于所述两个凸起结构中部之间的间隙。
12.如权利要求10所述的具有悬空源漏的半导体结构的形成方法，其特征在于，所述悬空薄层通过对所述多个凸起结构退火形成，所述退火温度为800-1350度，且在退火时气氛中含有氢气。
13.如权利要求10所述的具有悬空源漏的半导体结构的形成方法，其特征在于，还包括：
去除位于隔离区域中的悬空薄层以形成隔离结构。
14.如权利要求10所述的具有悬空源漏的半导体结构的形成方法，其特征在于，还包括：
在所述栅堆叠两侧形成一层或多层侧墙。
15.如权利要求10所述的具有悬空源漏的半导体结构的形成方法，其特征在于，所述绝缘材料为SixNy、SiO2或SiOxNy中的至少一种。
16.如权利要求10所述的具有悬空源漏的半导体结构的形成方法，其特征在于，所述在每两个凸起结构之间填充绝缘材料进一步包括：
对所述凸起结构的两侧及所述衬底的露出部分进行氧化以产生SiO2层；和
在所述每两个凸起结构之间及所述SiO2层之上外延SixNy或SiOxNy。
17.如权利要求16所述的具有悬空源漏的半导体结构的形成方法，其特征在于，还包括：
在所述SixNy或SiOxNy之中掺杂C。
18.如权利要求10所述的具有悬空源漏的半导体结构的形成方法，其特征在于，所述悬空薄层通过外延形成。
19.如权利要求10所述的具有悬空源漏的半导体结构的形成方法，其特征在于，所述在衬底之上形成多个凸起结构进一步包括：
在所述衬底之上形成第一半导体材料层；
向所述第一半导体材料层之中注入Si或Ge离子以在所述第一半导体材料层之中形成离子注入层；和
对所述第一半导体材料层进行选择性刻蚀以形成所述多个凸起结构。
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