CN102201014A - Multi-channel data collection unit - Google Patents
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Abstract
The invention relates to a multi-channel data collection unit, belonging to the technical field of data collection in testing and measurement. The collection unit consists of a plurality of collection channels, a testing channel and a collection unit control module, wherein each collection channel comprises a conditioning circuit which consists of a conventional filter circuit and a voltage protective circuit, an electric switch and a delta sigma analog to digital converter; the testing channel is formed by a delta sigma digital to analog converter; the collection unit control module is realized on the basis of a programmable logic controller; the plurality of collection channels are connected with the collection unit control module; the input end of the delta sigma digital to analog converter is connected with the output end of the collection unit control module; and the output end of the delta sigma digital to analog converter is connected with each electric switch and each delta sigma analog to digital converter of the collection channel respectively. By the multi-channel data collection unit, high dynamic range, low input nose, low harmonic distortion, low crosstalk and high common mode rejection ratio can be realized, and the requirement of low power consumption and low cost can be fulfilled.
Description
Technical field
The invention belongs to the data acquisition technology field in the thermometrically, be particularly related to and realize high dynamic range, low input noise, low harmonics distortion, low crosstalking and high cmrr, can satisfy data acquisition unit and collecting method that power consumption reaches the low requirement of cost less again.
Background technology
Data acquisition unit is based on indispensable parts in the test macro of computer technology, and its performance index directly influence the performance of test macro.In thermometrically, there are the performance index of a big class data signal collecting unit to have relatively high expectations, mainly comprise low crosstalk etc. between high dynamic range, low input noise, low harmonics distortion, high cmrr and the hyperchannel.Simultaneously,, also require low-power consumption, guarantee that the power supply of band has the sufficiently long working time at random if at the scene in the thermometrically system of Shi Yonging.For example, the data acquisition during petroleum prospecting, mineral mining, geologic prospect and biomedical signals measuring are used often requires the long period continuous working.Wherein, when utilizing seismic method to carry out petroleum prospecting, to the microvolt level, and the detection of microvolt level signal can obtain the deeper information of layer to the dynamic range of data acquisition unit input signal from volt level, and is more meaningful.Simultaneously, because the needs of stratigraphic analysis, the expectation collecting unit is the smaller the better to the harmonic distortion of input signal.Moreover, because the ground line loop has caused common mode voltage, also require collecting unit to have very strong inhibition ability; For multichannel collecting, require more that each interchannel crosstalking can not be too big in the collecting unit.Usually, modern petroleum prospecting data acquisition unit requires dynamic range greater than 120dB, and equivalent input noise is less than 5uV, and harmonic distortion is less than-106dB, and interchannel is crosstalked less than 100dB.In fact, require highlyer in medical science, as in the brain wave detection system, the input signal of data acquisition unit is little of microvolt even sub-micro volt level, and requires the little and common-mode rejection ratio height of harmonic distortion, only in this way could guarantee the detection of faint abnormal signal.
At present, the commercial data acquisition unit technology based on Δ ∑ modulation analog/digital signal conversion principle can realize high dynamic range and low input noise.Yet these data acquisition units are the ubiquity difficulty aspect realization low harmonics distortion and the low crosstalk performance of passage.At petroleum exploration field a kind of data acquisition plan is arranged, adopt the earthquake data acquisition nest plate of U.S. CirrusLogic company to realize above-mentioned data acquisition index, its principle as shown in Figure 1.This scheme is the data acquisition that core realizes 4 passages with a cover earthquake data acquisition nest plate usually, and a cover nest plate is made up of 4 prime amplifier CS3301A, 2 Δ ∑ modulator CS5372A, 1 digital filter CS5376A and 1 Δ ∑ digital to analog converter CS4373A.Each data acquisition channel is made up of 1 modulate circuit, 1 electronic switch, 1 prime amplifier, 1/2 Δ ∑ modulator and 1/4 digital filter, i.e. 2 shared Δ ∑ modulators of acquisition channel, 4 shared 1 digital filters of acquisition channel.This scheme produces test digital bit stream TBS (TBS, Test Bit Stream) by digital filter CS5376A, sends into Δ ∑ digital to analog converter CS4373A and produces high-precision test signal, can carry out self check to data acquisition channel and sensor.The collecting unit control module of this scheme realizes data acquisition and self check by the control to digital filter CS5376A, can adopt hardware such as general microprocessing unit such as MCU, DSP or FPGA to realize.
Owing to the earthquake data acquisition nest plate is the similar high dynamic range of petroleum prospecting, low input noise, low harmonics distortion, low crosstalk and the data acquisition application demand of high cmrr is developed specially, therefore, it has guaranteed the realization of above-mentioned these performance index on the one hand from the chip index, control function commonly used such as integrated earthquake nest plate data acquisition and self check in digital filter CS5376A on the other hand requires fairly simple based on the hardware design and the software programming of the data acquisition unit control module of this nest plate.But also just because this is a special chipset, and it is produced specially by U.S. CirrusLogic company, monopoly of sale therefore cost an arm and a leg, and this nest plate power consumption is bigger, and is not suitable for open-air long-term the use.
Summary of the invention
The objective of the invention is to deficiency and shortcoming at above-mentioned prior art, a kind of multi-channel data acquisition unit is provided, both can realize high dynamic range, low input noise, low harmonics distortion, low crosstalking and high cmrr, and can satisfy low-power consumption and requirement cheaply again.
The present invention proposes a kind of multi-channel data acquisition unit, it is characterized in that, this collecting unit is made up of a plurality of acquisition channels, a test channel and a collecting unit control module; Each acquisition channel comprises modulate circuit, electronic switch and the Δ ∑ analog to digital converter of being made up of conventional filtering circuit and voltage protection circuit, test channel is made of a Δ ∑ digital to analog converter, and the collecting unit control module realizes based on programmable logic controller (PLC) (FPGA) chip; A plurality of sensor signals to be tested link to each other with an acquisition channel respectively, and described a plurality of acquisition channels link to each other with the collecting unit control module; The input end of Δ ∑ digital to analog converter links to each other with the output terminal of collecting unit control module, and the output terminal of Δ ∑ digital to analog converter links to each other with each Δ ∑ analog to digital converter with each electronic switch of acquisition channel respectively; Wherein:
Acquisition channel is used for the sensor signal to be tested of gathering is nursed one's health and changed, and acquired signal and test signal is switched;
Test channel is used to receive the digital bit stream of collecting unit control module, and will change the input end that good analog test signal is delivered to electronic switch and Δ ∑ analog to digital converter ADS1282 respectively;
The collecting unit control module is used to receive the signal that acquisition channel is sent here, and assigns test instruction to acquisition channel; Assign digital bit stream to test channel, an instruction that the reception host computer is sent and a data storage that collects also send host computer to.
Characteristics of the present invention and beneficial effect:
Compared with prior art, technical advantage of the present invention is high-performance, low-power consumption and low cost.High-performance of the present invention is to reach channel distortion and is lower than-116dB, and the passage noise is lower than 1.6 μ V, and the channels crosstalk rejection ratio is greater than 122dB, and common-mode rejection ratio is greater than 110dB.Low-power consumption of the present invention is that the power consumption of collecting unit (not comprising cell controller) when four-way is gathered simultaneously only is 221mW.Low cost of the present invention is to have avoided to adopt expensive exclusive data to gather nest plate.
Description of drawings
Fig. 1 is existing four-way data acquisition unit theory diagram based on the earthquake data acquisition nest plate;
Fig. 2 is the structural principle block diagram of multi-channel data acquisition of the present invention unit;
Fig. 3 is the structural drawing of collecting unit control module of the present invention;
Fig. 4 is the connection layout that FPGA internal module of the present invention is communicated by letter with polylith ADS1282 and implemented;
Fig. 5 is the TBS maker structural drawing of FPGA of the present invention inside;
Fig. 6 is multi-channel data acquisition work principle figure of the present invention;
Fig. 7 is the process flow diagram of collecting unit control program of the present invention.
Embodiment
Embodiment to multi-channel data acquisition of the present invention unit is illustrated below in conjunction with accompanying drawing.
A kind of multi-channel data acquisition unit that the present invention proposes is characterized in that this collecting unit is made up of a plurality of acquisition channels, a test channel and a collecting unit control module; Each acquisition channel comprises modulate circuit, electronic switch and the Δ ∑ analog to digital converter of being made up of conventional filtering circuit and voltage protection circuit, test channel is made of a Δ ∑ digital to analog converter, and the collecting unit control module realizes based on programmable logic controller (PLC) (FPGA) chip; A plurality of sensor signals to be tested link to each other with an acquisition channel respectively, and described a plurality of acquisition channels link to each other with the collecting unit control module; The input end of Δ ∑ digital to analog converter links to each other with the output terminal of collecting unit control module, and the output terminal of Δ ∑ digital to analog converter links to each other with each Δ ∑ analog to digital converter with each electronic switch of acquisition channel respectively; Wherein:
Acquisition channel is used for the sensor signal to be tested of gathering is nursed one's health and changed, and acquired signal and test signal is switched;
Test channel is used to receive the digital bit stream of collecting unit control module, and will change the input end that good analog test signal is delivered to electronic switch and Δ ∑ analog to digital converter ADS1282 respectively;
The collecting unit control module is used to receive the signal that acquisition channel is sent here, and assigns test instruction to acquisition channel; Assign digital bit stream to test channel, an instruction that the reception host computer is sent and a data storage that collects also send host computer to.
The example structure of multi-channel data acquisition of the present invention unit as shown in Figure 2, present embodiment is made up of a plurality of acquisition channels, a test channel and a collecting unit control module.Each acquisition channel comprises modulate circuit, electronic switch (as ADG733) and the Δ ∑ analog to digital converter ADS1282 (American TI Company production) that is made up of conventional filtering circuit and voltage protection circuit in the present embodiment, test channel is made up of a Δ ∑ digital to analog converter CS4373A (production of U.S. Cirrus Logic company), and the collecting unit control module realizes based on programmable logic controller (PLC) fpga chip (as the EP2C35F484-C8 chip in the Cyclone II of the altera corp series); Wherein, a plurality of sensor signals to be tested link to each other with an acquisition channel respectively, and described a plurality of acquisition channels link to each other with the collecting unit control module; The input end of Δ ∑ digital to analog converter links to each other with the output terminal of collecting unit control module, and the output terminal of Δ ∑ digital to analog converter links to each other with each Δ ∑ analog to digital converter with each electronic switch of acquisition channel respectively.
The example structure of collecting unit control module of the present invention is made up of FPGA internal module and external structure as shown in Figure 3.External structure comprises outside FLASH storer (as the Am29LV28M chip), SRAM storer (as the K6F1616R6C chip) and RS232 interface (as the MAX3237 chip).The FPGA internal module is for illustrating in the thick black surround among the figure, it is the main body of collecting unit control module, the FPGA internal module of present embodiment comprises the control module and TBS maker module three parts of system's operation module, acquisition channel and test channel, and the composition and the functional description of each several part are as follows:
System's operation module comprises soft-core processor, timer internal (Interval Time), system banner device (System ID), JTAGUART interface, UART interface, general Flash interface and SRAM controller.Above-mentioned each parts all link to each other with the Avalon bus; Timer internal provides system timing information; The system banner device provides the identification information of this system; JTAG UART interface is the serial communication interface between host computer and collecting unit control module, is used for the debugging of collecting unit control module; To be the collecting unit control module connect the serial communication interface of host computer by the RS232 interface to the UART interface, is used to support the transmission of data and instruction between collecting unit control module and the host computer; General Flash interface connects outside FLASH storer, and supports to be stored in the storage of the collecting unit control program in the outside FLASH storer and to read; The SRAM controller connects and supports the SRAM storer to carry out the storage of data.
The control module of acquisition channel and test channel comprises parallel I/O kernel sdrdy monitor, parallel I/O kernel PAD controller, several SPI interfaces and a MUX.Parallel I/O kernel sdrdy monitor, parallel I/O kernel PAD controller all link to each other with the Avalon bus with several SPI interfaces; Whether parallel I/O kernel sdrdy monitor is used to monitor collection result and can be read; Parallel I/O kernel PAD controller is realized functions such as restarting of polylith ADS1282 and synchronously, the output mode of CS4373A and the setting of output gain, the on off state of electronic switch ADG733 are provided with; The quantity of SPI interface is identical with the quantity of acquisition channel, it is the corresponding SPI interface of each acquisition channel, 1 SPI interface wherein is configured to holotype, reads the data that ADS1282 sends here, and is connected writing of all acquisition channels instructions of realization with MUX; Remaining SPI interface is configured to from pattern, reads the data that corresponding ADS1282 sends here; MUX is between the ADS1282 of holotype SPI interface and all acquisition channels, by the gating of MUX realization different acquisition passage ADS1282, can be accepted the instruction of holotype SPI interface and carry out the setting of acquisition parameter by the ADS1282 of gating.The SPI interface can realize that the data parallel of each acquisition channel ADS1282 reads and instruct non-being written in parallel in the control module of acquisition channel and test channel.Data parallel reads can realize that multi-channel data reads the most fast, thereby guarantees higher sampling rate.Instruct the non-acquisition parameter that can guarantee that different path settings is different that is written in parallel to, guarantee the dirigibility of data acquisition parameters.
Figure 4 shows that the FPGA internal module of present embodiment and the polylith ADS1282 communication link map interlinking of acquisition channel.Wherein, the SPI_1_SCLK pin of the holotype SPI interface of FPGA internal module and the SCLK pin of every ADS1282 link to each other, give each piece ADS1282 by SPI_1_SCLK pin output data collecting work clock, the Dout pin of each piece ADS1282 is connected to the MISO pin (SPI_1_MISO) or the corresponding MOSI pin (SPI_2_MOSI from the SPI interface of corresponding holotype SPI interface respectively, SPI_n_MOSI), the Din pin of each piece ADS1282 is connected respectively to the respective pin (Mux_Din_1 of MUX, Mux_Din_2, Mux_Din_n).Simultaneously, the DRDY/ pin of any 1 ADS1282 is connected to the sdrdy pin of parallel I/O kernel sdrdy monitor.
Fig. 5 is TBS maker (TBS Generator) structural drawing of the FPGA inside of present embodiment, and it is made up of the waveform data memory, digital interpolative wave filter and the Δ ∑ modulator that connect successively.TBS maker module is used to produce data bit stream, gives CS4373A and produces high-precision test signal.Wherein, what store in the waveform data memory is the waveform of one-period, improves sampling rate behind this waveform process digital interpolative wave filter, again through producing digital bit stream TBS after the Δ ∑ modulators modulate.
The collecting method that the present invention adopts above-mentioned multi-channel data acquisition unit comprises that data acquisition, self check and collecting unit control three parts as shown in Figure 6; Be described below respectively:
Data acquisition: from the signal elder generation process signal condition of survey sensor; be filtering and voltage protection; then by entering Δ ∑ modulus conversion chip ADS1282 after the channel allocation; amplify therein, after the analog to digital conversion, filtering by 31 high-accuracy digital signals of its SPI interface output; enter the collecting unit control module, carry out data storage or upload by it.
Self check: if the collecting unit control module receives the order that the collecting unit self check is carried out in the host computer requirement, then it produces data test signal bit stream TBS by its inner TBS maker immediately, give digital to analog converter, produce high-precision test signal by it by digital-to-analog conversion, the test signal that produces is carried out channel allocation according to the difference of test event, give acquisition channel or sensor respectively, then carry out the step of aforesaid data acquisition.
Collecting unit control: the control of collecting unit realizes by the control flow that is stored in the outside FLASH storer.
Figure 7 shows that collecting unit control flow chart of the present invention.This control flow may further comprise the steps:
The collecting unit control module receives and resolves the instruction of host computer, and whether " self check " is judged.Self check if desired, then collecting unit control module elder generation output data bit stream and drive the CS4373A chip produces high-precision analog test signal by it, and delivers to the inlet end of electronic switch or ADS1282.No matter be data acquisition or self check, all need according to different test needs, the state of electronic switch is set earlier and sets acquisition parameter by the collecting unit control module, restart data acquisition and carry out analog to digital conversion, finish data storage and upload by the collecting unit control module at last.
Claims (5)
1. a multi-channel data acquisition unit is characterized in that, this collecting unit is made up of a plurality of acquisition channels, a test channel and a collecting unit control module; Each acquisition channel comprises modulate circuit, electronic switch and the Δ ∑ analog to digital converter of being made up of conventional filtering circuit and voltage protection circuit, test channel is made of a Δ ∑ digital to analog converter, and the collecting unit control module realizes based on the programmable logic controller (PLC) fpga chip; A plurality of sensor signals to be tested link to each other with an acquisition channel respectively, and described a plurality of acquisition channels link to each other with the collecting unit control module; The input end of Δ ∑ digital to analog converter links to each other with the output terminal of collecting unit control module, and the output terminal of Δ ∑ digital to analog converter links to each other with each Δ ∑ analog to digital converter with each electronic switch of acquisition channel respectively; Wherein:
Acquisition channel is used for the sensor signal to be tested of gathering is nursed one's health and changed, and acquired signal and test signal is switched;
Test channel is used to receive the digital bit stream of collecting unit control module, and will change the input end that good analog test signal is delivered to electronic switch and Δ ∑ analog to digital converter ADS1282 respectively;
The collecting unit control module is used to receive the signal that acquisition channel is sent here, and assigns test instruction to acquisition channel; Assign digital bit stream to test channel, an instruction that the reception host computer is sent and a data storage that collects also send host computer to.
2. collecting unit as claimed in claim 1 is characterized in that, described collecting unit control module is made up of FPGA internal module and external circuit; External circuit comprises outside FLASH storer, SRAM storer and RS232 interface; The FPGA internal module comprises the control module and TBS maker module three parts of system's operation module, acquisition channel and test channel.
3. collecting unit as claimed in claim 2 is characterized in that, described system's operation module comprises soft-core processor, timer internal, system banner device, JTAGUART interface, UART interface, general Flash interface and SRAM controller; Described each parts all link to each other with the Avalon bus; Timer internal provides system timing information; The system banner device provides the identification information of this system; JTAG UART interface is the serial communication interface between host computer and collecting unit control module, is used for the debugging of collecting unit control module; To be the collecting unit control module connect the serial communication interface of host computer by the RS232 interface to the UART interface, is used to support the transmission of data and instruction between collecting unit control module and the host computer; General Flash interface connects outside FLASH storer, and supports to be stored in the storage of the collecting unit control program in the outside FLASH storer and to read; The SRAM controller connects and supports the SRAM storer to carry out the storage of data.
4. collecting unit as claimed in claim 2, it is characterized in that the control module of institute's acquisition channel and test channel comprises parallel I/O kernel sdrdy monitor, parallel I/O kernel PAD controller, several SPI interfaces and a MUX; Parallel I/O kernel sdrdy monitor, parallel I/O kernel PAD controller all link to each other with the Avalon bus with several SPI interfaces; Whether parallel I/O kernel sdrdy monitor is used to monitor collection result and can be read; Parallel I/O kernel PAD controller is realized restarting of polylith ADS1282 and synchronous, the output mode of CS4373A and the setting of output gain, and the on off state of electronic switch ADG733 is provided with function; The quantity of SPI interface is identical with the quantity of acquisition channel, it is the corresponding SPI interface of each acquisition channel, 1 SPI interface wherein is configured to holotype, reads the data that ADS1282 sends here, and is connected writing of all acquisition channels instructions of realization with MUX; Remaining SPI interface is configured to from pattern, reads the data that corresponding ADS1282 sends here; MUX is between the ADS1282 of holotype SPI interface and all acquisition channels, by the gating of MUX realization different acquisition passage ADS1282, can be accepted the instruction of holotype SPI interface and carry out the setting of acquisition parameter by the ADS1282 of gating; The SPI interface can realize that the data parallel of each acquisition channel ADS1282 reads and instruct non-being written in parallel in the control module of acquisition channel and test channel; Data parallel reads can realize that multi-channel data reads the most fast, thereby guarantees higher sampling rate; Instruct the non-acquisition parameter that can guarantee that different path settings is different that is written in parallel to, guarantee the dirigibility of data acquisition parameters.
5. collecting unit as claimed in claim 2 is characterized in that, the TBS maker of described FPGA inside is made up of the waveform data memory, digital interpolative wave filter and the Δ ∑ modulator that connect successively; TBS maker module is used to produce data bit stream, gives CS4373A and produces high-precision test signal; Wherein, what store in the waveform data memory is the waveform of one-period, improves sampling rate behind this waveform process digital interpolative wave filter, again through producing digital bit stream TBS after the Δ ∑ modulators modulate.
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