CN102194683A - 电极部的构造 - Google Patents
电极部的构造 Download PDFInfo
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- CN102194683A CN102194683A CN2010105720284A CN201010572028A CN102194683A CN 102194683 A CN102194683 A CN 102194683A CN 2010105720284 A CN2010105720284 A CN 2010105720284A CN 201010572028 A CN201010572028 A CN 201010572028A CN 102194683 A CN102194683 A CN 102194683A
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Abstract
一种电极部的构造,在贯通配线的端部形成电极,防止该电极部的断线。在基板(12)上设置贯通上下的贯通孔(16),在贯通孔(16)内设置贯通电极(15)。贯通电极(15)从基板(12)的上表面曲面状地突出。用绝缘膜(18)覆盖基板(12)的上表面,与贯通电极(15)对应在绝缘膜(18)上开设接触孔(19)。接触孔(19)的开口直径比贯通电极(15)的截面直径小,贯通电极(15)的上表面的周围通过接触孔(19)覆盖。接触孔(19)开口缘的自贯通电极(15)的基板上表面的突出长度Dp不比绝缘膜(18)的膜厚Ddiel大。将自贯通电极(15)的顶部的基板上表面的突出长度(最大突出长度)设定为Dtsv时,该突出长度Dtsv被调整为:0≤Dtsv≤Ddiel+Dp,其中Dp>0。
Description
技术领域
本发明涉及电极部的构造,具体而言,涉及在贯通配线的端部形成有电极的电极部的构造。
背景技术
图1及图2是表示在贯通配线的端部形成电极的电极构造物的一例的概略立体图及其剖面图。该电极构造物11A在基板12的上表面形成电极13,在基板12的下表面形成电极14,通过贯通基板12内的贯通电极15电连接位于基板12的上表面和下表面的电极13和电极14。
即,如图1及图2所示,从基板12的上表面朝向下表面开设有贯通孔16,贯通孔16的内周面用孔内绝缘膜17覆盖,经由孔内绝缘膜17在贯通孔16内形成贯通电极15。基板12的上表面及下表面用绝缘膜18覆盖,在上表面的绝缘膜18上面形成电极13,电极13通过绝缘膜18的接触孔19与贯通电极15的上端面连接。在下表面的绝缘膜18下面设置有电极14,电极14的上表面与贯通电极15的下表面连接。另外,下表面的电极14通过焊锡等接合材料28与配线基板20的图形配线27接合。
例如图3及图4所示,该电极构造物11A将电极13与其它部件接合。图3表示使用焊锡等接合材料21将电极13与电路基板22的配线焊盘接合的情况。另外,图4表示用贯通电极15连接形成于基板12的两面的电极13和电极14的电极构造物11A、用贯通电极15连接形成于基板12的两面的电极13彼此之间的电极构造物11B,用接合材21接合电极构造物11A的电极13和电极构造物11B的电极13而将电极构造物彼此之间层叠。
这种电极构造物11A或11B的电极部用如图5(a)~(d)所示的工序制作。首先,如图5(a)所示,在由Si等构成的基板12上形成凹部16a后,在凹部16a的内表面形成由SiO2等构成的孔内绝缘膜17,再在用孔内绝缘膜17覆盖的凹部16a内填充导电材料,在凹部16a内形成贯通电极15。
通过研磨该基板12使贯通电极15露出,并研磨上端面,如图5(b)所示,与基板12的上表面相对应,将贯通电极15的上端面整修为平滑。接着,如图5(c)所示,在基板12的上表面通过SiO2等形成绝缘膜18,与贯通电极15的上端面相对应,在绝缘膜18上开设接触孔19。之后,在贯通电极15及绝缘膜18的上表面通过蒸镀及溅射等堆积电极金属,如图5(d)所示,将电极金属层进行构图而形成电极13,并且,将电极13和贯通电极15进行连接。
图5(b)的工序原理上为平滑地加工贯通电极15的端面(露出面)。但实际上,将贯通电极15的端面和基板12的表面之间的高度差设定得小到亚微等级以下,将贯通电极15的端面与基板12的表面相对应进行平坦加工在技术上变得困难。
因此,通过对从基板12突出的贯通电极15进行化学机械研磨而使其与基板12的表面接近平坦时,利用进行化学机械研磨时的化学作用和机械作用的配合,如图6(a)所示,在贯通电极15和孔内绝缘膜17之间产生槽26,或者如图7(a)所示,贯通电极15的端面凹陷成盆状。另外,因为研磨加工时的面内偏差,所以,当在某区域使贯通电极15的端面接近平坦时,在其它区域如图6(a)所示在贯通电极15和孔内绝缘膜17之间产生槽26,或图7(a)所示,贯通电极15的端面凹陷成盆状。
这样,如图6(a)所示在贯通孔16内在贯通电极15的周围产生槽26时,如图6(b)所示,在除去贯通电极15的区域形成绝缘膜18,在贯通电极15的端面及其周围在绝缘膜18上形成电极13时,由于槽26的存在而在电极13上产生断线。这样,在形成于贯通电极15的端面的电极13a(13)和形成于绝缘膜18上的电极13b(13)之间产生断线时,即使周围的电极13b与例如图3所示的电路基板22连接,贯通电极15和电路基板22也不能电连接,产生劣质品。
另外,如图7(a)所示,在贯通电极15的端面凹陷成盆状时,如图7(b)所示,在除去贯通电极15的区域形成绝缘膜18,在贯通电极15的端面及其周围在绝缘膜18上形成电极13时,在形成于贯通电极15的端面的电极13a(13)和形成于绝缘膜18上的电极13b(13)之间产生断线。
另外,在贯通电极15的端面凹陷时,使用焊锡等接合材料21使电极13与电路基板22等接合时,如图8所示,根据位置不同,接合材21的厚度大幅变化。因此,因温度变化等发生热伸缩时,在接合材料21及电路基板22、电极13等之间产生的内部应力变大,在该接合部分容易发生剥离及裂纹,在电极13和电路基板22之间有可能断线。
(关于专利文献1)
作为将贯通电极的端面与基板的表面平滑地加工的技术,公开在专利文献1中。专利文献1记载的加工方法如图9所示,在粘贴于平板23上的研磨布24上涂敷含有平均磨粒直径为80nm以下的胶质的二氧化硅的研磨剂25,且在其上使基板12和贯通电极15的研磨面接触,将研磨压力控制为规定的压力,由此,以使贯通电极端面和基板表面的高度差d成为-0.5μm≤d≤0.5μm的方式进行抛光加工。
但是,为防止断线,只要将贯通电极端面和基板表面的高度差d设定为-0.5μm≤d<0.5μm即可这样的记载于专利文献1的条件只不过只是经验原则,尤其是,在基板12的上表面形成绝缘膜18,从其上形成电极13的情况下,根据绝缘膜18的膜厚和电极13的厚度的关系,即使贯通电极端面和基板表面的高度差满足-0.5μm≤d≤0.5μm的条件的情况下,有时也会发生断线,另外,即使没有满足该条件的情况下有时也不会发生断线。
另外,在用专利文献1的方法中追求基板和贯通电极的平坦性的情况下,要根据贯通电极的材料、形状、寸法等变化研磨条件,反复试验决定最适合的研磨条件,存在需要花费时间和成本,电极构造物的成本增高,并且开发时间也变长的问题。
专利文献1:(日本)特开平7-283536号公报
发明内容
本发明是鉴于上述技术课题而提出的,其目的在于,提供一种在贯通配线的端部形成电极的电极部的构造,其能够可靠地防止该电极部的断线。
本发明提供的电极部的构造,在设置于基板的贯通孔内形成贯通电极,对所述基板的表面进行磨削、研磨,通过绝缘膜覆盖所述基板的表面,并且,与所述贯通电极的端面对应,在所述绝缘膜上开口形成有接触孔,在所述绝缘膜上形成电极,而且,通过所述接触孔在所述贯通电极的端面形成所述电极,其特征在于,以使所述贯通电极的端面不从所述基板的表面凹陷的方式而形成,在所述接触孔的开口缘从所述基板的表面测定的所述贯通电极的突出长度Dp为所述绝缘膜的膜厚Ddiel以下,且将从所述基板的表面测定的所述贯通电极的顶部的突出长度设定为Dtsv时,以满足以下条件的方式形成所述贯通电极的端面,即、0≤Dtsv≤Ddiel+Dp,其中,Dp>0。
根据本发明的电极部的构造,能够将使绝缘膜的膜厚设定为一定时的电极表面的最大高度差设定为最小,提高电极表面的平坦度。因此,在将具备该触点部的电极构造物安装于另外的电路基板等或层叠多个电极构造物彼此时,在使用焊锡等接合材料将电极与电路基板的电极焊盘接合、或将电极彼此接合时,能够使接合材料的厚度均匀化。因此,能够缓和伴随温度变化等的热膨胀/收缩导致的在接合材料及电极等上产生的内部应力,防止接合材料及电极的剥离及裂纹,能够防止电极接合部的断线。
本发明的电极部构造的某实施方式的特征在于,所述电极的厚度比所述绝缘膜的膜厚厚。根据该实施方式,不会因绝缘膜的高度差部分等而导致电极断线。
本发明的电极部构造的其它实施方式的特征在于,所述贯通电极的端面由弯曲面构成。在这样的实施方式中,能够将贯通电极的端面制成弯曲面,因此,通过基板研磨能够平整贯通电极,提高量产性。
本发明的电极部构造的再其它实施方式的特征在于,使所述贯通电极的端面整体从所述绝缘膜的所述开口露出。根据这样的实施方式,能够使贯通电极的端面和电极的连接面积最大,能够减小贯通电极和电极的连接部分的阻抗。
本发明的电极部构造的再其它实施方式的特征在于,所述绝缘膜的所述开口形成于比所述贯通电极的外周更靠内侧。根据这样的实施方式,能够防止由于开设接触孔时的偏差导致的基板从绝缘膜露出,能够缓和对接触孔开口时的要求精度。另外,根据该实施方式,能够将贯通电极的突出长度Dtsv的上限值设定为大的值,因此,能够扩大贯通电极的突出长度Dtsv的允许范围或调整范围,电极部的设计及制造变得容易。
另外,用于解决本发明的所述课题的技术手段具有适当组装以上说明的构成要素的特征,本发明根据构成要素的组合能够进行多种变化。
附图说明
图1是表示电极构造物的一例的概略立体图;
图2是沿图1的X-X线的剖面图;
图3是表示将图2所示的电极构造物的电极与电路基板接合的形态的剖面图;
图4是表示在基板的两面具有电极的电极构造物的两电极中的一个电极和图2所示的电极构造物的电极接合的形态的剖面图;
图5(a)~(d)是表示在电极构造物上制作电极部的工序的概略剖面图;
图6(a)及(b)是表示通过研磨在贯通电极的端面的周围产生槽的情况下的概略剖面图;
图7(a)及(b)是表示通过研磨而贯通电极的端面凹陷成盆状的情况下的概略剖面图;
图8是用于说明如图7(b)所示贯通电极的端面凹陷情况下的不良情况的剖面图;
图9是用于说明专利文献1公示的贯通电极的研磨方法的概略剖面图;
图10是表示本发明的电极部的构造的概略剖面图;
图11是用于说明本发明的电极部的制造工序的剖面图;
图12是用于说明与图11的工序连续的工序的剖面图;
图13(a)是用于说明与图12的工序连续的工序的剖面图,图13(b)是用于说明与图13(a)的工序连续的工序的剖面图;
图14是用于说明与图13(b)的工序连续的工序的剖面图;
图15是表示电极部的一形态(形态I)的图;
图16是表示电极部的其它形态(形态II)的图;
图17是表示电极部的另外的其它形态(形态III)的图;
图18是表示电极部的另外的其它形态(形态IV)的图;
图19是表示电极部的另外的其它形态(形态V)的图;
图20是表示电极部的另外的其它形态(形态VI)的图;
图21是用于说明接触孔的边缘倾斜的情况下的接触孔的边缘的贯通电极的突出长度Dp的定义的图;
图22是表示电极的表面的最大高度差Rmax和贯通电极的突出长度Dtsv的关系的图;
图23(a)及(b)是用于说明本发明的作用效果的概略剖面图。
附图标记说明:
11A、13B、电极构造物
12、基板
13、电极
13a、电极
13b、电极
14、电极
15、贯通电极
16、贯通孔
16a、凹部
17、孔内绝缘膜
18、绝缘膜
19、接触孔
20、配线基板
21、接合材料
22、电路基板
具体实施方式
下表面,参照附图说明本发明的具体实施方式。但是,本发明并不限于以下的实施方式,在不脱离本发明的宗旨的范围内可进行各种设计变更。
图10是表示本发明的电极部的构造的放大剖面图。该电极部的构造用于例如图1及图2所示的电极构造物11A及图4所示的电极构造物11B等。在本发明的电极部的构造中,如图10所示,从由Si等构成的基板12的上表面朝向下表面开设有贯通孔16,贯通孔16的内周面用由SiO2等构成的孔内绝缘膜17覆盖,在贯通孔16内经由孔内绝缘膜17通过镀敷Cu、AuSn等导电材料等进行填充,形成贯通电极15。贯通配线也包括在基板12和贯通电极15之间层状地形成孔内绝缘膜17和Ti及氮化膜等势垒金属膜的结构。贯通电极15的端面(上表面)以与基板12的上表面成为同一面内的方式平坦地形成,或从基板12的上表面突出成为大致平滑的曲面。基板12的上表面用由SiO2等构成的绝缘膜18覆盖,在绝缘膜18上与贯通孔16对应开设有接触孔19。接触孔19的开口直径与形成于贯通孔16的内周面的孔内绝缘膜17的内径相等,接触孔19的内周缘也可以与孔内绝缘膜17的内周面一致。或者也可以使接触孔19的开口直径比形成于贯通孔16的内周面的孔内绝缘膜17的内径小,在贯通电极15的端面重合绝缘膜18(接触孔19的边缘的部分)。在向接触孔19内露出的贯通电极15的端面及其周围的绝缘膜18上形成有由Au及Pt等电极金属构成的电极13,电极13通过接触孔19与贯通电极15的端面连接。另外,设置于贯通电极15的另一端面(下表面)的电极14如图1及图2所示的电极构造物11A那样与图形配线27连接,或与图4所示的电极构造物11B那样相同,与电极13接合。
另外,在本发明的电极部的构造中,在将以基板12的上表面为基准的贯通电极15的端面顶部的突出长度(最大突出量)设定为Dtsv、将以基板12的上表面为基准的接触孔19的边缘的贯通电极15的突出长度设定为Dp、将绝缘膜18的膜厚设定为Ddiel时,满足DP≤Ddiel(条件1)且满足0≤Dtsv≤Ddiel+Dp(条件2)。
其中,在Dtsv≥0、Dp≥0、Ddiel>0,且突出长度Dtsv及Dp在贯通电极15的端面从基板12的上表面突出的情况下为Dtsv>0、Dp>0,在贯通电极15的端面从基板12的上表面凹陷的情况下,Dtsv<0、Dp<0。
另外,上述条件1及2也可以用0≤Dtsv≤Ddiel+Dp≤2×Ddiel的条件式表示。
另外,电极13的厚度Del比绝缘膜18的膜厚Ddiel厚。即,成为Del>Ddiel(条件3)。
只要以满足上述条件1且条件2和条件3的方式研磨贯通电极15或形成绝缘膜18及电极13,则就能够防止电极13及其周围的断线。
(制造方法)
图11、图12、图13(a)、(b)及图14是表示电极构造物11A及其电极部的制造工序的概略剖面图。在图11的工序中,在用绝缘膜18覆盖了下表面的基板12(例如SOI基板)的下表面形成盲孔状的凹部16a,用由SiO2等构成的孔内绝缘膜17覆盖凹部16a的内表面。另外,对用孔内绝缘膜17覆盖的凹部16a内实施镀敷等,向凹部16a内填充由Cu、AuSn等导电材料构成的贯通电极15,另外,在凹部16a的正下方设置电极14,使电极14的上表面与贯通电极15的下表面接合。电极14通过焊锡等接合材料28与配线基板20的图形配线27接合。
接着,如图12所示,研磨基板12的上表面,直到从基板12的上表面露出贯通电极15。该研磨工序只要研磨效率高,则加工精度也可以低,因此,研磨的基板12的上表面也可以是粗糙的状态。其结果是,凹部16a将基板12上下贯通而成为贯通孔16,贯通电极15的上端面与基板12的上表面大致成为一个面。
另外,通过化学机械研磨(CMP:Chemical Mechanical Polishing)多次研磨基板12的上表面。在化学的机械的研磨中,在机械的研磨的基础上也进行化学研磨,因此,通过使用适用于特定材料的研磨剂能够选择性地仅研磨由多种材料构成的研磨对象物中的特定材料。因此,在第一阶段的化学机械研磨中相对于基板12使用研磨性能高的浆体(研磨剂)将基板12的上表面研磨成平坦。在第一阶段的化学机械研磨中,基板12的研磨量比贯通电极15的研磨量大,因此,在研磨的基板12的上表面,如图13(a)所示,在基板12的上表面,贯通电极15的上端部未被研磨而残留,从基板12的上表面突出。随后,在第二阶段的化学机械研磨中,相对于贯通电极15使用研磨性能高的浆体(研磨剂)微细地研磨基板12的上表面。在第二阶段的化学机械研磨中,研磨从基板12的上表面突出的贯通电极15,因此,如图13(b)所示,从基板12的上表面突出的贯通电极15的端面加工成平滑的曲面状。在该第二阶段的化学机械研磨中,以贯通电极15的端面不从基板12的上表面凹陷的方式进行管理,贯通电极15的端面以从基板12的上表面稍微突出的状态结束研磨工序。
之后,如图14所示,在基板12的上表面形成SiO2等绝缘膜18,在贯通电极15的端面在绝缘膜18上开设有接触孔19。接触孔19也可以以其开口直径与孔内绝缘膜17的内径相等的方式开设,但是,理想是将接触孔19的孔径设定为比孔内绝缘膜17的内径(贯通电极15的水平断面的直径)小,贯通电极15的端面用绝缘膜18覆盖一部分。将接触孔19的开口直径设定为与孔内绝缘膜17的内径相等时,可能会由于接触孔19的开口直径的偏差及错位而使基板12的上表面从绝缘膜18露出。接着,通过蒸镀及溅射等在绝缘膜18上层叠Au及Pt等电极金属,另外,在将电极金属层进行构图并在贯通电极15上形成电极13,并且,通过接触孔19使电极13与贯通电极15连接。由此,结束电极部的制造工序。
(本发明的原理)
下面,说明上述条件1~3的根据。图15~图20分别表示尺寸形状不同的几个贯通电极15的情况。以下,对这些电极部(形态I~VI)分别评价电极13的表面的最大高度差Rmax。在图15~图20中使用的记号如图10所示,分别表示如下。
Dtsv:以基板12的上表面为基准的贯通电极15的端面顶部的突出量(最大突出长度)
Dp:以基板12的上表面为基准的接触孔19的缘部的贯通电极15的突出长度
Ddiel:绝缘膜18的膜厚
Del:电极13的厚度
Rmax:电极13的表面的最大高度差
另外,所谓电极13的表面的最大高度差Rmax,意思是电极13的表面内最高部位的高度(从基板12的上表面垂直测定的高度)Hmax和电极13的表面内最低部位的高度(从基板12的上表面垂直测定的高度)Hmin的差Hmax-Hmin。Dtsv、Dp、Hmax、Hmin都是从基板12的上表面测定且在基板12的外侧(在图上,基板上表面的上侧)用正数(+)量表示,在基板12的内侧(在图上为基板上表面的下侧)用负数(一)量表示。另外,在贯通电极15的研磨工序中,贯通电极15的端面为弯曲面,因此,成为
|Dp|≤|Dtsv|这样的关系。
首先,对图15所示的形态I的情况进行考虑。在图15的形态I中表示的是贯通电极15的上端面比与基板12的上表面一致或从基板12的上表面突出,且贯通电极15的突出长度Dtsv为绝缘膜18的膜厚Ddiel以下的情况。即,图15的形态I为满足0≤Dtsv≤Ddiel(条件4)这样的条件的情况。
在这样的形态I的情况下,从图15可知,
Hmax=Dp+Ddiel+Del
Hmin=Dp+Del
因此,电极13的表面的最大高度差Rmax用如下的数学式1表示。
Rmax=Hmax-Hmin
=(Dp+Ddiel+Del)-(Dp+Del)
=Ddiel (数学式1)
因此,在形态I的情况下,电极13的表面的最大高度差Rmax与贯通电极15的突出长度Dtsv没有关系,成为一定值(Ddiel)。
在图16的形态II中,贯通电极15的突出长度Dtsv为绝缘膜18的膜厚Ddiel以上,且贯通电极15的突出长度Dtsv为在接触孔19的缘部从基板12的上表面测定的绝缘膜18的顶部的高度(Dp+Ddiel)以下的情况。另外,图16的形态II为接触孔19的缘部的贯通电极15的突出长度Dp为绝缘膜18的膜厚Ddiel以下的情况。即,图16的形态II为满足Ddiel≤Dtsv≤Ddiel+Dp且Dp≤Ddiel(条件5)这样的条件的情况。
在这种形态II的情况下,从图16可知,接触孔19的缘部的电极13的高度差成为最大高度差Rmax,因此,成为如下的数学式2。
Rmax=(Dp+Ddiel+Del)-(Dp+Del)
=Ddiel (数学式2)
因此,形态II的情况也是电极13的表面的最大高度差Rmax与贯通电极15的突出长度Dtsv没有关系,成为一定值(Ddiel)。
在图17的形态III中,与图16的情况相同,贯通电极15的突出长度Dtsv为绝缘膜18的膜厚Ddiel以上,且贯通电极15的突出长度Dtsv为在接触孔19的缘部从基板12的上表面测定的绝缘膜18的顶部的高度(Dp+Ddiel)以下的情况。但是,形态III为接触孔19的缘部的贯通电极15的突出长度Dp比绝缘膜18的膜厚Ddiel大的情况。即,图17的形态III为满足Ddiel≤Dtsv≤Ddiel+Dp且Dp>Ddiel(条件6)这样的条件的情况。如图17的形态III与图16的情况相比,产生在接触孔19的缘部的贯通电极15的突出长度Dp大时绝缘膜18的膜厚Ddiel薄的情况。
在这样的形态III的情况下,从图17可知,在接触孔19的缘部从基板12的上表面测定的电极13的顶部的高度成为最大高度Hmax,从基板12的上表面测定的电极13的平坦区域的表面高度成为最小高度Hmin,因此,
Hmax=Dp+Ddiel+Del
Hmin=Ddiel+Del
因此,电极13的表面的最大高度差为
Rmax=Hmax-Hmin
=(Dp+Ddiel+Del)-(Ddiel+Del)
=Dp (数学式3)
因此,在形态III的情况下,在贯通电极15的突出长度Dtsv变大时,伴随于此突出长度Dp也变大,因此,最大高度差Rmax也增大。
在图18的形态IV中,贯通电极15的突出长度Dtsv为在接触孔19的缘部从基板12的上表面测定的绝缘膜18的顶部的高度(Dp+Ddiel)以上的情况。另外,图18的形态IV的情况为接触孔19的缘部的贯通电极15的突出长度Dp为绝缘膜18的膜厚Ddiel以下的情况。即,图18的形态IV为满足Ddiel+Dp≤Dtsv且Dp≤Ddiel(条件7)这样的条件的情况。
在这样的形态IV的情况下,从图18可知,在贯通电极15的中央从基板12的上表面测定的电极13的表面的高成为最大高度Hmax,在接触孔19的缘部从基板12的上表面测定的电极13的谷部的高度成为最小高度Hmin,因此,
Hmax=Dtsv+Del
Hmin=Dp+Del
因此,电极13的表面的最大高度差为
Rmax=(Dtsv+Del)-(Dp+Del)
=Dtsv-Dp (数学式4)
因此,在该情况下,贯通电极15的突出长度Dtsv变大时,伴随于此Dtsv-Dp也变大,因此,最大高度差Rmax也增大。
在图19的形态V中,贯通电极15的突出长度Dtsv为在接触孔19的缘部从基板12的上表面测定的绝缘膜18的顶部的高度(Dp+Ddiel)以上的情况。但是,在图19的形态V的情况下,为接触孔19的缘部的贯通电极15的突出长度Dp比绝缘膜18的膜厚Ddiel大的情况。即,图19的形态V为满足Ddiel+Dp≤Dtsv且Dp>Ddiel(条件8)这样的条件的情况。
在这样的形态V的情况下,从图19可知,在贯通电极15的中央从基板12的上表面测定的电极13的表面的高度(Dtsv+Del)成为最大高度Hmax,从基板12的上表面测定的电极13的平坦区域的表面高度(Ddiel+Del)成为最小高度Hmin,因此,
Rmax=(Dtsv+Del)-(Ddiel+Del)
=Dtsv-Ddiel (数学式5)
因此,在形态V的情况下,贯通电极15的突出长度Dtsv变大时,伴随于此最大高度差Rmax也增大。
图20的形态VI表示贯通电极15的端面凹陷,且比基板12的上表面更凹陷的情况。即,图20的形态VI满足Dtsv<0(条件9)这样条件的情况。
在这样的形态VI的情况下,从图20可知,电极13的表面的最大高度差Rmax用如下的数学式6表示。
Rmax=(Ddiel+Del)-(Del+Dtsv)
=Ddiel-Dtsv (数学式6)
因此,电极13的表面的最大高度差Rmax随着贯通电极15的凹陷(-Dtsv)的变大而增大。
另外,在绝缘膜18上开口形成接触孔19时,实际上接触孔19的缘部(内周面)不垂直,如图21所示,有时接触孔19以在开口侧(图15~图20的上方)扩大的方式使缘部倾斜。在该情况下,接触孔19的缘部在水平方向扩展,因此,决定以基板12的上表面为基准的接触孔19的缘部的贯通电极15的突出长度Dp的位置不确定。
一般而言,无论是以接触孔19的缘部的下端决定Dp,还是以上端决定Dp,Dp的值都不太变化,但是,在有问题的情况下,只要以图21表示的方式决定即可。在用于电极13的表面的最大高度Hmax的计算的情况下,只要将接触孔19的缘部的最高位置即位于接触孔19的缘部的上端正下方的贯通电极15的突出长度Dp(out)作为Dp的值使用即可。另外,在使用于电极13的表面的最小高度Hmin的计算的情况下,只要将接触孔19的缘部的最低位置即位于接触孔19的缘部的下端正下方的贯通电极15的突出长度Dp(in)作为Dp的值使用即可。
对上述形态I~VI整理求取的电极13的表面的最大高度差Rmax的值和其条件后,得出如下表1。
表1
另外,将该最大高度差Rmax作为贯通电极15的突出长度Dtsv的函数用图表表示时,成为图22。在图22中,纵轴表示电极13的表面的最大高度差Rmax,横轴表示贯通电极15的突出长度Dtsv。另外,图22所示的图表的各线段I~VI与各个形态I~VI对应。
图23(a)及(b)都表示将电极13通过焊锡等接合材料21与电路基板22接合的状态。在此,图23(a)表示电极13的表面的最大高度差Rmax比较小的电极部,图23(b)表示电极13的表面的最大高度差Rmax比较大的情况。在如图23(b)所示最大高度差Rmax比较大的情况下,通过接合材料21将电极13与电路基板22接合时,接合材料21的厚度偏差(不均匀度)变大。因此,在由于温度变化等而在接合材料21上产生热伸缩时,在接合材料21和电路基板22或接合材料21和电极13之间产生的内部应力变大,并且不均匀,在该接合部分发生剥离及裂纹,在接合部分容易断线。尤其是,在贯通电极15的端面凹陷的情况下(形态VI),接合材料21的厚度偏差变得非常大(也参照图8),在接合材料21上容易产生剥离及裂纹。与之相对,如图23(a)所示,在最大高度差Rmax比较小的情况下,通过接合材料21将电极13与电路基板22接合时的接合材料21的厚度偏差变小。因此,在因温度变化等而产生热伸缩时,在接合材料21和电路基板22及接合材料21和电极13之间产生的内部应力变小,在该接合部分难以产生剥离及裂纹,能够防止接合部分的断线。因此,在将电极13与另外的部件的电极焊盘等接合并将电极构造物安装于电路基板等的情况下,或将电极13彼此之间接合并层叠电极构造物彼此之间的情况下,为了抑制其接合部分的剥离及裂纹的发生,使接合部分的机械强度及电气特性稳定,理想的是电极13的表面的最大高度差Rmax尽可能地小,使电极13平坦化,使安装高度均匀化。
在此,看图22后可知,在线段I及II(形态1及II)的情况下,最大高度差Rmax为最小值Ddiel。即,可知只要将贯通电极15的突出长度Dtsv设定为0≤Dtsv≤Ddiel(上述条件4)或Dp≤Ddiel且Ddiel≤Dtsv≤Ddiel+Dp(上述条件5),贯通电极15的端面的最大高度差Rmax就能够为最小。
对于贯通电极15而言,考虑为Dp≤Dtsv即可,因此,在满足条件4的情况下,当然成为DP(≤Dtsv)≤Ddiel。因此,上述条件4或5也可以表现为
DP≤Ddiel且0≤Dtsv≤Ddiel+Dp。
这是上述条件1、2。
因此,如果预先决定绝缘膜18的膜厚Ddiel,则以突出长度Dtsv成为满足上述条件4或5的范围内的方式研磨加工贯通电极15,或如果在绝缘膜18上开设接触孔19,则能使最大高度差Rmax为最小且能够使电极13形成大致平坦,通过接合材料21接合电极13时就难以产生剥离及裂纹,也难以引起断线。
另外,接触孔19的开口直径也可以与贯通电极15的外径相等。但是,在接触孔19的开口直径与贯通电极15的外径相等的情况下,如上所述,因接触孔19的开口位置的错位及孔径的偏差,基板12可能从绝缘膜18露出。与之相对,将接触孔19的开口直径设定为比贯通电极15的外径小,如果绝缘膜18覆盖贯通电极15的端面的周围,则不会因接触孔19开口时的偏差而使基板12露出,能够缓和开口接触孔19时的要求精度。另外,在贯通电极15突出的情况下,减小接触孔19的开口直径时,Dp(>0)逐渐变大,因此,贯通电极15的突出长度Dtsv的上限值(Ddiel+Dp)变大,贯通电极15的突出长度Dtsv的允许范围变大,电极部的设计及制造变得容易。
另外,在贯通电极15的研磨工序中,也可以以贯通电极15的端面成为平坦的方式进行研磨。但是,要将贯通电极15的端面研磨为平坦时,有可能如图6及图7所示在周围产生槽26,或者化学机械研磨时的化学作用过强而使贯通电极15的端面凹陷。因此,贯通电极15的研磨加工时的突出长度Dtsv的目标值更优选为0.1μm≤Dtsv。
Claims (5)
1.一种电极部的构造,在设置于基板的贯通孔内形成贯通电极,对所述基板的表面进行磨削、研磨,通过绝缘膜覆盖所述基板的表面,并且,与所述贯通电极的端面对应,在所述绝缘膜上开口形成有接触孔,在所述绝缘膜上形成电极,而且,通过所述接触孔在所述贯通电极的端面形成所述电极,其特征在于,
以使所述贯通电极的端面不从所述基板的表面凹陷的方式而形成,
在所述接触孔的开口缘从所述基板的表面测定的所述贯通电极的突出长度Dp为所述绝缘膜的膜厚Ddiel以下,且将从所述基板的表面测定的所述贯通电极的顶部的突出长度设定为Dtsv时,以满足以下条件的方式形成所述贯通电极的端面,即、
0≤Dtsv≤Ddiel+Dp,
其中,Dp>0。
2.如权利要求1所述的电极部构造,其特征在于,所述电极的厚度比所述绝缘膜的膜厚厚。
3.如权利要求1所述的电极部构造,其特征在于,所述贯通电极的端面由弯曲面构成。
4.如权利要求1所述的电极部构造,其特征在于,使所述贯通电极的端面整体从所述绝缘膜的所述开口露出。
5.如权利要求1所述的电极部构造,其特征在于,所述绝缘膜的所述开口形成于比所述贯通电极的外周更靠内侧。
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US20130342211A1 (en) * | 2012-06-26 | 2013-12-26 | Schlumberger Technology Corporation | Impedance Spectroscopy Measurement Device And Methods For Analysis Of Live Reservoir Fluids And Assessment Of In-Situ Corrosion Of Multiple Alloys |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005174991A (ja) * | 2003-12-08 | 2005-06-30 | Seiko Epson Corp | 半導体装置の製造方法、半導体装置、回路基板および電子機器 |
US20050161587A1 (en) * | 2004-01-27 | 2005-07-28 | Casio Computer Co., Ltd. | Optical sensor module with semiconductor device for drive |
JP2006049557A (ja) * | 2004-08-04 | 2006-02-16 | Seiko Epson Corp | 半導体装置 |
US20070018313A1 (en) * | 2005-07-21 | 2007-01-25 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure and method of manufacturing the same |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4571542A (en) * | 1982-06-30 | 1986-02-18 | Japan Synthetic Rubber Co., Ltd. | Method and unit for inspecting printed wiring boards |
EP0647090B1 (en) * | 1993-09-03 | 1999-06-23 | Kabushiki Kaisha Toshiba | Printed wiring board and a method of manufacturing such printed wiring boards |
JPH07283536A (ja) | 1994-04-15 | 1995-10-27 | Hitachi Ltd | 厚膜/薄膜混成基板とその研磨加工方法 |
JP2785768B2 (ja) * | 1995-09-14 | 1998-08-13 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2000077622A (ja) * | 1998-08-31 | 2000-03-14 | Texas Instr Inc <Ti> | 半導体記憶装置及びその製造方法 |
JP3160583B2 (ja) * | 1999-01-27 | 2001-04-25 | 日本特殊陶業株式会社 | 樹脂製基板 |
JP2003329444A (ja) * | 2002-03-07 | 2003-11-19 | Alps Electric Co Ltd | 静電容量式センサ |
US7024947B2 (en) * | 2002-03-07 | 2006-04-11 | Alps Electric Co., Ltd. | Detection device including circuit component |
JP3627932B2 (ja) * | 2003-06-04 | 2005-03-09 | 日立金属株式会社 | 貫通電極つき基板の製造方法 |
JP4365750B2 (ja) * | 2004-08-20 | 2009-11-18 | ローム株式会社 | 半導体チップの製造方法、および半導体装置の製造方法 |
JP4400408B2 (ja) * | 2004-10-12 | 2010-01-20 | パナソニック電工株式会社 | 貫通電極の形成方法 |
JP4409455B2 (ja) * | 2005-01-31 | 2010-02-03 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP2006237520A (ja) * | 2005-02-28 | 2006-09-07 | Nec Tokin Corp | 薄型多端子コンデンサおよびその製造方法 |
KR101248738B1 (ko) * | 2005-12-07 | 2013-03-28 | 엔지케이 스파크 플러그 캄파니 리미티드 | 유전체 구조체, 유전체 구조체의 제조방법 및 유전체구조체를 포함한 배선기판 |
KR100826452B1 (ko) * | 2006-12-18 | 2008-04-29 | 삼성전기주식회사 | 광학 부품 및 그 제조방법 |
US8284557B2 (en) * | 2007-10-18 | 2012-10-09 | Kyocera Corporation | Circuit board, mounting structure, and method for manufacturing circuit board |
JP5237607B2 (ja) * | 2007-10-25 | 2013-07-17 | 新光電気工業株式会社 | 基板の製造方法 |
-
2010
- 2010-03-10 JP JP2010052642A patent/JP2011187771A/ja active Pending
- 2010-10-27 EP EP10189078A patent/EP2365742A1/en not_active Withdrawn
- 2010-10-28 KR KR1020100105740A patent/KR101174578B1/ko not_active IP Right Cessation
- 2010-12-03 CN CN2010105720284A patent/CN102194683A/zh active Pending
- 2010-12-23 US US12/977,888 patent/US20110220406A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005174991A (ja) * | 2003-12-08 | 2005-06-30 | Seiko Epson Corp | 半導体装置の製造方法、半導体装置、回路基板および電子機器 |
US20050161587A1 (en) * | 2004-01-27 | 2005-07-28 | Casio Computer Co., Ltd. | Optical sensor module with semiconductor device for drive |
JP2006049557A (ja) * | 2004-08-04 | 2006-02-16 | Seiko Epson Corp | 半導体装置 |
US20070018313A1 (en) * | 2005-07-21 | 2007-01-25 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure and method of manufacturing the same |
Also Published As
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KR20110102124A (ko) | 2011-09-16 |
EP2365742A1 (en) | 2011-09-14 |
JP2011187771A (ja) | 2011-09-22 |
KR101174578B1 (ko) | 2012-08-16 |
US20110220406A1 (en) | 2011-09-15 |
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