CN102184876A - Method for measuring wafer positioning error during laser processing - Google Patents
Method for measuring wafer positioning error during laser processing Download PDFInfo
- Publication number
- CN102184876A CN102184876A CN 201110056309 CN201110056309A CN102184876A CN 102184876 A CN102184876 A CN 102184876A CN 201110056309 CN201110056309 CN 201110056309 CN 201110056309 A CN201110056309 A CN 201110056309A CN 102184876 A CN102184876 A CN 102184876A
- Authority
- CN
- China
- Prior art keywords
- wafer
- micrometering
- laser processing
- test
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000012545 processing Methods 0.000 title claims abstract description 29
- 238000012360 testing method Methods 0.000 claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000002019 doping agent Substances 0.000 claims description 12
- 238000005259 measurement Methods 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 6
- 230000004304 visual acuity Effects 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- 230000001419 dependent effect Effects 0.000 claims description 2
- 238000001310 location test Methods 0.000 claims description 2
- 238000012937 correction Methods 0.000 abstract description 3
- 238000010561 standard procedure Methods 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005224 laser annealing Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000009897 systematic effect Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Images
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a method for measuring a wafer positioning error during laser processing, belonging to the technical field of semiconductor manufacturing. The method comprises the following steps of: designing a semiconductor manufacturing layout; making a plate after the layout is designed; and entering a manufacturing flow for manufacturing micro testing structures. Except a low-concentration doped region, other parts all adopts processes same as the conventional process, then a corresponding manufacturing process which comprises a laser processing step for manufacturing micro testing structures distributed at different positions is adopted, and the electric characteristics of the micro testing structures are tested lastly. The wafer positioning error during laser processing can be judged according to different measuring results of each testing structure and the known position distribution situation, so that a testing basis is provided for error correction. The method is simple, convenient and practical, can be implemented without large-sized complex instrument equipment or extra accurate operation, can be combined with laser processing equipment, and is a standard method for periodically detecting and calibrating the equipment performance.
Description
Technical field
The invention belongs to the semiconductor fabrication scope, the method for measurement of wafer position error in particularly a kind of laser processing.
Background technology
Laser has been widely used in the processed of semi-conducting material, comprises laser annealing, the laser assisted film deposition, and the laser recrystallization growth of material waits diversified concrete application.
Because laser beam has very strong coherence, light beam is pack often, and being not easy to scatter becomes the larger area light beam; On the other hand, the wafer size is very big again, so laser beam is for the effect of backing material, under technical conditions at present, can not carry out in the mode of the laser light field that covers whole wafer, and can only be that carry out partly one of a part.Usually the mode that adopts is that laser beam is done scanning with respect to material surface, stepping, perhaps the stepping translation that adds scanning is moved, realize line by line, perhaps by processed.
No matter be line by line,, always exist between the row connection problem between the field by the field.For bad linking, exist two class problems, the one, joining place two row or two have small overlapping, although then the overlapping region is very little, but consider that the size of electronic devices and components is in littler magnitude in the integrated circuit, be affected, had much by the component number of excess process, this will directly influence the integrated circuit crudy.Another kind of problem is between two row, has small space between two, similarly, is subjected to this to influence the electronic devices and components quantity that is not lasered processing and has a lot, and crudy can not guarantee equally.
At the problem in the above practice, a kind of effective treatment measures are the scribing road width that make full use of between the chip.Specifically, order scanning or stepping, strictly carry out left or to the right along the transversely arranged direction of chip array, the last lower edge of light beam bundle spot, light intensity is inhomogeneous herein, processing effect can't guarantee, this part at edge makes it fall within the scribing road between chip array, thus, can avoid between the scan line the bad problem of linking between the field of step-scan.After scanning or stepping to the wafer edge, laser beam line down (moving delegation perhaps), and turn around in the opposite direction, continue its horizontal scanning or stepping and advance by the field.For the latter, if adopt one one place processed of step-by-step system, then restraint spot about two edges, also all drop in the chip scribing road.
When requiring scanning, perhaps step-scan is along the direction of chip array, and the edge of sewwp beam spot naturally, has also just produced the problem of wafer aligning when falling within scribing the road in.Because scribing road width is tens microns magnitude, the requirement that this moment, wafer was aimed at not is very high, and alignment tolerance and the same magnitude of scribing road width are at tens microns.For instance, alignment precision can relax to 10 microns or wideer.
Further, a lot of laser processings all require to carry out the processing that preheats of substrate, and for the wafer that this generic request substrate heats up, its alignment procedures can be subjected to the certain high temperature influence.Can arrive 400～500 degree when temperature is higher, so higher.Under high-temperature condition, the thermal expansion of wafer will be difficult to ignore, and higher in addition temperature, and the infrared radiation background of wafer full wafer under the higher temperature all may be to the optical system for alignment of wafer, and registration signal is handled and brought very big harmful effect.So a kind of wafer is preferably aimed at strategy, employing is separated with process cavity, independently align structures carries out the aligning of wafer, and the wafer behind the aligning is sent on the process cavity sheet platform by the precision optical machinery hand again, carries out complementary heat temperature raising there again.Because the aligning of separate type does not relate to process high-temperature, alignment result can be protected.
Adopt the aligning of separate type, the sheet platform that is used to form actions such as laser beam scanning in alignment tab platform and the technology is two cover self-contained units, so this each self-defining direct of travel of two sheet platforms also has origin of coordinates position etc. all to be not quite similar, and can produce systematic error.For instance, the alignment tab platform according to self X (about) direction removes to adjust the rotation amount of wafer, makes that the horizontal scribing road of the chip array on the wafer is strict consistent with alignment tab platform directions X.When the precision optical machinery hand is placed into wafer on the processing scanning sheet platform, because the X of scanning sheet platform (about) direct of travel, although in the ordinary course of things can with alignment tab platform directions X differ one very little, but the angle of absolute being, thereby the direction in length and breadth of wafer array, not with processing sheet platform defined X (about), Y (front and back) direction is parallel fully.The biography sheet process of precision optical machinery hand also can be introduced extra alternate position spike in addition.The systematic error that these all can cause wafer to aim at.This systematic error, each machine is not quite similar with the precision difference of complete machine assembling, debugging.
Poor for calibrating position, before implementing, calibration needs the size of clear and definite alignment error value, and to this, the present invention proposes the method that the wafer position error measures in a kind of laser processing.By using the micrometering examination structure and the technical process of particular design, electrology characteristic that can throughput micrometer test structure is grasped the position error amount of wafer alignment system.
Summary of the invention
The purpose of this invention is to provide the method for measurement of wafer position error in a kind of laser processing, it is characterized in that, comprise the steps:
1) at first determine to select for use the kind of test structure, the domain that designing semiconductor is made partners two micrometerings examination structures earlier, then with a series of micrometering examination structure to forming one group; In same group, different micrometering examination structure is right, and the spacing between two micrometering examination structures wherein is to increase progressively or successively decrease by certain direction; The opsition dependent coordinate is put, and constitutes arranging of some series; Certain size has like this determined the resolving power that position error is measured, adopt the micrometering examination structural group of some groups of different resolving powers, the direction of spacing is both along laterally also longitudinally, just constitute comparatively complete test domain, adopted the IC manufacturing technology on the substrate of laser beam scanning area, to make a series of small test structure;
2) by the method for photoetching location test structure is formed upper and lower pairing by per two, and according to the distance between two test structures from big to small according to arrange diverse location place on the wafer of a series of coordinate position;
3) test structure on the wafer is carried out the scanning processed of laser beam;
4) the produced micrometering of test tries the electrology characteristic of structure, judges which micrometering examination structure fabrication success, and which making is unsuccessful; If there is not position error in wafer, then the processing of laser beam is to cover whole test structure, thereby produces intact micrometering examination structure; If but there is position error, then the processing of laser beam may only relate to a part of test structure, thereby the micrometering of producing examination structure is an imperfection, unsuccessful;
5), make the value size of wafer position error in the laser processing by the measurement of step 4) to the series of tests structure electrology characteristic of arranging by coordinate position.
Described micrometering examination structure is resistance or transistor.
Described micrometering examination structure is that the metal pressure-welding block district links to each other with the high-concentration dopant district by contact hole, the high-concentration dopant district links to each other with the low concentration doping district again, wherein high-concentration dopant district and low concentration doping district are homotypes, promptly all are that the N type mixes, and perhaps all are that the P type mixes.
The invention has the beneficial effects as follows, the domain and the related manufacturing process of special micrometering examination structure have been designed, by producing the micrometering examination structure that distributes by diverse location, and the test that micrometering is tried the electrology characteristic of structure, can measure the error of the location of wafer in the laser processing, thereby provide the test foundation for error correction.This method is simple and practical, need not can carry out by means of large complicated instrument and equipment and extra accurate operation, can combine with laser process equipment, becomes the standardized means of the regular spot check calibration of latter's equipment performance.
Description of drawings
Fig. 1, Fig. 2 is for measuring the electric resistance structure of wafer position error and the schematic diagram of distributing position thereof in the laser processing.
Among Fig. 1 and Fig. 2,
1. be metal and press welding block zone; 2. be the high-concentration dopant district; 3. be the low concentration doping district; 4. be the contact hole between metal and the doped region; 5. be micro-structural resistance at diverse location; 6. be the laser beam scanning area; 7. be the upper edge of low doped region; 8. be the lower edge of low doped region.
Embodiment
The method for measurement that the purpose of this invention is to provide wafer position error in a kind of laser processing.According to the hereinbefore described technical thought of application, concrete implementation method illustrates as follows.
It is as follows to illustrate a kind of specific embodiment.
At first after definite micrometering examination structure, the domain that designing semiconductor is made is finished in layout design, and after the plate-making, enters manufacturing process, makes these micrometering examination structures.The all same common process of the technology of other parts except that the low concentration doping district, especially, the high-concentration dopant district adopts ion to inject the mode that adds annealing and forms, and conventional boiler tube high annealing is adopted in annealing.For the low concentration doping district, adopt ion to inject the mode that adds laser annealing and make.
Resistance micrometering examination structure shown in Figure 1 is arranged by mode shown in Figure 2 on wafer, thereby can be produced the small resistance test structure of a series of diverse locations.
Right by each resistance that Fig. 2 mode is arranged, when beam of laser light beam 6 from left to right scans, when doped regions 3 is annealed, in the location of wafer when error free with respect to the scanning of laser beam, the situation of scanning beam and each resistance, promptly as shown in Figure 2.If wafer is positioned with error, so, can occur in a pair of resistance, last resistance per square is annealed, and the following resistance per square situation (perhaps conversely) that can not be annealed, thereby the measurement by resistance value, can understand the situation of position error, specifically carry out following explanation.
Get micrometering examination structure shown in Figure 1,, put these test structures in different positions according to Fig. 2 mode, thus integrant test domain.Test structure can be a resistance device, also can be transistor or other device.Under the situation of resistance device (as shown in Figure 1), adopt resistance shown in Figure 1 to try structure as micrometering.Metal pressure-welding block district 1 among Fig. 1 links to each other with high-concentration dopant district 2 by contact hole 4, and high-concentration dopant district 2 links to each other with low concentration doping district 3 again, and high-concentration dopant district and low concentration doping district are homotypes here, for example all is that the N type mixes, and perhaps all is that the P type mixes.Playing a decisive role for resistance value, will be the doping content in low concentration doping district 3, and this region doping impurity situation about activating under the laser annealing effect.Except that low concentration doping district 3, every other zone, its manufacture craft is all with general integrated circuit manufacturing, especially, high-concentration dopant district 2 can adopt the mode of the high annealing of ion injection and routine to form, ion injects concrete zone of implementing, and is determined by photoetching.In whole test structure, low concentration doping district 3 is only arranged, adopt first photoetching to determine the zone that ion injects, carry out the doping that ion injects low concentration then, again after, the annealing of adopting the method for laser annealing to carry out impurity activates.In Fig. 2, resistance is represented with rectangle frame 5 one by one.It is some right that these resistance from left to right are divided into again, and a pair of resistance has comprised resistance of top and resistance of below.The a pair of resistance of high order end, the distance between its upper and lower two resistance for example is taken as 10 millimeters, from this resistance is begun to the right, each dwindles successively to the spacing between the resistance, for example the every pair of resistance spacing all than last to dwindling 0.5 millimeter, produce how right resistance successively.Resistance centering, the spacing between the resistance up and down, what get is to go up resistance per square doped regions upper edge 7 to the distance between the resistance per square doped regions lower edge 8 down.
Wherein mainly providing the part of resistance as micrometering examination structure is low concentration doping district 3, and other parts in the structure are in order to make resistance test to carry out smoothly.
Being 10 millimeters with laser linewidth is example, and it is right to put different resistance, each resistance centering, and the spacing of last resistance per square and following resistance per square, by 6,7,8,9,10,11,12,13,14 millimeters designs amount to 9 pairs of resistance.9 pairs of resistance like this can constitute one group, and its position resolution is 500 microns.If expect higher resolution, can the design centre value be 10 millimeters then, but by 1,10,100,500 microns to left increase progressively, to the right-hand right group of different resistance of successively decreasing.Whole test domain, the group right by several resistance constitutes, and the spacing that group and difference between the group only are internal upper and lower two resistance of resistance can provide different resolution by different change in size.Domain except that resistance to image pattern 2 such horizontal arranging, also comprise vertically arranging, to be used to measure wafer position error longitudinally.When the scope of laser beam processing is determined, because micrometering examination physical dimension is different series, perhaps disperses to put by different series, some test structures are in outside the machining area, perhaps critical position, so its electrical characteristics test value can reflect the situation of actual light beam processing.The test value of electrical characteristics is put with the different size of known micro-structural test structure or different position and to be contrasted, and can draw the gap situation between wafer coordinate system and the laser beam machining coordinate system, and this is a position error.Here, the wafer coordinate system can be determined jointly by the coordinate of each the micrometering examination structure graph on the known wafer sheet.
On wafer the somewhere laterally, longitudinally the alternate position spike, also can measure the alternate position spike at first place and the alternate position spike at the second place that is separated by far away, both can determine the rotation amount of wafer with respect to beam flying or stepping-scanning direction.Further, the electrical testing amount of the micrometering examination structure by the many places diverse location can draw to statistical the statistical conclusions of wafer position error.
Suppose that laser anneal device is making up and the assembling stage, through the Primary Location calibration, can guarantee positioning accuracy in 2 millimeters scopes, so, use the beam flying of the 10 mm wides one group of resistance of annealing right, by the right spacing of above-mentioned resistance is 6,7,8,9,10,11,12,13,14 millimeters, totally 9 resistance to the time, if 2 millimeters on the upper side of the positions of laser beam actual scanning, spacing is that a pair of resistance of 14 millimeters so, lower test resistance value can be annealed thereby present to resistance well on it, and higher test resistance value can not be annealed thereby present to resistance down; And another is that a pair of resistance of 6 millimeters to spacing, and its upper and lower resistance all is within the light beam beamwidth scope, thereby upper and lower resistance just can full annealing and all present lower resistance value; Other are several to resistance, and last resistance always can be dead annealed, and down resistance can't be annealed or can't full annealing and present different higher resistance value.By such one group of test value, can conclude that relative error between laser beam and the wafer is on the laser beam inclined to one side 2 millimeters.Situation inclined to one side 2 millimeters under the laser beam is similar.The right position error certainty of measurement of 9 resistance of this group is 500 microns.
More than describe and be summarized as two, one, install and the adjustment process by machinery, guarantee that original positioning accuracy is no more than 2 millimeters; Two, the resistance of diverse location that by resolving power is 500 microns is to characteristic test, and measurable range is compressed to 500 microns.If by certain correction and compensation, the practical position error is in littler magnitude, then can adopt resolving power higher, other resistance further measures group.The ultimate resolution of the inventive method only depends on the right spacing setting of being adopted of resistance.On the other hand, also can adopt transistor or other basic components and parts to try structure as micrometering, transistor or other device also are to put in different positions according to above-mentioned similar mode, location gap is by the certain size increments or the variation of successively decreasing, then, can obtain high-precision site error recognition capability equally by the measuring element characteristic.
In sum, the inventive method is simple and practical, need not can carry out by means of large complicated instrument and equipment and extra accurate operation, can combine with laser process equipment, becomes the standardized means of the regular spot check calibration of latter's equipment performance.This method is applicable to the location requirement of lower accuracy, is typically the magnitude of micron.The size or the putting position of micrometering examination structure depend on photoetching process, because the positioning accuracy of photoetching process is higher than micron dimension far away, therefore can ignore the error of the relevant coordinate data of micro-structural.
Claims (3)
1. the method for measurement of wafer position error in the laser processing is characterized in that, comprises the steps:
1) at first determine to select for use the kind of test structure, the domain that designing semiconductor is made partners two micrometerings examination structures earlier, then with a series of micrometering examination structure to forming one group; In same group, different micrometering examination structure is right, and the spacing between two micrometering examination structures wherein is to increase progressively or successively decrease by certain direction; The opsition dependent coordinate is put, and constitutes arranging of some series; Certain size has like this determined the resolving power that position error is measured, adopt the micrometering examination structural group of some groups of different resolving powers, the direction of spacing is both along laterally also longitudinally, just constitute comparatively complete test domain, adopted semiconductor fabrication on the substrate of laser beam scanning area, to make a series of small test structure;
2) by the method for photoetching location test structure is formed upper and lower pairing by per two, and according to the distance between two test structures from big to small according to arrange diverse location place on the wafer of a series of coordinate position;
3) test structure on the wafer is carried out the scanning processed of laser beam;
4) the produced micrometering of test tries the electrology characteristic of structure, judges which micrometering examination structure fabrication success, and which making is unsuccessful; If there is not position error in wafer, then the processing of laser beam is to cover whole test structure, thereby produces intact micrometering examination structure; If but there is position error, then the processing of laser beam may only relate to a part of test structure, thereby the micrometering of producing examination structure is an imperfection, unsuccessful;
5), make the value size of wafer position error in the laser processing by the measurement of step 4) to the series of tests structure electrology characteristic of arranging by coordinate position.
2. according to the method for measurement of wafer position error in the described laser processing of claim 1, it is characterized in that described micrometering examination structure is resistance or transistor.
3. according to the method for measurement of wafer position error in the described laser processing of claim 1, it is characterized in that, described micrometering examination structure is that the metal pressure-welding block district links to each other with the high-concentration dopant district by contact hole, the high-concentration dopant district links to each other with the low concentration doping district again, wherein high-concentration dopant district and low concentration doping district are homotypes, promptly all being that the N type mixes, perhaps all is that the P type mixes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110056309A CN102184876B (en) | 2011-03-09 | 2011-03-09 | Method for measuring wafer positioning error during laser processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110056309A CN102184876B (en) | 2011-03-09 | 2011-03-09 | Method for measuring wafer positioning error during laser processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102184876A true CN102184876A (en) | 2011-09-14 |
| CN102184876B CN102184876B (en) | 2012-09-05 |
Family
ID=44571030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110056309A Expired - Fee Related CN102184876B (en) | 2011-03-09 | 2011-03-09 | Method for measuring wafer positioning error during laser processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102184876B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376569A (en) * | 2011-10-14 | 2012-03-14 | 清华大学 | Manufacturing method of micrometering structure for position measurement in laser processing |
| CN102519413A (en) * | 2011-12-29 | 2012-06-27 | 清华大学 | Space-time transformation method for wafer film thickness measuring error compensation for wafer table |
| CN102564378A (en) * | 2011-12-29 | 2012-07-11 | 清华大学 | Error compensation method for measuring film thickness of wafer of wafer stage |
| CN112820714A (en) * | 2020-12-28 | 2021-05-18 | 中国电子科技集团公司第十三研究所 | Wafer-level capacitor standard sample and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004052586A1 (en) * | 2002-12-06 | 2004-06-24 | Hamamatsu Photonics K.K. | Device and method for laser processing |
| CN101611324A (en) * | 2005-10-18 | 2009-12-23 | Gsi集团公司 | Utilize the method and the device of optical reference |
-
2011
- 2011-03-09 CN CN201110056309A patent/CN102184876B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004052586A1 (en) * | 2002-12-06 | 2004-06-24 | Hamamatsu Photonics K.K. | Device and method for laser processing |
| CN101611324A (en) * | 2005-10-18 | 2009-12-23 | Gsi集团公司 | Utilize the method and the device of optical reference |
Non-Patent Citations (1)
| Title |
|---|
| 《微细加工技术》 20020930 严利人 Nikon光刻机对准机制和标记系统研究 全文 1-3 , 第3期 2 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376569A (en) * | 2011-10-14 | 2012-03-14 | 清华大学 | Manufacturing method of micrometering structure for position measurement in laser processing |
| CN102519413A (en) * | 2011-12-29 | 2012-06-27 | 清华大学 | Space-time transformation method for wafer film thickness measuring error compensation for wafer table |
| CN102564378A (en) * | 2011-12-29 | 2012-07-11 | 清华大学 | Error compensation method for measuring film thickness of wafer of wafer stage |
| CN102564378B (en) * | 2011-12-29 | 2014-04-23 | 清华大学 | Error compensation method for measuring film thickness of wafer of wafer stage |
| CN112820714A (en) * | 2020-12-28 | 2021-05-18 | 中国电子科技集团公司第十三研究所 | Wafer-level capacitor standard sample and preparation method thereof |
| CN112820714B (en) * | 2020-12-28 | 2022-12-13 | 中国电子科技集团公司第十三研究所 | Wafer-level capacitor standard sample and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102184876B (en) | 2012-09-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103354212B (en) | The method of measuring and calculating contact hole and polysilicon gate deviation of the alignment value | |
| KR100296646B1 (en) | Probe system and probe method | |
| CN102184876B (en) | Method for measuring wafer positioning error during laser processing | |
| CN103354211B (en) | The method of measuring and calculating contact hole and polysilicon gate deviation of the alignment value | |
| US10048603B2 (en) | Alignment method and alignment system thereof | |
| US9059037B2 (en) | Methods for overlay improvement through feed forward correction | |
| KR102234659B1 (en) | Scanning electron microscope device capable of measuring in-cell overlay offset using high energy electron beam and methods thereof | |
| CN104425302A (en) | Defect detection method and device of semiconductor device | |
| WO2016188212A1 (en) | Alignment method and system for manufacturing mask integration framework | |
| CN102623368A (en) | Wafer defect detection method | |
| KR20120049220A (en) | A mask health monitor using a faraday probe | |
| CN102280400B (en) | Wafer aligning method in laser beam processing | |
| CN102290362B (en) | Method for correcting positioning error of wafer during laser processing | |
| CN102466977B (en) | Mark structure used for measuring distortion of projection object lens and its method | |
| CN112713102B (en) | Pattern alignment detection method | |
| CN104465619B (en) | A kind of picture structure and its alignment precision measurement method of alignment precision measurement | |
| US7883909B2 (en) | Method to measure ion beam angle | |
| CN104977812A (en) | Exposure apparatus and method for manufacturing article | |
| CN105280538A (en) | IGBT back side manufacturing method capable of realizing refining photolithography of back side | |
| CN102799062A (en) | Mask, wafer and monitor method | |
| CN100405526C (en) | Ion implantation apparatus and method | |
| US9798228B2 (en) | Maximizing potential good die per wafer, PGDW | |
| JPH02260419A (en) | Irradiation with laser | |
| CN109509738B (en) | Method for manufacturing alignment mark on wafer and structure of alignment mark | |
| CN103972119A (en) | Testing device and method for measuring alignment deviation through testing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120905 Termination date: 20170309 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |