CN112820714A - Wafer-level capacitor standard sample and preparation method thereof - Google Patents
Wafer-level capacitor standard sample and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L28/40—Capacitors
- H01L28/60—Electrodes
Abstract
The invention discloses a wafer-level capacitor standard sample and a preparation method thereof, belonging to the technical field of semiconductor process monitoring equipment calibration. The wafer level capacitance standard sample wafer comprises: a wafer and a plurality of chip units manufactured on the wafer; the structure of the chip unit comprises: the circuit breaker comprises a plurality of groups of nominal capacitor series with different magnitudes and circuit breakers which are respectively in one-to-one correspondence with each group of nominal capacitor series, wherein the nominal capacitor series comprises a plurality of nominal capacitors which are arranged in an array by taking a nominal value as a center and taking a preset value as a step; the capacitance value range of the nominal capacitance series is as follows: 0.5pF to 100 pF. The wafer-level capacitor standard sample wafer is used for the integral calibration of the PCM equipment on-wafer capacitor parameters, fills the blank of the field of calibration of the PCM equipment in the corresponding range of the parameters in China, ensures the accuracy and the uniformity of high-frequency small-capacitor measurement data of the PCM equipment, and ensures the process stability and the product quality of a semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductor monitoring equipment calibration, in particular to a wafer-level capacitor standard sample and a preparation method thereof.
Background
The semiconductor process monitoring equipment (PCM equipment) is special test equipment used by a semiconductor device development and production unit for batch and rapid test of chip characteristic parameters, evaluation of chip performance and elimination of unqualified chips.
The PCM equipment is used for measuring the on-chip small capacitance parameters, and is applied to the aspects of characteristic analysis of devices and processes, Wafer interconnection small capacitance measurement, C-V curve test of double-end nanometer devices and the like. In order to effectively monitor the process parameters such as gate oxide thickness, gate oxide charge, impurity concentration distribution and the like, the PCM pattern comprises a plurality of capacitance parameters, and the capacitance covers the pF magnitude and is as low as 0.5 pF. Therefore, the "on-chip capacitance parameter" is an important measure for judging the stability of the process related to the capacitor manufacturing.
In the aspect of PCM equipment capacitance parameter calibration, no commercialized on-chip capacitor standard part exists in China at present, and chip production units generally adopt 'product sample retention verification pieces' for preliminary verification. The verification sheet generally has two forms of a single sheet and a wafer. The capacitor on the proof piece is a PCM pattern randomly chosen from the product, with a single magnitude. The verification sheet does not trace to the upper level, can only verify the stability of the process at a certain value point, and cannot guarantee the accuracy in the process of manufacturing the process. Therefore, in order to ensure that the PCM device measures accurate data during the process monitoring, the PCM device should be calibrated by using wafer-level capacitance standard samples covering the measurement range.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to provide a wafer level capacitor standard sample and a preparation method thereof, aiming to meet the requirements of the current PCM device for low capacitance value and high frequency calibration.
In order to achieve the above object, an aspect of the present application provides a wafer level capacitor calibration sample, including: a wafer and a plurality of chip units manufactured on the wafer;
the structure of the chip unit comprises: the circuit breaker comprises a plurality of groups of nominal capacitor series with different magnitudes and circuit breakers which are respectively in one-to-one correspondence with each group of nominal capacitor series, wherein the nominal capacitor series comprises a plurality of nominal capacitors which are arranged in an array by taking a nominal value as a center and taking a preset value as a step; the capacitance ranges of the plurality of nominal capacitance series are: 0.5pF to 100 pF.
According to the wafer-level capacitor standard sample wafer provided by the embodiment of the invention, nominal capacitors with different magnitudes are manufactured on one chip unit, and in order to ensure the accuracy of capacitor testing, each group of nominal capacitor series is respectively provided with one circuit breaker, so that system errors caused by connecting cables, chip layout leads and the like are reduced. The method is used for the integral calibration of the on-chip capacitance parameters of the PCM equipment, ensures the accuracy and the uniformity of high-frequency small capacitance measurement data of the PCM equipment, and meets the calibration requirements of the PCM equipment on low capacitance value and high frequency.
In one possible implementation, the nominal capacitance series includes 4 sets, and the nominal values of the 4 sets of nominal capacitance series respectively correspond to 0.5pF, 1pF, 10pF, and 100 pF.
In one possible implementation, the nominal capacitance series has a test frequency of 100kHz to 1 MHz.
In one possible implementation, the plurality of nominal capacitors in each set of nominal capacitor series are arranged in a row array, and the plurality of sets of nominal capacitor series are arranged in a column array; or the plurality of nominal capacitors in each group of nominal capacitor series are arranged in a column array, and the plurality of groups of nominal capacitor series are arranged in a row.
In one possible implementation, a plurality of the chip units are position-marked using a 1:1 touch pad technology.
In one possible implementation, the nominal capacitance is in four-wire measurement mode, the dimensions and coordinates of the 4 metal electrodes used in the four-wire measurement mode being identical to those of the probe card to which the external test is connected.
In one possible implementation, the nominal capacitance structure is a metal-insulator-metal capacitor, and the dielectric material of the insulator is silicon nitride or silicon dioxide.
In one possible implementation, the dielectric material has a dielectric thickness and a dielectric dimension on the order of μm.
In one possible implementation, the chip unit has a size of 1mm × 1 mm.
On the other hand, the embodiment of the invention provides a preparation method of a wafer-level capacitance standard sample wafer, which comprises the following steps:
providing a wafer as a substrate, and preparing an insulating layer on the substrate;
preparing 4 sets of nominal capacitance series comprising 0.5pF, 1pF, 10pF and 100pF and an open circuit device corresponding to each nominal capacitance series one by one on the insulating layer as a chip unit;
repeatedly preparing a plurality of the chip units;
manufacturing a 1:1 contact plate, and marking a plurality of chip units on the wafer through a photoetching process;
and measuring by using a capacitor on-chip calibration device, and selecting a nominal capacitor consistent with a nominal value as a standard component.
According to the preparation method of the wafer-level capacitor standard sample wafer provided by the embodiment of the invention, a plurality of identical chip units are manufactured on the wafer, nominal capacitors with different magnitudes are arranged on each chip unit, and each group of nominal capacitor series is provided with a circuit breaker. The capacitor design processing method has the advantages that capacitors with various sizes, structures and processes are designed and processed on the same chip unit, all chip units on a wafer are provided with marks, and the position of a nominal capacitor is convenient to position. The capacitor is adopted to measure in a chip calibration device, and a proper capacitor is selected as a standard component. And correspondingly calibrating the PCM equipment by utilizing the developed capacitance sample so as to realize the overall automatic or semi-automatic metering of the capacitance parameters of the equipment.
Drawings
Fig. 1 is a schematic structural diagram of a wafer-level capacitor proof sample according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the structure of a single chip unit of FIG. 1;
FIG. 3 is a schematic diagram of the circuit breaker and a portion of the nominal capacitance of FIG. 2;
FIG. 4 is a schematic diagram of a PAD principle of an on-chip capacitor proof sample provided by an embodiment of the present invention;
FIG. 5 is a process flow diagram of a method for manufacturing a wafer level capacitor proof sample according to an embodiment of the present invention;
in the figure: 1. the device comprises a wafer, 2, a chip unit, 3, a circuit breaker, 3-1, a first circuit breaker, 3-2, a second circuit breaker, 3-3, a third circuit breaker, 3-4, a fourth circuit breaker, 4, 0.5pF nominal capacitance, 5, 1pF nominal capacitance, 5-1, first 1pF nominal capacitance, 6, 10pF nominal capacitance and 7, 100pF nominal capacitance.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
According to the embodiment of the invention, the plurality of capacitors with different magnitudes are prepared on the wafer 1, so that the requirements of low capacitance value and high frequency calibration of PCM equipment are met.
As an embodiment of the present invention, as shown in fig. 1, a wafer level capacitance proof sample comprises: a wafer 1 and a plurality of chip units 2 formed on the wafer 1. The wafer 1 for manufacturing the capacitance standard sample wafer can be selected from Si base, GaN, SiC, GaAs and the like, and different application occasions and cost factors are mainly considered. The wafer 1 used in this embodiment is 4 inches, and the size of one corresponding chip unit 2 is 1mm × 1mm, and the wafer 1 generally includes 40 repeated chip units 2.
As shown in fig. 2, the structure of the chip unit 2 includes: a plurality of nominal capacitance series with different magnitudes and an open circuit 3 corresponding to each nominal capacitance series one by one. The range of values for the nominal capacitance series is: 0.5pF to 100 pF. The series of nominal capacitances comprises a plurality of nominal capacitances arranged in an array centered on a nominal value and stepped by a preset value. In the actual layout design process, due to the influence of multiple aspects such as process fluctuation, environment and the like, the actually processed capacitance value cannot be completely consistent with the design value, and certain process deviation exists, so that a series of capacitor chips need to be designed according to certain step distribution near the center size of the simulation result, and the most stable on-chip capacitor standard component which is closest to the nominal value is ensured to be selected from the capacitor chips. The preset value is set according to the principle that the central dimension corresponding to each group of nominal capacitor series is taken as a core, and the layout dimension is considered according to the process deviation of the line width in the process of processing.
According to the wafer-level capacitance standard sample wafer provided by the embodiment of the invention, nominal capacitances with different magnitudes of 0.5pF-100pF are manufactured on one wafer 1, so that the semi-automatic and full-automatic calibration of PCM equipment can be supported, the PCM equipment does not need to be detached independently, the sample wafer can be loaded on an automatic wafer conveying mechanism, the integral measurement of pF-level capacitance parameters can be completed in a short time, the damage to system stability possibly caused by splitting measurement is avoided, the advantage of 'online measurement' is fully embodied, and the measurement efficiency is greatly improved. At present, the capacitance value of a coaxial form under the domestic frequency of 1MHz is 1pF at the lowest, a shielding structure is generally adopted, the interface is BNC coaxial, and the volume is larger. The capacitor in the form of a real object does not belong to the category of an on-chip standard component, and cannot be directly used for calibrating the probe end face of PCM equipment, so that the on-chip small-capacitance standard component can meet the calibration requirement of the small capacitance of the PCM equipment.
In the embodiment of the present application, in order to meet the accuracy requirement of ± 1% of the capacitance standard, the capacitance graph is designed to be "distributed", that is: and corresponding to a nominal capacitor, a plurality of capacitors can be designed according to the process fluctuation range, and a high-precision capacitor standard component can be obtained.
In the embodiment of the present application, the semiconductor capacitor device on chip is generally two PADs, and when the magnitude is as low as pF, the magnitude of the distribution parameter introduced by the external lead, the probe seat, the probe, etc. is about several tens of femtofarads, even though the open circuit mode in the air by the two probes is different due to the different positions at each open circuit, so the open circuit device 3 designed in the embodiment and corresponding to each nominal capacitor series one by one can fix and eliminate the distribution parameter, thereby achieving the purpose of accurately defining the nominal capacitor.
As an example, the nominal capacitance series comprises 4 sets, the nominal values of the 4 sets of nominal capacitance series corresponding to 0.5pF, 1pF, 10pF, 100pF, respectively. And the test frequency of the nominal capacitor series is 100kHz to 1 MHz. As shown in fig. 2, each set of nominal capacitance series corresponds to one of the switches 3, wherein 0.5pF nominal capacitance series corresponds to the first switch 3-1, 1pF nominal capacitance series corresponds to the second switch 3-2, 10pF nominal capacitance series corresponds to the third switch 3-3, and 100pF nominal capacitance series corresponds to the fourth switch 3-4.
The 0.5pF nominal capacitor 4 in the embodiment belongs to a high-frequency capacitor with a frequency up to 1MHz and a low capacitance value, and two parameters of line width and medium thickness must be accurately controlled to meet the accuracy requirement of +/-2% of a standard component. In the aspect of process manufacturing: the capacitor standard component is a whole set of nominal capacitors, and in order to ensure the consistency of the process, all the nominal capacitors should use one processing platform, namely, the capacitors have the same 'unit area capacitance'. Therefore, the 0.5pF nominal capacitor 4 can not be directly manufactured in a mode of reducing the unit area capacitor, according to a calculation formula of the capacitor, the length-width ratio corresponding to the dead area of a capacitor medium is reduced by one time compared with the 1pF of the conventional capacitor, the width of a corresponding grid bar is in a micrometer level, and higher requirements are placed on the processing precision. The material selection aspect is as follows: the surface of the 0.5pF nominal capacitor 4 is made of a low-stress dielectric film, so that the influence of the tiny deformation of the material on the capacitance value is overcome, the frequency response characteristic of the capacitor is improved, and the accuracy of +/-2% can be achieved under 1 MHz. After the frequency has risen to 1MHz, the magnitude of the distributed parameters introduced by external leads, probe holders, probes, etc. is about tens of femtofarads, which brings trouble to the accurate definition of the 0.5pF nominal capacitance 4. Therefore, in the manufacturing process of the high-frequency 0.5pF nominal capacitor 4, the invention adds the insulating layer between the wafer 1 and the lower metal polar plate of the capacitor, and the purpose of the insulating layer is to reduce the generation of leakage current under high frequency, ensure that the current in a capacitor measuring loop does not leak towards the substrate direction, and furthest ensure the measuring accuracy of small signals.
As an embodiment, the plurality of nominal capacitors in each nominal capacitor series are arranged in a row array, and the plurality of nominal capacitor series are arranged in a column; or the plurality of nominal capacitors in each nominal capacitor series are arranged in an array according to columns, and the plurality of nominal capacitor series are arranged according to rows. As shown in fig. 2, in the embodiment of the present application, each group of the series of nominal capacitors has 8 nominal capacitors, the 8 nominal capacitors are arranged in rows, and the circuit breaker 3 is disposed at the uppermost row of each group of the series of nominal capacitors. Each set of nominal capacitances is: 0.5pF nominal capacitance 4, 1pF nominal capacitance 5, 10pF nominal capacitance 6, 100pF nominal capacitance 7.
The exact definition of the nominal capacitance is based on the open-circuit device 3, as shown in fig. 3, which is a schematic diagram of the first 1pF nominal capacitor 5-1 and its corresponding second open-circuit device 3-2. The uppermost row of each chip unit 2 is an opener 3 corresponding to each group of nominal capacitance series, and 8 nominal capacitances corresponding to the openers are arranged below the openers 3. The first step of measuring the capacitance value in each chip unit 2 is to prick a probe on the shunt 3 of the chip unit 2, and then measure the capacitance to be measured, so the design of the shunt 3 is particularly important. As shown in fig. 2, the circuit breaker 3 is disposed at the uppermost row of each group of nominal capacitance series, and the test sequence is to test the circuit breaker 3 first and then test the nominal capacitance corresponding to the circuit breaker 3; then another shunt 3 is tested and the corresponding nominal capacitance of the other shunt 3 is tested. The circuit breaker 3 and the corresponding nominal capacitor are longitudinally arranged, so that the measuring time after each nominal capacitor is opened is shortened, and the accuracy can be improved when the 0.5pF nominal capacitor 4 is tested.
As an example, the nominal capacitor is structured as a metal-insulator-metal capacitor (MIM capacitor), and the dielectric material of the insulator is silicon nitride or silicon dioxide. The MIM capacitor is a planar 'multilayer structure', has the advantages of small loss, small parasitic capacitance, higher breakdown voltage, small influence of bias voltage on capacitance value and the like, is close to the manufacturing process of a tested PCM pattern to the greatest extent, and is suitable for serving as a special PCM standard component. The upper layer and the lower layer of metal material of the MIM capacitor are Au, the uppermost surface is a SiN passivation layer, the manufactured electrode PAD material is Au, and the coordinate design of the electrode PAD material is consistent with the coordinate design of the most representative PCM pattern on the production line.
In the embodiments of the present application, the thickness of the dielectric material and the dielectric dimensions are in the order of μm during the design of the MIM capacitor. According to the 4 target nominal capacitance values, the medium thickness, positive opposite area and other values in the process machining process are calculated by using a theoretical formula, and the specific parameter design process is as follows:
the ideal plate capacitor belongs to a sandwich structure (a dielectric medium is sandwiched between a pair of electrodes), and is processed from the bottom to the top of a substrate in a multilayer mode.
The capacitance calculation method is shown in formula (1),
capacitance and unit area capacitance (C) under the premise of fixed medium thickness□) And the plate facing area (S). The semiconductor fabrication process has multiple processing platforms, typically measuring from 1000pF/mm2To 50pF/mm2The platform types and the medium thickness d are in one-to-one correspondence. The capacitance processing platform is determined according to the target nominal capacitance value, and the selection principle is that the capacitance processing platform is closest to the target capacitance value, so that the scheme can ensure the smallest capacitor device dead-against area and can avoid the process deviation caused by undersize processing.
The 4 target nominal capacitance systems are an inseparable whole, capacitance values need to be comprehensively considered in consideration of requirements of process consistency and production cost, a unified processing platform is determined, and (100-500) pF/mm is selected2And (7) processing the platform. As can be seen from formula (1), in C□Under the premise of determination, the capacitance value is only related to the positive area S of the polar plate, and is setThe target nominal capacitance value can be obtained by directly aligning the length and the width of the area, and the design value is detailed in the attached table description of the table 1:
TABLE 1 capacitance Standard parts graphic parameters
In setting the nominal capacitance series preset values, the relative dimensions in table 1 can be referenced.
In the manufacturing process of the high-frequency 0.5pF nominal capacitor 4, an insulating layer is added between the substrate of the wafer 1 and the metal polar plate of the capacitor, and the purpose of the insulating layer is to reduce the generation of leakage current under high frequency, ensure that the current in a capacitor measurement loop does not leak towards the substrate direction, and ensure the measurement accuracy of small signals to the maximum extent.
As an embodiment, since the wafer 1 is provided with the plurality of chip units 2, and each chip unit 2 is provided with a plurality of groups of nominal capacitor series, the repeated chip units 2 on the wafer 1 can be marked by adopting a 1:1 contact board technology, so as to accurately position the plurality of groups of chip units 2.
As an example, the conventional capacitor PAD size cannot meet PCM system calibration requirements, i.e. cannot be directly used for PCM auto-calibration. The wafer-level capacitor standard component designed by the embodiment of the invention adopts a 'same-nominal in-line distributed' structure, the PAD size is in one-to-one correspondence with the PCM system to be calibrated, and the PAD size can be directly used for full-automatic calibration. The nominal capacitance in this embodiment is in four-wire measurement mode, and the dimensions and coordinates of the 4 metal electrodes used in four-wire measurement mode are consistent with those of the probe card to which external test is connected.
In the embodiment of the application, 4 sets of nominal capacitance series are all in the pF magnitude, the minimum magnitude is 0.5pF, and on the basis of completing the design of the graph dimension, the error introduced by a measuring loop must be reduced to the minimum so as to be accurately calibrated. And in the layout step, designing the PAD layout and the test lead of the nominal capacitor standard component. PAD as the key part of the contact between the chip capacitor standard and the probe/probe card, PADs of 4 groups of nominal capacitor series should be consistent, the size interval of each PAD should be designed symmetrically, the test lead is designed in a four-wire mode as shown in FIG. 4, wherein A, B is the current terminal of the capacitor, and C, D is the voltage sampling terminal. The size and the spacing of the PAD are consistent with those of the PCM patterns, and the design scheme can meet the test requirement of the direct current probe, can be matched with a probe card of a calibrated system, and meets the layout and wiring requirements of a standard part.
As another embodiment of the present invention, the present invention further provides a method for preparing a wafer-level capacitor standard sample, wherein the preparation process requires a plurality of links such as substrate processing, metallization, dielectric deposition, photolithography, passivation, and the like, and as shown in fig. 5, the method specifically includes the following steps:
1) preparing a substrate: the wafer 1 is used as a substrate, and deionized water and the like are used for cleaning the surface of the substrate to remove dirt;
2) manufacturing an insulating layer: an insulating layer is manufactured by depositing a thin-layer dielectric material, and a metal layer (such as a metal pole plate) on the insulating layer is prevented from permeating downwards;
3) transferring the pattern of the lower polar plate: manufacturing a pattern of a lower electrode plate of the capacitor through a photoetching process;
4) manufacturing a lower polar plate: manufacturing a capacitor lower polar plate (corresponding to an M layer in an MIM capacitor structure) by using a metal material through a photoetching process;
5) manufacturing a capacitor medium: depositing a dielectric material (e.g. SiN, SiO) according to the process parameters2) Forming a dielectric layer corresponding to the 'I' (dielectric layer) of the MIM plate;
6) transferring the upper polar plate pattern: manufacturing a pattern of an upper electrode plate of the capacitor through a photoetching process;
7) manufacturing an upper polar plate: manufacturing an upper polar plate (corresponding to an M layer in the MIM capacitor structure) by using a metal material through a photoetching process;
8) transferring the PAD/lead pattern: making PAD and lead patterns by a photoetching process;
9) manufacturing a PAD/lead: according to the test requirement, depositing metal (such as Ag), and manufacturing PAD and leads;
10) making a chip unit (CELL) mark: manufacturing a 1:1 contact plate, and manufacturing unique marks for all chip units on a wafer through a photoetching process;
11) manufacturing a passivation layer: the uppermost surface of the device is deposited with a passivation layer (such as SiN) to protect the device from external moisture, dust and the like.
And after the wafer-level capacitor standard sample wafer is prepared, measuring by using a capacitor on-wafer calibration device, and selecting a nominal capacitor consistent with a nominal value as a standard component.
In the embodiment of the application, the resistance of a plurality of nominal resistance series in a plurality of prepared chip units is tested by adopting a capacitance on-chip calibration device consisting of a probe station, a standard instrument (LCR measuring instrument), a connecting cable and a probe card (or a probe seat) and testing the chips one by adopting a four-wire method. The method comprises the following steps:
1) primary screening: screening out (5-15) sets within +/-20% of process deviation;
2) and (4) final screening: and performing repeatability and stability assessment on the primary screened product within 1 year, wherein the stability of the primary screened product is superior to that of the index 1/3 and the primary screened product is used as a final standard component.
The final format of the standard is a wafer 1, and the standard has a plurality of repeating chip units 2, each chip unit 2 includes 4 nominal capacitors of 0.5pF, 1pF, 10pF and 100pF, and an open circuit device 3 corresponding to the nominal capacitors of 4 nominal values.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Claims (10)
1. A wafer level capacitance proof sample wafer, comprising: a wafer and a plurality of chip units manufactured on the wafer;
the structure of the chip unit comprises: the circuit breaker comprises a plurality of groups of nominal capacitor series with different magnitudes and circuit breakers which are respectively in one-to-one correspondence with each group of nominal capacitor series, wherein the nominal capacitor series comprises a plurality of nominal capacitors which are arranged in an array by taking a nominal value as a center and taking a preset value as a step; the capacitance ranges of the plurality of nominal capacitance series are: 0.5pF to 100 pF.
2. The wafer-level capacitance proof sample wafer of claim 1, wherein the nominal capacitance series comprises 4 sets, and the nominal values of the 4 sets of nominal capacitance series correspond to 0.5pF, 1pF, 10pF, 100pF, respectively.
3. The wafer-level capacitive proof mass of claim 1, wherein the nominal capacitance family has a test frequency of 100kHz to 1 MHz.
4. The wafer-level capacitance proof sample wafer of claim 1 or 2, wherein a plurality of nominal capacitances in each set of the series of nominal capacitances are arranged in a row array, and a plurality of sets of the series of nominal capacitances are arranged in a column array; or the plurality of nominal capacitors in each group of nominal capacitor series are arranged in a column array, and the plurality of groups of nominal capacitor series are arranged in a row.
5. The wafer-level capacitive reference sample as recited in claim 1, wherein a plurality of the chip units are position-marked using a 1:1 touch pad technique.
6. The wafer-level capacitance proof sample of claim 5, wherein the nominal capacitance is in four-wire measurement mode, and the dimensions and coordinates of the 4 metal electrodes used in the four-wire measurement mode are consistent with the dimensions and coordinates of a probe card connected to an external test.
7. The wafer level capacitor proof sample of claim 1, wherein the nominal capacitor has a metal-insulator-metal structure, and the dielectric material of the insulator is silicon nitride or silicon dioxide.
8. The wafer-level capacitive proof mass of claim 7, wherein the dielectric material has a dielectric thickness and a dielectric dimension on the order of μm.
9. The wafer-level capacitive proof-sample of claim 1, wherein the chip unit has a size of 1mm x 1 mm.
10. A preparation method of a wafer-level capacitor standard sample is characterized by comprising the following steps:
providing a wafer as a substrate, and preparing an insulating layer on the substrate;
preparing 4 sets of nominal capacitance series comprising 0.5pF, 1pF, 10pF and 100pF and an open circuit device corresponding to each nominal capacitance series one by one as a chip unit on the insulating layer;
repeatedly preparing a plurality of the chip units;
manufacturing a 1:1 contact plate, and marking a plurality of chip units on the wafer through a photoetching process;
and measuring by using a capacitor on-chip calibration device, and selecting a nominal capacitor consistent with a nominal value as a standard component.
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| CN113866511A (en) * | 2021-08-26 | 2021-12-31 | 中国电子科技集团公司第十三研究所 | On-chip capacitance measuring system and measuring method |
| CN113866511B (en) * | 2021-08-26 | 2024-04-16 | 中国电子科技集团公司第十三研究所 | On-chip capacitance measurement system and measurement method |
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| CN212008893U (en) * | 2020-03-02 | 2020-11-24 | 厦门市三安集成电路有限公司 | Calibration wafer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113866511A (en) * | 2021-08-26 | 2021-12-31 | 中国电子科技集团公司第十三研究所 | On-chip capacitance measuring system and measuring method |
| CN113866511B (en) * | 2021-08-26 | 2024-04-16 | 中国电子科技集团公司第十三研究所 | On-chip capacitance measurement system and measurement method |
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