CN106098582A - Calibration is used in chip capacitor standard component and preparation method thereof - Google Patents
Calibration is used in chip capacitor standard component and preparation method thereof Download PDFInfo
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- CN106098582A CN106098582A CN201610628267.4A CN201610628267A CN106098582A CN 106098582 A CN106098582 A CN 106098582A CN 201610628267 A CN201610628267 A CN 201610628267A CN 106098582 A CN106098582 A CN 106098582A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Abstract
The invention discloses a kind of calibration and be used in chip capacitor standard component and preparation method thereof, relate to test metering device technique field.Described standard component includes that dielectric substrate, the upper surface of described dielectric substrate are provided with the different standard capacitance of several capacitances and a standard open circuit device.Of the present invention at chip capacitor standard component, it is possible to achieve piece calibration MEMS wafer sheet to be measured the system overall measurement and calibration in chip capacitor parameter, it is achieved magnitude tracing, it is ensured that the wafer chip level measurement result in MEMS production process is accurately, unanimously.This standard component can provide the capacitance (1pF～100pF, test frequency 1kHz～100kHz) with traceability, can be designed in the range of above-mentioned value as required.
Description
Technical field
The present invention relates to test metering device technique field, particularly relate to a kind of calibration be used in chip capacitor standard component and
Preparation method.
Background technology
MEMS wafer chip test system be each MEMS development and production unit for batch, quickly test chip features parameter,
Evaluate chip performance, reject the special test equipment of defective chip, be mainly used in testing the plates capacitance value (electricity of MEMS
Hold parameter) characteristic, accurately measure these parameters for ensure MEMS product accurately and reliably with ensure that yield rate has the heaviest
The meaning wanted.
The typical structure of MEMS wafer chip test system is as it is shown in figure 1, by capacitance measuring instrument, matrix switch, power supply mould
Block, probe station system are constituted.Wherein, probe station system mainly includes connecting cable, the portion such as probe station, probe card (or probe base)
Part.
The purpose of capacitance measurement is by measuring the small electric capacitance fixing between tooth or movable teeth in comb electric capacity,
According to electrical quantity and then the physical parameter such as accekeration of deriving correspondence, thus complete the design work of accelerometer.Therefore,
Accurately measuring of capacitance parameter is especially significant to the quality of final products to wafer.
Below as a example by the wafer of MEMS capacitance accelerometer product is tested, capacitance parameter test process and important
Property.Typical MEMS capacitance accelerometer structure is as in figure 2 it is shown, be comb structure.I.e. sensing element is a bilateral comb structure,
The change (acceleration as extraneous) of extraneous non electrical quantity can be converted into the change of capacitance with movable teeth by fixing tooth, is used for accelerating
The measurement of the physical quantitys such as degree.Mass is H type, and mass is fixed on horizontal direction, mass by four thin beams (such as a, b 2 point)
Freely-movable along horizontal direction with the change of extraneous acceleration.Movable teeth stretches out to both sides from mass, with fixing tooth (as
C, d 2 point) form two electrodes of electric capacity, some groups of electrodes are interconnected, form differential detection electrode, thus measure the external world and add
The change of rate signal.
When Design Theory, the value of comb electric capacity is through design, and the actual chip processed wishes that capacitance is to the greatest extent
Amount meets design load.The final response of accelerometer product is the most relevant to capacitance, therefore to obtain the spy of accelerometer
Property, it is necessary to accurately measure between fixing tooth, between movable teeth, or the capacitance between fixing tooth and movable teeth.In view of
The MEMS wafer chip test system capacitance parameter accuracy significance to product quality, needs such system carries out overall meter
Amount calibration, so it also avoid due to quasi-instrument each in frequent disassembling system (such as matrix switch, LCR measuring instrument, power module)
The systematic entirety that may cause can be inconsistent situation, thus realize the entirety at chip capacitor value and trace to the source, it is ensured that value is accurate
Really, unanimously, Liao Qian road process procedure and rear road test encapsulation the carrying out smoothly of link are ensured, it is to avoid the waste of packaging cost,
Improve production efficiency.
The domestic technological means being disclosed and product all cannot realize the metering to MEMS wafer chip test system electric capacity
Calibration, the calibration program that instrument producer takes is to be calibrated by the composition instrument separate unit of system, accurately can not of separate unit instrument
Ensure the accurate, this is because the measurement result of probe end face is by outside electromagnetic interference and the influence amount of probe system of probe end face
Relatively big, so cannot eliminate the influence amount brought due to lead-in wire, probe card, probe station；MEMS producer makees frequently with test product
For checking part, the drawback of this way is that operator does not has means to ensure the long-time stability of checking part, moreover cannot measure it
Accuracy.Above two means one are to calibrate to probe end face, and two is to ensure its accuracy, therefore cannot realize electricity
Hold tracing to the source of parameter, it is impossible to reach the purpose that value is accurate, consistent.
The relevant report at sheet standard component of link is surveyed in the document needleless centering of external open report.NIST is only to MEMS
The five in one reference standard material that the test system of finished product (such as mems accelerometer, MEMS gyroscope etc.) is applied
(RM8096 and RM8097) has carried out relevant elaboration and has sold as product.This kind of standard substance can measure the eight of MEMS product
Big technical characteristic (Young's modulus, shoulder height, overstrain, strain gradient, plane length, residual stress, stress gradient, horizontal stroke
Cantilever thickness).But, these parameters are the characterisitic parameters of final products, rather than " the middle survey link " wafer mentioned by this paper is surveyed
Needed for the examination stage.
To sum up, existing public technology and the standard sample of photo of commercialization or standard substance all cannot solve the survey of MEMS wafer sheet
Test system is in sheet D.C. resistance, the piece calibration problem of capacitance parameter.
Summary of the invention
The technical problem to be solved is to provide a kind of calibration and is used in chip capacitor standard component and preparation method thereof, institute
State standard component can solve in chip capacitor parameter in sheet calibration problem, it is achieved MEMS wafer built-in testing conventional in MEMS technology
The tracing to the source in chip capacitor parameter of system, it is ensured that value is accurately, unanimously.
For solving above-mentioned technical problem, the technical solution used in the present invention is: a kind of calibration is used in chip capacitor standard component,
It is characterized in that: include dielectric substrate, the upper surface of described dielectric substrate be provided with the different standard capacitance of several capacitances and
One standard open circuit device.
Further technical scheme is: include described in described standard capacitance that substrate, described substrate are provided with comb electric capacity,
Described comb electric capacity includes several discrete capacitor being connected in parallel, and wherein the negative pole of comb electric capacity is positioned at two row electric capacity
Side, and the negative pole of electric capacity is provided with two negative plates, the positive pole of described electric capacity is positioned at the outside of two row electric capacity, and the positive pole of electric capacity
Being provided with two positive plates, described pole plate arranges string, and positive plate is positioned at the rear side of described standard capacitance, described negative plate position
In the front side of described standard capacitance, it is provided with ground connection pole plate, described two positive plates and two with the substrate of described pole plate string
Individual negative plate is for being connected with LCR measuring instrument, it is achieved the measurement to described standard capacitance, two positive plates therein are respectively used to
Connect the I of LCR measuring instrumentHEnd and PHEnd, two negative plates are respectively used to connect the I of LCR measuring instrumentLEnd and PLEnd.
Further technical scheme is: described standard capacitance also includes and described anode plate, negative plates and connect
Pole plate reserved by symmetrical five discrete first of the pole plate in ground.
Further technical scheme is: the distance between the electrode of two, the same side is 200 μm-400 μm, horizontal direction two
Distance between individual electrode is 9mm-11mm.
Further technical scheme is: described standard open circuit device includes substrate, and left side or the right side of described substrate are provided with
String five elements' pole plate, be wherein positioned at rear side two the first pole plates for being connected by the positive pole of metal lead wire with comb electric capacity,
Two middle the second pole plates are for being connected by the negative pole of metal lead wire with comb electric capacity, and a tri-electrode of front side is used
In ground connection.
Further technical scheme is: be provided with five points with described first to the 3rd symmetrical opposite side of battery lead plate
Vertical second reserves pole plate.
Further technical scheme is: described standard capacitance is provided with three, and capacitance is respectively 1pF, 10pF and 100pF.
The invention also discloses a kind of calibration and be used in chip capacitor standard component preparation method, it is characterised in that include walking as follows
Rapid:
1) preparing electric capacity and open circuit device on two wafers respectively, one of them wafer includes several different appearances
The electric capacity of value, another wafer includes several devices of opening a way；
2) wafer is carried out scribing process, form several discrete electric capacity and open circuit device, use MEMS chip disk
Discrete electric capacity is packaged by level packaging technology；
3) use LCR measuring instrument that discrete electric capacity and open circuit device are tested, select satisfactory electric capacity and open
Road device is as standard capacitance and standard open circuit device；
4) using quartz wedge as carrier, device of standard capacitance and standard being opened a way sticks on quartz wedge, forms electric capacity mark
Quasi-part.
Further technical scheme is: the described method preparing electric capacity on a wafer is as follows:
1) complete mark on a wafer, prepared by dicing lane；
2) by photoetching, the preparation of corrosion window has been etched；
3) metal line is completed by photoetching, metallization process；
4) complete to be bonded block by photoetching, etching technics to prepare；
5) complete comb capacitance structure by photoetching, etching technics to prepare；
6) structured bonding is completed；
7) completed the making of probe test window by photoetching, etching technics, make pole plate expose.
Further technical scheme is: the preparation method of described comb electric capacity is as follows:
1) bury oxide layer by introducing one layer between at the bottom of top layer silicon and backing, prepare soi structure；
2) do mask layer with photoresist, utilize ICP deep etching method by lower floor's silicon base partial etching of soi structure
Fall；
3) RIE reactive ion etching method is utilized to be fallen by the intermediate etch of silicon dioxide layer；
4) utilize sputtering technology in the position of above-mentioned silicon dioxide sputtering layer of metal film to overcome Nothing effect:
5) in the top layer silicon of soi structure, it is coated with a layer photoetching glue, and carries out photoetching making and go out dentation figure；
6) ICP deep etching method is utilized to etch required mass figure；
7) caustic solution is utilized to be fallen by the Metallic film corrosion in the middle of soi structure；
8) caustic solution is utilized to be removed by uppermost for soi structure photoresist, dispensing device structure.
Use and have the beneficial effects that produced by technique scheme: be of the present invention at chip capacitor standard component, Ke Yishi
Now piece calibration MEMS wafer sheet is measured the system overall measurement and calibration in chip capacitor parameter, it is achieved magnitude tracing, it is ensured that
Wafer chip level measurement result in MEMS production process is accurately, unanimously.This standard component can provide the capacitance with traceability
(1pF～100pF, test frequency 1kHz～100kHz), can be designed as required in the range of above-mentioned value.This standard
Part uses MEMS chip wafer level packaging so that standard component is not affected by factors such as extraneous dust, humiture, electromagnetic interference,
There are good repeatability and long-time stability.
Accompanying drawing explanation
Fig. 1 is typical at MEMS wafer chip test system structural representation；
Fig. 2 is typical capacitance accelerometer structural representation；
Fig. 3 is the principle schematic of comb electric capacity；
Fig. 4 is photolithography edition territory design diagram；
Fig. 5 is the preparation flow figure of standard capacitance described in the embodiment of the present invention；
Fig. 6 a-Fig. 6 h is the preparation figure of comb electric capacity；
Fig. 7 is the structural representation of standard capacitance described in the embodiment of the present invention；
Fig. 8 is the structural representation of the open circuit device of standard described in the embodiment of the present invention；
Fig. 9 is electric capacity calibration process connection diagram；
Figure 10 is the structural representation of standard component described in the embodiment of the present invention；
Wherein: 1, mass 2, fixing tooth 3, movable teeth 4, positive plate 5, negative plate 6, comb electric capacity 7, probe are surveyed
Examination window 8, corrosion window 9, capacitance structure 10, metal line 11, dicing lane
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground describes, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention is all right
Using other to be different from alternate manner described here to implement, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
As shown in Figure 10, the invention discloses a kind of calibration and be used in chip capacitor standard component, including dielectric substrate, described insulation
The upper surface of substrate is provided with the different standard capacitance of several capacitances and a standard open circuit device, the most described mark
Pseudo-capacitance is provided with three, and capacitance is respectively 1pF, 10pF and 100pF, it should be pointed out that the capacitance of standard capacitance is not limited to
In the above-mentioned type, those skilled in the art can carry out selecting and arranging according to actual needs.
In one embodiment of the invention, as it is shown in fig. 7, include substrate described in described standard capacitance, on described substrate
Being provided with comb electric capacity, described comb electric capacity includes several discrete capacitor being connected in parallel, and wherein the negative pole of comb electric capacity is positioned at
The inner side of two row electric capacity, and the negative pole of electric capacity is provided with two negative plates, the positive pole of described electric capacity is positioned at the outside of two row electric capacity,
And the positive pole of electric capacity is provided with two positive plates, described pole plate arranges string, and positive plate is positioned at the rear side of described standard capacitance,
Described negative plate is positioned at the front side of described standard capacitance, is provided with ground connection pole plate, described two with the substrate of described pole plate string
Individual positive plate and two negative plates are for being connected with LCR measuring instrument, it is achieved the measurement to described standard capacitance, therein two just
Pole plate is respectively used to connect the I of LCR measuring instrumentHEnd and PHEnd, two negative plates are respectively used to connect the I of LCR measuring instrumentLEnd and
PLEnd.
Further for later extended method, described standard capacitance also include with described anode plate, negative plates with
And symmetrical five discrete first of ground connection pole plate reserves pole plate.
In one embodiment of the invention, as shown in Figure 8, described standard open circuit device includes substrate, a left side for described substrate
Side or right side are provided with string five elements' pole plate, are wherein positioned at two the first pole plates of rear side for by metal lead wire and comb electric capacity
Positive pole connect, two middle the second pole plates for being connected by the negative pole of metal lead wire with comb electric capacity, on front side of one
Individual tri-electrode is used for ground connection, and to be provided with five discrete second pre-with described first to the 3rd symmetrical opposite side of battery lead plate
Stay pole plate.
The invention also discloses a kind of calibration and be used in chip capacitor standard component preparation method, comprise the steps:
1) preparing electric capacity and open circuit device on two wafers respectively, one of them wafer includes several different appearances
The electric capacity of value, another wafer includes several devices of opening a way；
2) wafer is carried out scribing process, form several discrete electric capacity and open circuit device, use MEMS chip disk
Discrete electric capacity is packaged by level packaging technology；
3) use LCR measuring instrument that discrete electric capacity and open circuit device are tested, select satisfactory electric capacity and open
Road device is as standard capacitance and standard open circuit device；
4) using quartz wedge as carrier, device of standard capacitance and standard being opened a way sticks on quartz wedge, forms electric capacity mark
Quasi-part.
Below in conjunction with concrete theory, above structure is illustrated:
The comb electric capacity that the present invention makes uses the structure design that N group electric capacity is in parallel, as shown in Figure 3.This structure is permissible
In limited space, electric capacity less for some polar plate areas is together in parallel and forms bigger electric capacity, it is thus possible to obtain relatively
Big capacitance and resolving power.
According to plate capacitors computing formula:
(the dielectric constant of wherein ε: medium；The height of the width of l: pole plate: h: pole plate；The spacing of d: pole plate；N: electric capacity
Group number).The medium that the present invention uses is air, by fixing ε, l, h and d value, the number of regulation N, i.e. changes shunt capacitance
Group number, thus reach target capacitance and prepare.
In order to realize the preparation of standard capacitance, backing material selects monocrystal silicon, and main cause has 6 aspects: a) mechanical property
Can be stable, and can be integrated on the electronic device of same substrate；B) silicon is almost a preferable structural material, and it has
Almost identical with steel Young's modulus, but light as aluminum；C) light weight of silicon materials, density is stainless 1/3, and curved
Qu Qiangdu is but stainless 3.5 times, and it has high strength to density ratio and high rigidity density ratio；D) its fusing point is 1400
DEG C, the about twice of aluminum；E) its thermal coefficient of expansion than steel little times, less 10 times than aluminum；F) monocrystal silicon has excellent machinery, thing
Rationality matter, its mechanical quality factor may be up to 106 orders of magnitude, delayed minimum with creep, almost nil, and good mechanical stability is
Preferably sensor and the material of executor.Therefore, silicon substrate has greater flexibility, as electric capacity in design and manufacture
The substrate of standard sample of photo.
Standard capacitance has carried out layout design, as shown in Figure 4.One is divided into 6 steps: 1) prepared by mark, dicing lane, position
In the outermost dicing lane of chip, primarily to electric capacity disk is cut into junior unit one by one after completing and prepares
's；2) opening corrosion window, structure and morphology is etched by the means that the structured window of all needs is required for by dry etching
Come；3) prepared by metal line, and in domain, all of region needing signal is required for practical metal Au and carries out metal line, as
The positive pole of electric capacity, the negative pole of electric capacity and both and the line of probe test window PAD；4): prepared by bonding block, the present invention uses
Compound bonding in " Au-Si bonding " technology, principle is to utilize the mutual low-melting feature of gold silicon；5): prepared by capacitance structure, ash
The region of color is the comb structure of capacitor, is to be formed in parallel by the tooth of several high-aspect-ratios；6): probe test window system
Standby, be designed with during being positioned at each side 5 PAD, PAD making of chip is the coupled reaction in dry etching
Plasma etching, integrated artistic flow process is as shown in Figure 5.
Wherein, the preparation method of comb electric capacity is crucial, uses the technique as shown in Fig. 6 a-6h, comprises the steps: 1)
Lower floor in SOI device structure carries out ICP body silicon etching；2) silicon dioxide layer is carried out RIE etching；3) metal film sputtering: 4)
Photoetching on silicon fiml；5) ICP mass etching；6) Metallic film corrosion；7) device architecture release.
By the computing formula of capacitor model, according to technological process, it then follows layout design principle, real on 6 cun of Si disks
Show the preparation of tri-capacitances of 1pF, 10pF, 100pF, and carried out distribution design, it is therefore intended that from a series of products
The print filter out repeatability, having good stability is as final standard component.The overall construction design of chip is as shown in Figure 7.
Wherein to be that 5 PAD are internal be connected with comb electric capacity in left side, outside as calibrating terminal, front four as test lead
Mouth is connected as signal testing terminal with probe (or exploration card), and a bottom PAD holds as shell；In 5 PAD in right side
Portion is empty, is to coordinate the exploration card of symmetrical structure to use and custom-designed.
According to the typical sizes of MEMS product, PAD (electrode) spacing and size are designed: the same side PAD one by one
Vertical direction interval is about 300 μm, and the size between two PAD of horizontal direction is 10mm, and the specification of each PAD is (12.3*
4.1) μm, the width of outside dicing lane is 40 μm, and it is as shown in the table for detailed PAD coordinate position.
Table 1-PAD position respective coordinates
| Position | X(μm) | Y(μm) | Position | X(μm) | Y(μm) |
| A | 1320 | 1565 | A’ | -8680 | 1565 |
| B | 1320 | 930 | B’ | -8680 | 930 |
| C | 1320 | 330 | C’ | -8680 | 330 |
| D | 1320 | -330 | D’ | -8680 | -330 |
| E | 1320 | -930 | E’ | -8680 | -930 |
3 pre-designed standard components are carried out distribution row by typical wafer chip layout according to MEMS product on a wafer
Row, are laid out according to 1pF (3 row), 10pF (2 row), the principle of 100pF (2 row), have arranged altogether 4 groups, are total to about 230～250
Individual chip.
Present invention design in the main purpose of sheet open circuit device is, eliminate the institute outside comb electric capacity core devices leaded,
The impact that PAD, the test factor such as cable, probe system are brought, the capacitance of the print of accurate definition design.Mentality of designing be
On the basis of original layout design, the part of output capacitance being removed, other holding is constant, as shown in Figure 8.
Encapsulation is to utilize certain material to be protected by chip, and the mode that is isolated from the outside and processing method.Encapsulation
Effect: there is protection and buffer action；Suitable outer lead structure is provided for chip；Heat radiation and electromagnetic shielding bar is provided for chip
Part；Improve mechanical strength and the ability of anti-foreign impacts of chip.
MEMS is wanted to form a contact interface between test environment and obtain non-electrical signal, and external environment condition is to spirit
Being all the harshest for the MEMS sensing element that sensitivity is high, it to have the ability bearing each side environmental effect, such as
(stress swings, impact etc.) of machinery, (gas, temperature, corrosive medium etc.), (temperature, pressure, the acceleration of physics of chemistry
Deng) etc..All include mobilizable element due to MEMS, owing to MEMS volume is little, it is special the most all must to use
Technology and encapsulation.Standard capacitance in the present invention takes the design of wafer-level packaging.To adapt to its suspension, movable structure
Particularity, prevent it to be damaged, adhere to moisture, dust, reach the purpose avoiding losing efficacy.
Follow parameter designing and according to layout design, by related process flow process, 6 cun of Si disks achieve 1pF,
The preparation of tri-capacitances of 10pF, 100pF, and carried out distribution design, it is therefore intended that from a series of products, filter out weight
Renaturation, the print having good stability are as final standard component.
Using electric capacity the four lines measuring method when robot scaling equipment is calibrated, concrete connection is as shown in Figure 9.Utilize calibration dress
Put the data to first examination to screen, select the process deviation standard component to be examined of the conduct within 20%, to first sieve
The print selected is examined, and is spaced examination in 3 months once, and the final standard component made is as shown in Figure 10.Use 40mm*
The quartz wedge of the 2mm thickness of 40mm is as carrier, thereon by laser marking machine by information such as unit, title, numbering, capacitances
Can stick on quartz wedge after electric capacity, open circuit device scribing above, wherein open circuit device is the electricity that hereinbefore MEMS technology is developed
Hold open-circuit structure.Standard component repeatability is better than 0.05%, and within its year, stability is better than 0.1%, calibrates accuracy 1%, can carry out
Working at sheet piece calibration of MEMS wafer chip test system.
Of the present invention at chip capacitor standard component, it is possible to achieve system of measuring piece calibration MEMS wafer sheet is at chip capacitor
The overall measurement and calibration of parameter, it is achieved magnitude tracing, it is ensured that the wafer chip level measurement result in MEMS production process accurately, one
Cause.This standard component can provide the capacitance (1pF～100pF, test frequency 1kHz～100kHz) with traceability, Ke Yigen
It is designed in the range of above-mentioned value according to needs.This standard component uses MEMS chip wafer level packaging so that standard component is not subject to
The impact of the factors such as extraneous dust, humiture, electromagnetic interference, has good repeatability and long-time stability.
Claims (10)
1. a calibration is used in chip capacitor standard component, it is characterised in that: include that dielectric substrate, the upper surface of described dielectric substrate set
There are the different standard capacitance of several capacitances and a standard open circuit device.
2. calibration as claimed in claim 1 is used in chip capacitor standard component, it is characterised in that: include lining described in described standard capacitance
The end, described substrate is provided with comb electric capacity, and described comb electric capacity includes several discrete capacitor being connected in parallel, wherein comb electricity
The negative pole held is positioned at the inner side of two row electric capacity, and the negative pole of electric capacity is provided with two negative plates, and the positive pole of described electric capacity is positioned at two
The outside of row electric capacity, and the positive pole of electric capacity is provided with two positive plates, described pole plate arranges string, and positive plate is positioned at described mark
The rear side of pseudo-capacitance, described negative plate is positioned at the front side of described standard capacitance, is provided with ground connection with the substrate of described pole plate string
Pole plate, two described positive plates and two negative plates are for being connected with LCR measuring instrument, it is achieved the survey to described standard capacitance
Amount, two positive plates therein are respectively used to connect the I of LCR measuring instrumentHEnd and PHEnd, two negative plates are respectively used to connect LCR
The I of measuring instrumentLEnd and PLEnd.
3. calibration as claimed in claim 2 is used in chip capacitor standard component, it is characterised in that: described standard capacitance also includes and institute
State symmetrical five discrete first of anode plate, negative plates and ground connection pole plate and reserve pole plate.
4. calibration as claimed in claim 3 is used in chip capacitor standard component, it is characterised in that: between the electrode of two, the same side away from
From for 200 m-400 m, the distance between two electrodes of horizontal direction is 9mm-11mm.
5. calibration as claimed in claim 1 is used in chip capacitor standard component, it is characterised in that: described standard open circuit device includes lining
The end, the left side of described substrate or right side are provided with string five elements' pole plate, are wherein positioned at two the first pole plates of rear side for by gold
Belonging to lead-in wire to be connected with the positive pole of comb electric capacity, two middle the second pole plates are for by the negative pole of metal lead wire Yu comb electric capacity
Connecting, a tri-electrode of front side is for ground connection.
6. calibration as claimed in claim 5 is used in chip capacitor standard component, it is characterised in that: with described first to the 3rd battery lead plate
Symmetrical opposite side is provided with five discrete second and reserves pole plate.
7. calibration as claimed in claim 1 is used in chip capacitor standard component, it is characterised in that: described standard capacitance is provided with three,
Capacitance is respectively 1pF, 10pF and 100pF.
8. a calibration is used in chip capacitor standard component preparation method, it is characterised in that comprise the steps:
1) preparing electric capacity and open circuit device on two wafers respectively, one of them wafer includes several different capacitances
Electric capacity, another wafer includes several devices of opening a way；
2) wafer is carried out scribing process, form several discrete electric capacity and open circuit device, use MEMS chip wafer level envelope
Discrete electric capacity is packaged by dress technique；
3) use LCR measuring instrument that discrete electric capacity and open circuit device are tested, select satisfactory electric capacity and open circuit device
As standard capacitance and standard open circuit device；
4) using quartz wedge as carrier, device of standard capacitance and standard being opened a way sticks on quartz wedge, forms capacity standard part.
9. calibration as claimed in claim 8 is used in chip capacitor standard component preparation method, it is characterised in that described at wafer
On to prepare the method for electric capacity as follows:
1) complete mark on a wafer, prepared by dicing lane；
2) by photoetching, the preparation of corrosion window has been etched；
3) metal line is completed by photoetching, metallization process；
4) complete to be bonded block by photoetching, etching technics to prepare；
5) complete comb capacitance structure by photoetching, etching technics to prepare；
6) structured bonding is completed；
7) completed the making of probe test window by photoetching, etching technics, make pole plate expose.
10. calibration as claimed in claim 9 is used in chip capacitor standard component preparation method, it is characterised in that described comb electricity
The preparation method held is as follows:
1) bury oxide layer by introducing one layer between at the bottom of top layer silicon and backing, prepare soi structure；
2) do mask layer with photoresist, utilize ICP deep etching method to be fallen by lower floor's silicon base partial etching of soi structure；
3) RIE reactive ion etching method is utilized to be fallen by the intermediate etch of silicon dioxide layer；
4) utilize sputtering technology in the position of above-mentioned silicon dioxide sputtering layer of metal film to overcome Nothing effect:
5) in the top layer silicon of soi structure, it is coated with a layer photoetching glue, and carries out photoetching making and go out dentation figure；
6) ICP deep etching method is utilized to etch required mass figure；
7) caustic solution is utilized to be fallen by the Metallic film corrosion in the middle of soi structure；
8) caustic solution is utilized to be removed by uppermost for soi structure photoresist, dispensing device structure.
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| CN112666506A (en) * | 2020-12-10 | 2021-04-16 | 中国电子技术标准化研究院 | On-chip capacitor standard sample for integrated circuit calibration |
| CN112820715A (en) * | 2020-12-28 | 2021-05-18 | 中国电子科技集团公司第十三研究所 | Wafer-level on-chip resistor standard sample wafer for calibration and preparation method thereof |
| CN112820714A (en) * | 2020-12-28 | 2021-05-18 | 中国电子科技集团公司第十三研究所 | Wafer-level capacitor standard sample and preparation method thereof |
| CN113866511A (en) * | 2021-08-26 | 2021-12-31 | 中国电子科技集团公司第十三研究所 | On-chip capacitance measuring system and measuring method |
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| CN113866511A (en) * | 2021-08-26 | 2021-12-31 | 中国电子科技集团公司第十三研究所 | On-chip capacitance measuring system and measuring method |
| WO2023178756A1 (en) * | 2022-03-23 | 2023-09-28 | 长鑫存储技术有限公司 | Capacitance measurement method, system and apparatus, and electronic device and storage medium |
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