CN105280538A - IGBT back side manufacturing method capable of realizing refining photolithography of back side - Google Patents
IGBT back side manufacturing method capable of realizing refining photolithography of back side Download PDFInfo
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- CN105280538A CN105280538A CN201510600038.7A CN201510600038A CN105280538A CN 105280538 A CN105280538 A CN 105280538A CN 201510600038 A CN201510600038 A CN 201510600038A CN 105280538 A CN105280538 A CN 105280538A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/682—Mask-wafer alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
Abstract
The invention relates to an IGBT back side manufacturing method capable of realizing refining photolithography of a back side. The manufacturing method includes the steps of: a, obtaining a required front cellular structure on the wafer front of a wafer; b, thinning the wafer back side of the wafer; c, performing the first time of back side ion implantation, and coating a photoresist layer; d, providing a photolithography machine; e, aligning a mask with a reference mark, and scanning a metal layer overlay alignment mark on the wafer by using a penetrating signal emitter; f, correcting the position of the wafer so as to obtain accurate alignment of the wafer with the mask; g, performing exposure and development on the photoresist layer, and performing the required secondary back side ion implantation on the wafer back side after the exposure and development; h, activating carriers after annealing; and i, arranging a back side metal layer. According to the invention, the photolithography alignment can be effectively achieved; the overlay precision can be effectively controlled; the IGBT design demand is satisfied; and the target of refinement of back side figures is really realized without the influence of the back side figures.
Description
Technical field
The present invention relates to a kind of process, especially a kind of IGBT back side manufacture method with diode-built-in, belongs to technical field prepared by IGBT device.
Background technology
IGBT combines power MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor, mos field effect transistor) and the advantage of power transistor, there is operating frequency high, control circuit is simple, current density is high, on-state such as to force down at the feature, is widely used in power control field.In actual applications, IGBT seldom uses as an individual devices, and especially under the condition of inductive load, IGBT needs a fast recovery diode afterflow.Therefore existing IGBT product, the general inverse parallel diode that adopts, to play afterflow effect, protects IGBT device.
For reducing costs, antiparallel diode can be integrated in igbt chip, namely integrated anti-paralleled diode IGBT or there is the IGBT of diode-built-in.Publication number is that the file of CN202796961U discloses a kind of IGBT with diode-built-in, concrete structure can with reference to the accompanying drawing 4 in open file, wherein, in the employing back side, the back side P type of IGBT device and the form of N-type alternating parallel distribution, to form diode-built-in; Front bar shaped cellular and back side bar shaped perpendicular, form the autoregistration of the back side and Facad structure, by the pro rate of back side P type and N-type, rough adjusting device performance.At present, during for preparation back side P type and N-type, can only use bar paten, and the control precision of figure requires comparatively rough, the device solution be suitable for is comparatively limited, does not have universality.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of back side that can realize is provided to become more meticulous the IGBT back side manufacture method of photoetching, its processing step is simple, can effectively realize photoetching contraposition, can control effectively to alignment precision, meet the demand of IGBT design, and not by the impact of back side graphic feature, really realize the target that back side figure becomes more meticulous.
According to technical scheme provided by the invention, a kind of back side that can realize becomes more meticulous the IGBT back side manufacture method of photoetching, and described IGBT back side manufacturing process comprises the steps:
A, provide the wafer of preparation needed for IGBT device, required front technique is carried out in the wafer frontside of described wafer, to obtain required front structure cell in the wafer frontside of wafer, described front structure cell comprises front metal layer and metallic layer overlay alignment mark;
B, carry out thinning to the wafer rear of above-mentioned wafer, with make thinning after obtain wafer thickness be not more than 300 μm;
C, required first backside particulate is carried out to the wafer rear of above-mentioned wafer inject, and wafer rear after ion implantation applies photoresist layer;
D, be provided for the mask aligner photoresist layer that above-mentioned wafer rear applies being carried out to photoetching, described mask aligner comprises lower exposure desk and is positioned at the upper exposure desk above described lower exposure desk, the reference mark being used for mask plate and aiming at is set at the lower surface of upper exposure desk, lower exposure desk is arranged can launch penetrate thinning rear wafer signal penetrate sender unit, upper exposure desk is arranged and penetrates signal receiving device for what receive signal after through wafer;
E, by the wafer rear of above-mentioned wafer upward and be placed between lower exposure desk and upper exposure desk, and the mask plate be positioned at above wafer is aimed at reference mark, and utilize the metallic layer overlay alignment mark penetrated on sender unit scanning wafer;
F, utilize penetrate signal receiving device receive penetrate wafer after penetrate signal, to obtain alignment alignment mark graphical information, according to the position of alignment alignment mark graphical information and reference mark determination wafer, and the centre coordinate of mask plate alignment alignment mark on comparison metallic layer overlay alignment mark and mask plate; According to the centre coordinate of mask plate alignment alignment mark on the centre coordinate of metallic layer overlay alignment mark and mask plate, the position of wafer is corrected, to make the accurate contraposition of wafer and mask plate;
G, mask plate is utilized to carry out exposure imaging to the photoresist layer on wafer rear, and after exposure imaging, carry out required secondary back side ion implantation to wafer rear, the ionic conduction type of described secondary back side ion implantation is contrary with the ionic conduction type that first backside particulate injects;
H, remove the photoresist layer of above-mentioned wafer rear, and activated carrier after annealing, to be distributed in the diode of wafer rear needed for obtaining;
I, required metal layer on back is set at above-mentioned wafer rear.
The shape of described metallic layer overlay alignment mark comprises cross, square, circular, triangle, rhombus, pentagon, hexagon or octagon.
Described step b comprises the steps:
B1, paste blue film in the wafer frontside obtaining front structure cell, and the thinning for the first time of cmp mode is adopted to the back side of described wafer;
B2, remove the above-mentioned blue film being attached to wafer frontside, and at wafer frontside bonding glass substrate, and it is thinning to carry out secondary to the back side of wafer by cmp mode, is no more than 300 μm to make the gross thickness of thinning rear wafer.
The refractive index of described glass substrate is 1.5 ~ 1.8, and reflectivity is 4% ~ 81.6%.
Advantage of the present invention: reference mark is set at the lower surface of upper exposure desk and penetrates signal receiving device, lower exposure desk is arranged and penetrates sender unit, utilize the aligning that reference mark can realize mask plate, utilization penetrates signal receiving device and penetrates sender unit and coordinate, the alignment alignment mark figure of wafer can be obtained, utilize the position of alignment alignment mark figure and reference mark determination wafer, utilize metallic layer overlay alignment mark on the mask plate alignment alignment mark on mask plate and wafer can realize the accurate contraposition between wafer and mask plate, utilize mask plate can carry out exposure imaging to the photoresist on wafer rear, the N doped region of wafer rear can be obtained, the position of P doped region and shape etc., realize back side figure to become more meticulous, safe and reliable.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that the present invention carries out back process.
Exposure desk, 3-reference mark under the upper exposure desk of description of reference numerals: 1-, 2-, 4-penetrates signal receiving device, 5-penetrates sender unit, 6-mask plate, 7-wafer frontside, 8-metallic layer overlay alignment mark, 9-glass substrate, 10-wafer rear, 11-mask plate alignment alignment mark and 12-wafer.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Figure 1: in order to effectively realize photoetching contraposition, can control effectively to alignment precision, meet the demand of IGBT design, and not by the impact of back side graphic feature, really realize the target that back side figure becomes more meticulous, the IGBT back side of the present invention manufacturing process comprises the steps:
A, provide the wafer 12 of preparation needed for IGBT device, required front technique is carried out in the wafer frontside 7 of described wafer 12, to obtain required front structure cell in the wafer frontside 7 of wafer 12, described front structure cell comprises front metal layer and metallic layer overlay alignment mark 8;
Particularly, the material of wafer 12 can be silicon, wafer frontside 7 and wafer rear 10 are two surfaces of wafer 12, conventional front technique can be implemented in wafer frontside 7, to obtain front structure cell, the concrete enforcement structure of front structure cell can structure known by the art personnel, also can carry out selection as required and determine, concrete selection and deterministic process are known by the art personnel, repeat no more herein.Front metal layer obtains metallic layer overlay alignment mark 8 by common process, and the specific implementation process obtaining metallic layer overlay alignment mark 8 repeats no more herein.The shape of described metallic layer overlay alignment mark 8 comprises cross, square, circular, triangle, rhombus, pentagon, hexagon or octagon.The concrete shape of metallic layer overlay alignment mark 8 is not limited to the above-mentioned shape enumerated, and employing criss-cross metallic layer overlay alignment mark 8 has been shown in Fig. 1.
B, carry out thinning to the wafer rear 10 of above-mentioned wafer 12, with make thinning after obtain wafer 12 thickness be not more than 300 μm;
In the embodiment of the present invention, described step b comprises the steps:
B1, paste blue film in the wafer frontside 7 obtaining front structure cell, and the thinning for the first time of cmp mode is adopted to the back side of described wafer 12;
Wafer frontside 7 pastes blue film, is to protect front structure cell not to be scratched; Wafer frontside 7 is pasted the process of blue film and utilizes cmp to carry out thinning process to the back side of wafer 12 to be known by the art personnel, to repeat no more herein.During concrete enforcement, after thinning for the first time, the thickness of wafer 12 can be made to be thinned to 400 μm from 725 μm, guarantee follow-up on wafer 12 after bonding glass substrate 9, glass substrate 9 and the gross thickness of wafer 12 be no more than wafer 12 first thinning before thickness.
B2, remove the above-mentioned blue film being attached to wafer frontside 7, and at wafer frontside 7 bonding glass substrate 9, and it is thinning to carry out secondary to the back side of wafer 12 by cmp mode, is no more than 300 μm to make the gross thickness of thinning rear wafer 12.
In the embodiment of the present invention, the refractive index of described glass substrate 9 is 1.5 ~ 1.8, and reflectivity is 4% ~ 81.6%.After wafer frontside 7 bonding glass substrate 9, the risk of wafer 12 fragment can be reduced.The gross thickness of the front structure cell that the gross thickness of thinning rear wafer 12 refers to wafer 12 and is positioned at wafer frontside 7 is no more than 300 μm.
C, required first backside particulate is carried out to the wafer rear 10 of above-mentioned wafer 12 inject, and wafer rear 10 after ion implantation applies photoresist layer;
In the embodiment of the present invention, the type that first backside particulate injects can be N-type impurity ion or p type impurity ion, and the process that wafer rear 10 applies photoresist layer, known by the art personnel, repeats no more herein.
D, be provided for carrying out the mask aligner of photoetching to the photoresist layer of coating on above-mentioned wafer rear 10, the upper exposure desk 1 that described mask aligner comprises lower exposure desk 2 and is positioned at above described lower exposure desk 2, the reference mark 3 being used for mask plate 6 and aiming at is set at the lower surface of upper exposure desk 1, lower exposure desk 2 is arranged can launch penetrate thinning rear wafer 12 signal penetrate sender unit 5, upper exposure desk 1 is arranged and penetrates signal receiving device 4 for receiving through signal after wafer 12;
In the embodiment of the present invention, upper exposure desk 1, lower exposure desk 2 act on and structure consistent with existing mask aligner, reference mark 3 is positioned at the little surface of exposure desk 1, utilize reference mark 3 as aligning initial point, reference mark 3 pairs of mask plates 6 are utilized to aim at, and utilizing reference mark 3 pairs of mask plates 6 to carry out on time, alignment error depends on the systematic error of mask aligner, and described systematic error can be ignored follow-up back side alignment procedures.Utilize process that reference mark 3 pairs of mask plates 6 are aimed at known by the art personnel, repeat no more herein.
Penetrate that sender unit 5 launches penetrate signal can pass thinning after wafer 12, through penetrating signal and can be penetrated signal receiving device 4 and receive after wafer 12, realize field picture to bit alignment.Penetrate the little surface that signal receiving device 4 is positioned at exposure desk 1, penetrate sender unit 5 and be positioned on lower exposure desk 2, the signal that penetrates penetrating sender unit 5 transmitting can along the axis propagation penetrating signal receiving device 4.Penetrate sender unit 5, penetrate signal receiving device 4 and can adopt existing conventional infrared signal device, penetrate the Master's thesis of " research & design of double face photoetching machine control system " that sender unit 5 can be won with reference to Central China University of Science and Technology Liu Xuan with the concrete engagement process penetrating signal receiving device 4, specifically repeat no more.To on the wafer rear 10 of wafer 12 during photoetching, front metal layer is contained in front, therefore, the surface of front metal layer is general more coarse, have many particles and small massif, and metallic layer overlay alignment mark 8 easily asymmetry change occurs, laser stepped alignment mode easily produces coherent fringe, by spurious signal serious interference, therefore select and penetrate sender unit 5 and penetrate field that signal receiving device 4 coordinates as contraposition alignment so.
E, by the wafer rear 10 of above-mentioned wafer 12 upward and be placed between lower exposure desk 2 and upper exposure desk 1, and aimed at reference mark 3 by the mask plate 6 be positioned at above wafer 12, and utilize the metallic layer overlay alignment mark 8 penetrated on sender unit 5 scanning wafer 12;
In the embodiment of the present invention, mask 6 is positioned at above the wafer rear 10 of wafer 12, penetrates sender unit 5 real time emission and penetrates signal, to scan metallic layer overlay alignment mark 8.Carrying out on time to wafer 12, needing real-time mobile wafer 12.
F, utilize penetrate signal receiving device 4 receive penetrate wafer 12 after penetrate signal, to obtain alignment alignment mark graphical information, the position of wafer 12 is determined according to alignment alignment mark graphical information and reference mark 3, and the centre coordinate of comparison metallic layer overlay alignment mark 8 and mask plate alignment alignment mark 11 on mask plate 6; According to the centre coordinate of mask plate alignment alignment mark 11 on the centre coordinate of metallic layer overlay alignment mark 8 and mask plate 6, the position of wafer 12 is corrected, to make the accurate contraposition of wafer 12 and mask plate 6;
In the embodiment of the present invention, what penetrate that sender unit 5 launches penetrates signal through after metallic layer overlay alignment mark 8, and by penetrating after signal receiving device 4 receives, can obtain alignment alignment mark graphical information.The position of wafer 12 can be determined according to alignment alignment mark graphical information and reference mark 3, according to the centre coordinate of mask plate alignment alignment mark 11 on the centre coordinate of metallic layer overlay alignment mark 8 and mask plate 6, the position of wafer 12 is corrected, to make the accurate contraposition of wafer 12 and mask plate 6, so that after accurate contraposition, the wafer rear 10 of mask plate 6 pairs of wafers 12 is utilized to carry out photoetching.
Shape and the metallic layer overlay alignment mark 8 of mask plate alignment alignment mark 11 are consistent.Reference mark 3 belongs to the contraposition initial point of mask aligner, mask plate 6 and wafer 10 are calibrated with reference mark 3 respectively, the coordinate figure of such mask plate 6 and wafer 10 is all the coordinate relative to reference mark 3, is equivalent to coarse alignment, and both are just of practical significance by ensuing calibrating coordinates.Penetrate signal receiving device 4 by penetrating the alignment aligning graph on Signal analysis wafer 12, calculate the deviation between mask plate alignment alignment mark 11 on the metallic layer overlay alignment mark 8 of wafer 12 and mask plate 6, real-time mobile wafer 10, calibration wafer 10 and reference mark 3 coordinate, until both deviations meet the standard that board judges.
G, the photoresist layer on mask plate 6 pairs of wafer rears 10 is utilized to carry out exposure imaging, and after exposure imaging, carry out required secondary back side ion implantation to wafer rear 10, the ionic conduction type of described secondary back side ion implantation is contrary with the ionic conduction type that first backside particulate injects;
In the embodiment of the present invention, the photoresist layer on mask plate 6 pairs of wafer rears 10 is utilized to carry out exposure imaging, figure after exposure imaging is determined by mask plate 6, image after described exposure imaging can determine the regional location after the ion implantation of the secondary back side, can obtain required N doped region and P doped region by secondary back side ion implantation in wafer rear 10.Concrete shape, the position of N doped region, P doped region all can be determined according to the figure of mask plate 6, are specially known by the art personnel.
H, remove the photoresist layer of above-mentioned wafer rear 10, and activated carrier after annealing, to be distributed in the diode of wafer rear 10 needed for obtaining;
In the embodiment of the present invention, after obtaining forming the N doped region of diode, P doped region, need to remove photoresist layer, remove the process of photoresist layer and the process of annealing activated carrier and process conditions and be known by the art personnel, repeat no more herein.
I, required metal layer on back is set at above-mentioned wafer rear 10.
In the embodiment of the present invention, metal layer on back can cover wafer rear 10 by metal evaporation mode, metal layer on back and N doped region, P doped region ohmic contact.
The present invention arranges reference mark 3 at the lower surface of upper exposure desk 1 and penetrates signal receiving device 4, lower exposure desk 2 is arranged and penetrates sender unit 5, utilize the aligning that reference mark 3 can realize mask plate 6, utilization penetrates signal receiving device 4 and penetrates sender unit 5 and coordinate, the alignment alignment mark figure of wafer 12 can be obtained, alignment alignment mark figure and reference mark 3 is utilized to determine the position of wafer 12, utilize metallic layer overlay alignment mark 8 on the mask plate alignment alignment mark 11 on mask plate 6 and wafer 12 can realize the accurate contraposition between wafer 12 and mask plate 6, utilize mask plate 6 can carry out exposure imaging to the photoresist on wafer rear 10, the N doped region of wafer rear 10 can be obtained, the position of P doped region and shape etc., realize back side figure to become more meticulous, safe and reliable.
Claims (4)
1. can realize the back side to become more meticulous the IGBT back side manufacture method of photoetching, it is characterized in that, described IGBT back side manufacturing process comprises the steps:
(a), the wafer (12) of preparation needed for IGBT device is provided, required front technique is carried out in the wafer frontside (7) of described wafer (12), obtain required front structure cell with the wafer frontside (7) in wafer (12), described front structure cell comprises front metal layer and metallic layer overlay alignment mark (8);
(b), carry out thinning to the wafer rear (10) of above-mentioned wafer (12), with make thinning after obtain wafer (12) thickness be not more than 300 μm;
(c), required first backside particulate carried out to the wafer rear (10) of above-mentioned wafer (12) inject, and wafer rear (10) after ion implantation applies photoresist layer;
(d), be provided for the mask aligner photoresist layer of the upper coating of above-mentioned wafer rear (10) being carried out to photoetching, described mask aligner comprises lower exposure desk (2) and is positioned at the upper exposure desk (1) of described lower exposure desk (2) top, the reference mark (3) being used for mask plate (6) and aiming at is set at the lower surface of upper exposure desk (1), lower exposure desk (2) is arranged can launch penetrate thinning rear wafer (12) signal penetrate sender unit (5), upper exposure desk (1) upper arrange be used for receiving through wafer (12) afterwards signal penetrate signal receiving device (4),
(e), by the wafer rear (10) of above-mentioned wafer (12) upward and be placed between lower exposure desk (2) and upper exposure desk (1), and aimed at reference mark (3) by the mask plate (6) being positioned at wafer (12) top, and utilize the metallic layer overlay alignment mark (8) penetrated on sender unit (5) scanning wafer (12);
(f), utilize penetrate signal receiving device (4) receive penetrate wafer (12) after penetrate signal, to obtain alignment alignment mark graphical information, the position of wafer (12) is determined according to alignment alignment mark graphical information and reference mark (3), and the centre coordinate of comparison metallic layer overlay alignment mark (8) and the upper mask plate alignment alignment mark (11) of mask plate (6); According to the centre coordinate of metallic layer overlay alignment mark (8) and the centre coordinate of the upper mask plate alignment alignment mark (11) of mask plate (6), the position of wafer (12) is corrected, to make the accurate contraposition of wafer (12) and mask plate (6);
(g), utilize mask plate (6) to carry out exposure imaging to the photoresist layer on wafer rear (10), and after exposure imaging, carry out required secondary back side ion implantation to wafer rear (10), the ionic conduction type of described secondary back side ion implantation is contrary with the ionic conduction type that first backside particulate injects;
(h), remove the photoresist layer of above-mentioned wafer rear (10), and activated carrier after annealing, to be distributed in the diode of wafer rear (10) needed for obtaining;
(i), required metal layer on back is set at above-mentioned wafer rear (10).
2. the back side that can realize according to claim 1 becomes more meticulous the IGBT back side manufacture method of photoetching, it is characterized in that: the shape of described metallic layer overlay alignment mark (8) comprises cross, square, circular, triangle, rhombus, pentagon, hexagon or octagon.
3. the back side that can realize according to claim 1 becomes more meticulous the IGBT back side manufacture method of photoetching, and it is characterized in that, described step (b) comprises the steps:
(b1), in the wafer frontside (7) obtaining front structure cell paste blue film, and the thinning for the first time of cmp mode is adopted to the back side of described wafer (12);
(b2), the above-mentioned blue film being attached to wafer frontside (7) is removed, and at wafer frontside (7) bonding glass substrate (9), and it is thinning to carry out secondary to the back side of wafer (12) by cmp mode, is no more than 300 μm to make the gross thickness of thinning rear wafer (12).
4. the back side that can realize according to claim 3 becomes more meticulous the IGBT back side manufacture method of photoetching, it is characterized in that: the refractive index of described glass substrate (9) is 1.5 ~ 1.8, and reflectivity is 4% ~ 81.6%.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510600038.7A CN105280538B (en) | 2015-09-18 | 2015-09-18 | It can realize that the back side becomes more meticulous the IGBT back sides preparation method of photoetching |
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| CN201510600038.7A CN105280538B (en) | 2015-09-18 | 2015-09-18 | It can realize that the back side becomes more meticulous the IGBT back sides preparation method of photoetching |
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| CN116736652A (en) * | 2023-08-11 | 2023-09-12 | 江苏芯德半导体科技有限公司 | Process method for exposure alignment in multilayer high-density packaging |
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