CN103943464A - Alignment mark forming method - Google Patents
Alignment mark forming method Download PDFInfo
- Publication number
- CN103943464A CN103943464A CN201410184978.8A CN201410184978A CN103943464A CN 103943464 A CN103943464 A CN 103943464A CN 201410184978 A CN201410184978 A CN 201410184978A CN 103943464 A CN103943464 A CN 103943464A
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- China
- Prior art keywords
- semiconductor substrate
- alignment mark
- formation method
- reference mark
- alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention provides an alignment mark forming method which includes providing a first semiconductor substrate and a second semiconductor substrate which are subjected to polishing, forming a reference mark on the first semiconductor substrate; conducting bonding on the second semiconductor substrate and the first semiconductor substrate; forming an opening in the second semiconductor substrate and enabling the opening to be exposed to the reference mark on the first semiconductor substrate. Due to the fact that the opening is formed in the second semiconductor substrate, the reference mark in the first semiconductor substrate is exposed, the problem of low product yield caused by the fact that double-side lithography is adopted in an alignment process, and alignment errors and mechanical damage exist is solved, and the alignment accuracy and the product yield are improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of alignment mark.
Background technology
In ic manufacturing process now, manufacturing a complete chip generally will be through the photoetching of tens to twenties times.In photoetching so repeatedly, except photoetching for the first time, the photoetching of all the other levels before exposure all will by the figure of this level with before the pattern alignment that stays of level, i.e. contraposition process.Concrete, so-called contraposition is namely located, in fact it be not directly to aim at contraposition with the figure in Semiconductor substrate with the figure on mask plate, but independent of each other, the position of determining mask plate is an independently process, and the position of determining Semiconductor substrate is again another independently process.Contraposition principle in prior art employing method is, has an alignment mark on exposure desk, it can be regarded as to the initial point of location coordinate system, all other position all relatively this point determine.Respectively mask plate and Semiconductor substrate and this alignment mark just can be determined to their position.Determining behind both positions, the figure on mask plate is transferred in Semiconductor substrate and is aimed at.In other words, measure and determine the position relationship between the alignment mark on alignment mark and the semiconductor substrate surface on mask by the aligning guide on exposure device, so that alignment mark mates to reach aligning mutually.
But, in said method, mainly utilizing dual surface lithography, the alignment mark of realization mates to reach aligning mutually, and its alignment precision is not very high, causes the different circuit elements in integrated circuit the specific location on semiconductor substrate surface not form; Meanwhile, in the time of dual surface lithography, also can cause the mechanical damage of Semiconductor substrate, reduce finished product yield.In order to realize high-precision Aligning degree, improve finished product yield, those skilled in the art meet the solution of this demand always in searching.
Summary of the invention
The object of the present invention is to provide a kind of formation method of alignment mark, use in contraposition process of the prior art to solve, owing to adopting dual surface lithography, introduce deviation of the alignment and mechanical damage, thereby cause the problem that product yield is low.
For solving the problems of the technologies described above, the invention provides a kind of formation method of alignment mark, the formation method of described alignment mark comprises:
The first Semiconductor substrate and second Semiconductor substrate of polishing are provided;
In described the first Semiconductor substrate, form figure and reference mark;
By described the second Semiconductor substrate and described the first Semiconductor substrate bonding;
At the upper formation opening of described the second Semiconductor substrate, described opening exposes the described reference mark in described the first Semiconductor substrate.
Optionally, in the formation method of described alignment mark, figure and reference mark in described the first Semiconductor substrate are formed by photoetching process and etching technics.
Optionally, in the formation method of described alignment mark, the opening of the upper formation of described the second Semiconductor substrate is formed by etching technics.
Optionally, in the formation method of described alignment mark, the lithographic method that described etching technics adopts is wet etching.
Optionally, in the formation method of described alignment mark, the lithographic method that described etching technics adopts is plasma etching.
Optionally, in the formation method of described alignment mark, described the first Semiconductor substrate is monocrystalline silicon.
Optionally, in the formation method of described alignment mark, described the second Semiconductor substrate is monocrystalline silicon.
Optionally, in the formation method of described alignment mark, the quantity of described reference mark is for being more than or equal to two.
In the formation method of alignment mark provided by the present invention, by the upper formation opening in described the second Semiconductor substrate, reference mark in described the first Semiconductor substrate is come out, save in existing contraposition process and needed to adopt dual surface lithography, introduce deviation of the alignment and mechanical damage, cause the problem that product yield is low, improved precision and the product yield of contraposition.
Brief description of the drawings
Figure 1A-1C is the structural representation of each step in the formation method of alignment mark in one embodiment of the invention;
Fig. 2 is the flow chart of each step in the formation method of alignment mark in one embodiment of the invention.
In Figure 1A-1C,
The first Semiconductor substrate-10; The second Semiconductor substrate-20; Figure-11; Reference mark-12; Opening 21.
Embodiment
The formation method of alignment mark the present invention being proposed below in conjunction with the drawings and specific embodiments is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, it is the flow chart of each step in the formation method of alignment mark in one embodiment of the invention.Below with reference to the formation method of the alignment mark described in Fig. 2 and Figure 1A-1C detailed description the present embodiment.
First, perform step S10, the first Semiconductor substrate 10 and second Semiconductor substrate 20 of polishing is provided.
Further, please refer to Figure 1A, described the first Semiconductor substrate 10 and described the second Semiconductor substrate 20 are monocrystalline silicon.
Then, execution step S20 forms reference mark 12 in described the first Semiconductor substrate 10.
Concrete, in described the first Semiconductor substrate 10, be also formed with figure 11, lay the first stone to form different circuit elements in integrated circuit.When forming described figure 11 in described the first Semiconductor substrate 10, form reference mark 12.
Further, the quantity of described reference mark is for being more than or equal to two.
Further, please refer to Figure 1B, the reference mark 12 in described the first Semiconductor substrate 10 is formed by photoetching process and etching technics.Preferably, the lithographic method that described etching technics adopts is wet etching or plasma etching.
Then, execution step S30, by described the second Semiconductor substrate 20 and described the first Semiconductor substrate 10 bondings.
Then, execution step S40, at the upper formation opening 21 of described the second Semiconductor substrate 20, described opening 21 exposes the described reference mark 12 in described the first Semiconductor substrate 10.
Preferably, please refer to Fig. 1 C, formed by etching technics at the opening 21 of the upper formation of described the second Semiconductor substrate 20.
Concrete, please continue to refer to Figure 1A-1C, the first Semiconductor substrate 10 of polishing is positioned on the wafer-supporting platform of mask aligner; CCD (charge coupled device) video camera that makes to be positioned at mask aligner wafer-supporting platform bottom searches out the reference mark in described the first Semiconductor substrate 10 from bottom to top, and is recorded on display; By described the second Semiconductor substrate 20 and described the first Semiconductor substrate 10 bondings, ccd video camera focal length is autofocusing on the nonbonding face of described the second Semiconductor substrate 20, the position of reference mark in described the first Semiconductor substrate 10 recording on display according to mask aligner, through adjusting these three knobs of directions X, Y-direction and angle θ of ccd video camera, on the nonbonding face of described the second Semiconductor substrate 20, carry out etching technics and form opening 21, thereby expose the described reference mark in described the first Semiconductor substrate 10.Whole process has been saved the operation that needs to adopt dual surface lithography in existing contraposition process, introduces deviation of the alignment and mechanical damage, causes the problem that product yield is low, has improved precision and the product yield of contraposition.
To sum up, in the formation method of alignment mark provided by the present invention, by the upper formation opening in described the second Semiconductor substrate, reference mark in described the first Semiconductor substrate is come out, save in existing contraposition process and needed to adopt dual surface lithography, introduce deviation of the alignment and mechanical damage, cause the problem that product yield is low, improved precision and the product yield of contraposition.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (8)
1. a formation method for alignment mark, is characterized in that, comprising:
The first Semiconductor substrate and second Semiconductor substrate of polishing are provided;
In described the first Semiconductor substrate, form figure and reference mark;
By described the second Semiconductor substrate and described the first Semiconductor substrate bonding;
At the upper formation opening of described the second Semiconductor substrate, described opening exposes the described reference mark in described the first Semiconductor substrate.
2. the formation method of alignment mark as claimed in claim 1, is characterized in that, figure and reference mark in described the first Semiconductor substrate are formed by photoetching process and etching technics.
3. the formation method of alignment mark as claimed in claim 1, is characterized in that, the opening of the upper formation of described the second Semiconductor substrate is formed by etching technics.
4. the formation method of the alignment mark as described in claim 2 or 3, is characterized in that, the lithographic method that described etching technics adopts is wet etching.
5. the formation method of the alignment mark as described in claim 2 or 3, is characterized in that, the lithographic method that described etching technics adopts is plasma etching.
6. the formation method of alignment mark as claimed in claim 1, is characterized in that, described the first Semiconductor substrate is monocrystalline silicon.
7. the formation method of alignment mark as claimed in claim 2, is characterized in that, described the second Semiconductor substrate is monocrystalline silicon.
8. the formation method of alignment mark as claimed in claim 2, is characterized in that, the quantity of described reference mark is for being more than or equal to two.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410184978.8A CN103943464A (en) | 2014-05-04 | 2014-05-04 | Alignment mark forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410184978.8A CN103943464A (en) | 2014-05-04 | 2014-05-04 | Alignment mark forming method |
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| CN103943464A true CN103943464A (en) | 2014-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410184978.8A Pending CN103943464A (en) | 2014-05-04 | 2014-05-04 | Alignment mark forming method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448748A (en) * | 2014-07-30 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electronic device |
| CN112466803A (en) * | 2021-02-04 | 2021-03-09 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device |
| CN112530908A (en) * | 2019-09-18 | 2021-03-19 | 芯恩（青岛）集成电路有限公司 | Preparation method of semiconductor device and semiconductor device |
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| CN1158004A (en) * | 1995-09-28 | 1997-08-27 | 日本电气株式会社 | Composite silicon-on-insulator substrate and method of fabricating the same |
| US20050073669A1 (en) * | 2002-12-20 | 2005-04-07 | Asml Netherlands B.V. | Dual sided lithographic substrate imaging |
| US20070210394A1 (en) * | 2006-03-07 | 2007-09-13 | International Business Machines Corporation | Method and structure for improved alignment in MRAM integration |
| CN102610494A (en) * | 2012-03-27 | 2012-07-25 | 上海宏力半导体制造有限公司 | Method for marking wafer, wafer with mark |
-
2014
- 2014-05-04 CN CN201410184978.8A patent/CN103943464A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1158004A (en) * | 1995-09-28 | 1997-08-27 | 日本电气株式会社 | Composite silicon-on-insulator substrate and method of fabricating the same |
| US20050073669A1 (en) * | 2002-12-20 | 2005-04-07 | Asml Netherlands B.V. | Dual sided lithographic substrate imaging |
| US20070210394A1 (en) * | 2006-03-07 | 2007-09-13 | International Business Machines Corporation | Method and structure for improved alignment in MRAM integration |
| CN102610494A (en) * | 2012-03-27 | 2012-07-25 | 上海宏力半导体制造有限公司 | Method for marking wafer, wafer with mark |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448748A (en) * | 2014-07-30 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electronic device |
| CN112530908A (en) * | 2019-09-18 | 2021-03-19 | 芯恩（青岛）集成电路有限公司 | Preparation method of semiconductor device and semiconductor device |
| CN112530908B (en) * | 2019-09-18 | 2023-12-26 | 芯恩（青岛）集成电路有限公司 | Preparation method of semiconductor device and semiconductor device |
| CN112466803A (en) * | 2021-02-04 | 2021-03-09 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device |
| CN112466803B (en) * | 2021-02-04 | 2021-06-25 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device |
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Application publication date: 20140723 |