CN112530908A - Preparation method of semiconductor device and semiconductor device - Google Patents
Preparation method of semiconductor device and semiconductor device Download PDFInfo
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- CN112530908A CN112530908A CN201910879851.0A CN201910879851A CN112530908A CN 112530908 A CN112530908 A CN 112530908A CN 201910879851 A CN201910879851 A CN 201910879851A CN 112530908 A CN112530908 A CN 112530908A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 238000000034 method Methods 0.000 claims abstract description 77
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000001514 detection method Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 abstract description 10
- 235000012431 wafers Nutrition 0.000 description 95
- 238000001459 lithography Methods 0.000 description 10
- 239000011521 glass Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000011897 real-time detection Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention provides a preparation method of a semiconductor device and the semiconductor device, wherein the method comprises the following steps: providing a wafer, wherein the wafer comprises a front surface and a back surface; performing a front side process on the front side, wherein the front side process comprises forming an alignment mark in the wafer; and the local attenuate is carried out to the wafer back, local attenuate includes the wafer back with alignment mark carries out the attenuate in order to the position that vertical direction corresponds the wafer back forms the groove, the groove will alignment mark exposes. The method does not need to thin the whole wafer, thereby avoiding the problems of cost rise, wafer strength reduction and the like; on the other hand, an expensive double-sided alignment photoetching machine is not needed, and the cost of the double-sided photoetching technology is further reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device preparation method used in a semiconductor photoetching process and a semiconductor device formed by the method.
Background
The traditional integrated circuit technology is a typical thin film technology, belongs to a two-dimensional technology, the copying of device patterns is carried out in the same plane, and the alignment between the patterns is realized by aligning visible light with the existing patterns on a silicon wafer through an alignment symbol on a photoetching plate. In micro-electro-mechanical systems (MEMS) or 3D integrated circuit (ic) processes, patterning of the back surface of the substrate is often required, which involves accuracy in alignment of the back surface with the front surface. This requirement is not met by conventional in-plane lithography. To solve this problem, a double-sided photolithography technique has been developed. The basic concept is that if one side (side a or front) of a silicon wafer has been left with a lithographic pattern or trace, it is planned to prepare a pattern on the other side (side B or back) that is aligned with the existing pattern on side a, a process known as double-sided lithography. However, in the case of using visible light (400-700nm) as the alignment light source, the visible light can only penetrate the thickness of the silicon wafer less than 20 μm, and the thickness of the wafer is usually much greater than 20 μm, so that it is difficult to penetrate. In order to solve the problems, on one hand, the whole wafer is thinned to promote the realization of back alignment, on the other hand, a tool is improved, an alignment light source is replaced by infrared light from visible light, and double-sided alignment is carried out by utilizing the characteristic that the infrared light can penetrate through a silicon wafer but is absorbed by air and metal.
Fig. 1-2 illustrate a prior art backside alignment method. As shown in fig. 1, a front side process is performed on a wafer, wherein the wafer 101 has a front side 108 and a back side 109, and the zero layer mark 104 is formed on the wafer 101 and the device layer 102 is formed after the front side process is performed on the wafer 101. Wherein wafer 101 comprises a silicon wafer. The first alignment marks 105 are also formed during the formation of the device layer 102. The pre-process layer 103 is also formed on the device layer 105 after the device layer 105 is formed, and the second alignment mark 106 is also formed in the pre-process layer 103. The visible light 107 used for alignment in the prior art includes light with a wavelength of 400-700nm, while the visible light 107 can only penetrate silicon materials below 20 μm. If an alignment mark is formed in a silicon material and visible light is used as a light source for alignment, it is necessary to ensure that the distance between the surface of the silicon material and the alignment mark is less than 20 μm. As shown in fig. 2, the front side of the wafer 101 is adhered to a carrier sheet 110 prior to back side lithography of the wafer 101. Wherein the slide 110 comprises glass, such that visible light 107 used for alignment can penetrate the slide 110 and reach the second alignment mark 106. A photoresist 111 is formed on the back surface of the wafer to perform a back surface process. Typically, a thinning process is performed on the wafer 101 before the photoresist 111 is formed. The front side 108 needs to be double-sided aligned with the back side 109 before the back side process is performed, wherein the visible light 107 is used for real-time detection and display of the second alignment mark 106 on the front side, and the infrared light 112 is used for real-time detection and display of the zero-layer mark 104 on the back side, so that the back side and the front side are aligned for smooth back side process.
However, the above alignment process has the following drawbacks and problems:
the first, conventional lithography machine generally does not have the capability to align the back side with the front side, and therefore, when back side-to-front side alignment is required, a dedicated double-side alignment lithography machine is used. As can be seen from fig. 1-2, unlike a conventional lithography machine with only front-side alignment function, this double-side alignment lithography machine needs to install an observation lens on the front side of the wafer, and needs to arrange an infrared lens on the back side of the wafer for alignment of the back side and the front side. This increases the cost due to the additional photolithography facilities required. The infrared alignment double-sided lithography has the following inherent defects: firstly, the infrared light has longer wavelength, and the alignment of thin lines is difficult; secondly, the absorption of infrared light by complex metal wiring and air voids present on uneven surfaces will interfere with pattern alignment.
Secondly, the whole wafer needs to be thinned before the back process, which increases the cost, and also reduces the strength of the wafer and may cause problems such as wafer warpage and deformation.
Thirdly, in the whole front process, because the alignment marks need to be arranged in the exposure process among the layers, on one hand, the cost is increased, and on the other hand, the precision is lower when the back surface is aligned with the front surface.
Fourth, a carrier such as glass is required to be adhered to the front surface of the wafer before the back surface process is performed, so that the cost of the double-sided photolithography technology is further increased.
In order to avoid the use of expensive double-side alignment lithography machines and to avoid the problems of cost increase and strength reduction caused by thinning the whole wafer, a better method for manufacturing a semiconductor device in a semiconductor lithography process is needed.
Disclosure of Invention
Embodiments of the present invention provide a better method for manufacturing a semiconductor device, so as to solve the foregoing technical problems in the prior art.
According to a first aspect, embodiments of the present invention provide a method for manufacturing a semiconductor device, the method including the steps of:
providing a wafer, wherein the wafer comprises a front surface and a back surface;
performing a front side process on the front side, wherein the front side process comprises forming an alignment mark in the wafer; and
it is right the wafer back carries out local attenuate, local attenuate include the wafer back with alignment mark carries out the attenuate in the corresponding position of vertical direction and handles with the wafer back forms the groove, the groove will alignment mark exposes.
Optionally, a distance between a surface of the bottom wall of the groove and a surface of the alignment mark on a side close to the bottom wall of the groove is less than 20 μm.
Optionally, the method of forming the trench includes deep silicon etching.
Optionally, the number of the grooves is not less than 5.
Optionally, the cross-sectional shape of the groove comprises square, circular or rectangular.
Optionally, the method further comprises the following steps: providing alignment light that passes through the trench and penetrates the bottom wall of the trench to the alignment mark, thereby enabling detection of the alignment mark.
Optionally, the alignment light comprises visible light.
Optionally, the alignment light comprises visible red light or visible green light.
Optionally, forming the alignment mark in the wafer includes forming a zero layer mark in the wafer.
Optionally, the upper portion of the cross-section of the groove has a width of 500 μm.
Optionally, the width has a tolerance of 100 μm or less.
Optionally, the alignment mark is formed on a side of the wafer away from the back surface.
The present invention also provides a semiconductor device including:
a wafer comprising a front side and a back side;
the alignment mark is formed on one side of the wafer far away from the back surface, and is formed in the front surface process; and
and the groove is formed at a position on one side of the back surface of the wafer, which corresponds to the alignment mark in the vertical direction, and does not expose the alignment mark.
Optionally, a distance between a surface of the bottom wall of the groove and a surface of the alignment mark on a side close to the bottom wall of the groove is less than 20 μm.
Optionally, the number of the grooves is not less than 5.
Optionally, the cross-sectional shape of the groove comprises square, circular or rectangular.
Optionally, the upper portion of the cross-section of the groove has a width of 500 μm.
Optionally, the width has a tolerance of 100 μm or less.
In the invention, the back surface of the wafer is locally thinned to form a deep groove, so that the alignment mark formed on the front surface of the wafer is directly detected on the back surface of the wafer. On one hand, the method does not need to thin the whole wafer, thereby avoiding the problems of cost increase, wafer strength reduction and the like; on the other hand, an expensive double-sided alignment photoetching machine is not needed, so that the cost of the double-sided photoetching technology is further reduced; finally, the method is not only suitable for precise alignment of the back side and the front side of the same wafer, but also suitable for precise alignment between wafers and between bare chips and wafers, and can realize precise alignment without changing the physical properties of the whole wafer.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:
fig. 1 is a schematic diagram illustrating a front-side process performed on a wafer in the prior art.
Fig. 2 is a schematic diagram of a prior art process for performing backside and frontside alignment.
Fig. 3 is a schematic diagram illustrating a backside alignment process in the prior art.
Fig. 4 is a schematic view showing a method for manufacturing a semiconductor device according to the present invention.
Fig. 5 is a schematic view showing a deep trench formed in the present invention.
Fig. 6 is a flowchart showing a method of manufacturing a semiconductor device according to the present invention.
Fig. 7-8 are schematic views showing the local thinning process performed in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, in the process of performing backside alignment, in order to enable infrared light to penetrate through the wafer and detect the alignment mark located in the wafer, the backside of the wafer is generally subjected to an overall thinning process so that the distance between the surface of the backside of the wafer and the alignment mark is within the thickness range that the infrared light can penetrate through. Fig. 3 is a schematic diagram illustrating a back side alignment process performed in the prior art, and as shown in fig. 3(a), a wafer 301 has a front side 302 and a back side 303, and an alignment mark 304 is further formed in the wafer 301, wherein the alignment mark 304 is formed in the front side process and on a side close to the front side 302. As shown in fig. 3(b), the back side 303 of the wafer is subjected to an overall thinning process, and the distance between the surface of the back side 303 of the wafer and the alignment mark 304 is controlled within a thickness range which can be penetrated by alignment light; as shown in fig. 3(c), the alignment mark 304 is detected using the alignment light 305. The above process thins the whole wafer, which increases the cost, and on the other hand, reduces the strength of the wafer and may cause problems such as wafer warpage.
In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device. Fig. 4 is a schematic view showing a method for manufacturing a semiconductor device according to the present invention, fig. 5 is a schematic view showing a deep trench formed according to the present invention, and fig. 6 is a flowchart showing a method for manufacturing a semiconductor device according to the present invention. The method for manufacturing a semiconductor device of the present invention is described in detail below with reference to fig. 4 to 6, and includes the steps of:
and S1, providing the wafer with the alignment mark.
In this step, as shown in fig. 4(a), a wafer 401 has a front surface 402 and a back surface 403, and an alignment mark 404 is also formed in the wafer 401, wherein the alignment mark 404 is formed in the front surface process and on a side close to the front surface 402. Wherein wafer 401 comprises a silicon wafer. In the front side process, a step of forming a semiconductor device on the front side of the wafer 401 is also included.
And S2, locally thinning the back of the wafer.
In this step, as shown in fig. 4(b), the back surface 403 of the wafer 401 is locally thinned, and the local thinning includes thinning the wafer 401 at a position corresponding to the alignment mark 404 in the vertical direction to form at least one deep groove 405 in the wafer 401, where the alignment mark is not exposed by the groove. The method of forming the deep trench 405 includes deep silicon etching. In a specific embodiment, the distance between the surface of the bottom wall of the deep groove 405 and the surface of the side of the alignment mark 404 close to the bottom wall of the groove is less than 20 μm. Fig. 5 is a schematic diagram of a specific deep groove, and in fig. 5, 5 deep grooves 405 are formed on the back surface of the wafer 401, where the 5 deep grooves 405 include 1 deep groove located at the center of the wafer 401 and 4 deep grooves evenly distributed along the circumference of the wafer 401. The number of the deep grooves 405 is not limited to 5, and can be designed according to specific actual requirements. In a specific embodiment, the number of deep grooves 405 is not less than 5, for example, it may be 5, 6, 9, 13, etc. In one particular embodiment, the deep groove 405 has a square cross-sectional shape. However, the deep groove 405 may have other cross-sectional shapes such as a circle, a rectangle, and the like.
And S3, detecting the alignment mark on the back of the wafer.
In this step, as shown in fig. 4(c), alignment light 406 is provided on the back surface of the wafer 401, and the alignment light 406 passes through the deep trench 405 and penetrates through the bottom wall of the deep trench 405 to reach the alignment mark 404, so as to detect the alignment mark 404 and further provide a basis for back surface alignment. Wherein the alignment light 406 comprises visible light.
The alignment method provided by the invention does not need to carry out back thinning treatment on the whole wafer, thereby avoiding the problems of cost increase, wafer strength reduction and the like; on the other hand, an expensive double-sided alignment photoetching machine is not needed, and the cost of the double-sided photoetching technology is further reduced.
Fig. 7-8 show schematic views of the local thinning process performed in the present invention, and how the local thinning is performed is further described below with reference to fig. 7-8.
As shown in fig. 7, a wafer 601 is provided, the wafer 601 having a front side 602 and a back side 603. Wherein the wafer 601 comprises a silicon wafer. First, a front side process is performed on the front side of the wafer 601, and the front side process includes preparing a semiconductor device on the front side of the wafer 601. An alignment mark 605 is also provided on the front surface of the wafer 601. The alignment mark 605 may include one or more. The alignment mark 605 includes a zero layer mark (zero mark). A dielectric layer 604 is further disposed in a partial region of the front surface of the wafer 601, where the dielectric layer may be a silicon glass layer, the silicon glass layer may also be used as a Shallow Trench Isolation (STI) and a sidewall mask, and the material of the glass layer 604 includes Boron Phosphorus Silicon Glass (BPSG) or Undoped Silicon Glass (USG). Semiconductor structures such as interconnect structures, including copper interconnect structures or other types of interconnect structures, may also be formed on the front side 602 of the wafer 601. The interconnect structure includes a dielectric layer 610 and an interconnect layer 611. After the front side process is completed, a back side process is performed on the back side 603 of the wafer 601. As shown in fig. 7, a photoresist 606 is coated on the back side 603 of the wafer, and then the photoresist 606 is patterned to remove the photoresist portion corresponding to the alignment mark 605 in the vertical direction, so that a portion of the wafer surface 607 corresponding to the alignment mark 605 in the vertical direction is exposed on the back side of the wafer 601. Wherein the partial wafer surface 607 has a width of about 500 μm, which may have a tolerance of 100 μm or less. The back side of the wafer 601 is then etched using the patterned photoresist 606 as a mask, thereby forming a number of deep grooves 608 equal to the number of alignment marks 605 on the back side 603 of the wafer, as shown in fig. 8. Wherein the etching comprises deep silicon etching. To achieve alignment with visible light (wavelength 400-700nm), the distance 609 between the bottom wall surface of the deep trench 608 and the alignment mark 605 is less than 20 μm, so that the alignment light can penetrate the wafer 601 and reach the alignment mark 605. The visible light includes visible red or green light. The photoresist 605 may be removed after the etching is completed. In a specific embodiment, the mouth of the deep trench 605 has a width of the same size as the partial wafer surface 607, i.e. a width of about 500 μm, which may have a tolerance below 100 μm.
In the back process, the back thinning treatment in the whole wafer range is not carried out, so that the problems of cost increase, wafer strength reduction and the like are avoided. On the other hand, the alignment mark can be detected only by providing the alignment light on the back surface of the wafer, and an alignment light source is not used on the front surface of the wafer, namely, an expensive double-sided alignment photoetching machine is not needed, so that the cost of the double-sided photoetching technology is further reduced. In the use of the light source, since the distance between the bottom wall surface of the deep groove 608 and the alignment mark 605 is set to be less than 20 μm, the alignment mark can be detected only by visible light, which greatly widens the selection range of the alignment light source.
The foregoing embodiments are merely illustrative of the principles of this invention and its efficacy, rather than limiting it, and various modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention, which is defined in the appended claims.
Claims (18)
1. A method of fabricating a semiconductor device, the method comprising the steps of:
providing a wafer, wherein the wafer comprises a front surface and a back surface;
performing a front side process on the front side, wherein the front side process comprises forming an alignment mark in the wafer; and
it is right the wafer back carries out local attenuate, local attenuate include the wafer back with alignment mark carries out the attenuate in the corresponding position of vertical direction and handles with the wafer back forms the groove, the groove will alignment mark exposes.
2. The method of claim 1, wherein a distance between a surface of a bottom wall of the groove and a surface of a side of the alignment mark close to the bottom wall of the groove is less than 20 μm.
3. The method of claim 1, wherein the method of forming the trench comprises a deep silicon etch.
4. The method of claim 1, wherein the number of slots is not less than 5.
5. The method of claim 1, wherein the cross-sectional shape of the groove comprises a square, circle, or rectangle.
6. The method according to any one of claims 1-5, characterized in that the method further comprises the steps of: providing alignment light that passes through the trench and penetrates the bottom wall of the trench to the alignment mark, thereby enabling detection of the alignment mark.
7. The method of claim 6, wherein the alignment light comprises visible light.
8. The method of claim 7, wherein the alignment light comprises visible red light or visible green light.
9. The method of any of claims 1-5, wherein forming alignment marks in the wafer comprises forming zero layer marks in the wafer.
10. A method according to any of claims 1-5, characterized in that the cross-sectional upper part of the groove has a width of 500 μm.
11. The method of claim 10, wherein the width has a tolerance of 100 μ ι η or less.
12. A method according to any of claims 1 to 5, wherein the alignment marks are formed on the side of the wafer remote from the back side.
13. A semiconductor device, characterized in that the semiconductor device comprises:
a wafer comprising a front side and a back side;
the alignment mark is formed on one side of the wafer far away from the back surface, and is formed in the front surface process; and
and the groove is formed at a position on one side of the back surface of the wafer, which corresponds to the alignment mark in the vertical direction, and does not expose the alignment mark.
14. The semiconductor device according to claim 13, wherein a distance between a surface of a bottom wall of the groove and a surface of a side of the alignment mark close to the bottom wall of the groove is less than 20 μm.
15. The semiconductor device according to claim 13, wherein the number of the grooves is not less than 5.
16. The semiconductor device according to claim 13, wherein a cross-sectional shape of the groove comprises a square, a circle, or a rectangle.
17. A semiconductor device according to any of claims 13-16, characterized in that the upper part of the cross-section of the trench has a width of 500 μm.
18. The semiconductor device according to claim 17, wherein the width has a tolerance of 100 μm or less.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1158004A (en) * | 1995-09-28 | 1997-08-27 | 日本电气株式会社 | Composite silicon-on-insulator substrate and method of fabricating the same |
| CN101034663A (en) * | 2006-03-07 | 2007-09-12 | 国际商业机器公司 | Method and structure for improved alignment in mram integration |
| CN103869638A (en) * | 2014-03-21 | 2014-06-18 | 武汉新芯集成电路制造有限公司 | Photoetching alignment method implemented by penetrating through wafer |
| CN103943464A (en) * | 2014-05-04 | 2014-07-23 | 上海先进半导体制造股份有限公司 | Alignment mark forming method |
| CN104655006A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting alignment between device graph on front face of wafer and back hole on back face |
-
2019
- 2019-09-18 CN CN201910879851.0A patent/CN112530908B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1158004A (en) * | 1995-09-28 | 1997-08-27 | 日本电气株式会社 | Composite silicon-on-insulator substrate and method of fabricating the same |
| CN101034663A (en) * | 2006-03-07 | 2007-09-12 | 国际商业机器公司 | Method and structure for improved alignment in mram integration |
| CN104655006A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting alignment between device graph on front face of wafer and back hole on back face |
| CN103869638A (en) * | 2014-03-21 | 2014-06-18 | 武汉新芯集成电路制造有限公司 | Photoetching alignment method implemented by penetrating through wafer |
| CN103943464A (en) * | 2014-05-04 | 2014-07-23 | 上海先进半导体制造股份有限公司 | Alignment mark forming method |
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