CN105573049A - Proximity nano-lithography double grating automatic alignment marks - Google Patents
Proximity nano-lithography double grating automatic alignment marks Download PDFInfo
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- CN105573049A CN105573049A CN201410620137.7A CN201410620137A CN105573049A CN 105573049 A CN105573049 A CN 105573049A CN 201410620137 A CN201410620137 A CN 201410620137A CN 105573049 A CN105573049 A CN 105573049A
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- grating
- line style
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- alignment
- jointing grating
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Abstract
The invention discloses proximity nano-lithography double grating automatic alignment marks. The automatic alignment marks comprise two groups of alignment marks which are respectively positioned on a mask and a silicon wafer; any one group of the alignment marks comprise a circular grating positioned in the center and linear tiled gratings positioned at four corners; the circular grating is in the middle of any one group of the alignment marks and used for realizing coarse alignment; the linear tiled gratings positioned at the four corners of any one group of the alignment marks are divided into two groups with adjacent periods; the linear tiled gratings positioned at the two upper corners are tiled longitudinally and used for fine alignment in the x direction; the linear tiled gratings positioned at the two lower corners are tiled transversely and used for fine alignment in the y direction. Through the two groups of the alignment marks, high-precision and rapid automatic alignment between the mask and the silicon wafer can be realized.
Description
Technical field
The present invention relates to a kind of auto-alignment mark in photoetching, especially for proximity nano-photoetching double grating auto-alignment mark, belong to technical field of micro and nano fabrication.
Background technology
Along with the research and development of highly integrated circuit and related device, the characteristic dimension of integrated circuit (IC) is more and more little, obtains significant progress with the high resolution micro-nano technology technology being lithographically representative.Close to the feature such as contact type nanometer manufacturing process is simple to operate with it, with low cost, become one of mainstream technology of future generation, as nano impression, array of zone plates imaging and photo-etching and X-ray lithography.Along with the raising of photolithography resolution, mask silicon wafer is aimed at becomes one of principal element affecting device feature size precision;
Existing alignment methods can be based on geometric scheme mark, zone plate and grating marker etc. several substantially.Wherein, the alignment methods based on geometric scheme mark is directly imaged onto on detector by the geometric scheme on mask and silicon chip, then extract profile or the center of two geometric schemes through image procossing, and both calculating relative coordinate is to realize aiming at.Its operation makes simple with alignment mark, but precision is relatively low, is used for the manual-alignment in early stage low resolution photoetching.Based on linear wave strap and the relative displacement all reflecting mask silicon wafer based on the alignment methods of diffraction grating mark with light intensity signal size, higher precision can be reached, but the many factors such as it cannot avoid mask silicon wafer gap to change, mark symmetry, photoresist coating, etching technics are to the disturbing influence of light intensity signal, and need process through complicated circuit, cost is also higher, and automaticity is lower.
Summary of the invention
The technical issues that need to address of the present invention are: overcome the deficiencies in the prior art, there is provided a kind of for proximity nano-photoetching double grating auto-alignment mark, this mark is not vulnerable to the impact of silicon chip technique, and alignment precision is higher, and operation is simple, automaticity is high.
The technology of the present invention solution: a kind of proximity nano-photoetching double grating auto-alignment that is used for marks, and is made up of two groups of alignment marks;
It is characterized in that comprising: round grating 1(1), line style jointing grating 1(2), line style jointing grating 2(3), line style jointing grating 3(4), line style jointing grating 4(5), round grating 2(6), line style jointing grating 5(7), line style jointing grating 6(8), line style jointing grating 7(9) and line style jointing grating 8(10).Round grating 1(1) and round grating 2(6) lay respectively at two groups of alignment mark centers, for realizing coarse alignment; Line style jointing grating 1(2) and line style jointing grating 5(7) lay respectively at two groups of alignment mark upper left position, for realizing x direction fine alignment; Line style jointing grating 2(3) and line style jointing grating 6(8) lay respectively at position, two groups of alignment mark lower left corner, for realizing y direction fine alignment; Line style jointing grating 3(4) and line style jointing grating 7(9) lay respectively at position, two groups of alignment mark upper right corner, for realizing x direction fine alignment; Line style jointing grating 4(5) and line style jointing grating 8(10) lay respectively at two groups of alignment mark upper left position, for realizing y direction fine alignment;
Described round grating 1(1) and round grating 2(6) cycle is respectively Q
1with Q
2, and Q
1with Q
2meet certain proportionate relationship, ratio value is 0.8 ~ 1.2;
Described line style jointing grating 1(2), line style jointing grating 5(7), line style jointing grating 2(3) with line style jointing grating 6(8) be T by the cycle respectively
1with T
2, T
2with T
1two gratings up and down or left and right be spliced to form, and T
1with T
2meet certain proportionate relationship, ratio value is 0.8 ~ 1.2.;
Described line style jointing grating 3(4), line style jointing grating 7(9), line style jointing grating 4(5) with line style jointing grating 8(10) be P by the cycle respectively
1with P
2, P
2with P
1two gratings up and down or left and right be spliced to form, and P
1with P
2meet certain proportionate relationship, ratio value is 0.8 ~ 1.2.;
Described all screen periods should be less than 10 μm;
Described round screen periods Q
1with Q
2any one group of line style screen periods (T should be corresponded to
1with T
2or P
1with P
2) 1/2 within;
The present invention's beneficial effect is compared with prior art:
(1) the present invention is according to the grating marker on spatial phase feature designing mask and silicon chip, can avoid affecting the silicon chip technological factors such as the photoresist of light intensity to the impact of aiming at, have good Technological adaptability and antijamming capability, reach high precision;
Then and make the relative displacement of mask and wafer enter line style jointing grating measurement range (2) first the present invention carries out coarse alignment by round grating; The final fine alignment carried out respectively by the longitudinal spliced grating of line style and the horizontally-spliced grating of line style on x, y direction.This invention is not vulnerable to the impact of silicon chip technique, and alignment precision is higher, and scope of aiming at is large, and operation is simple, and automaticity is high.
Accompanying drawing explanation
Fig. 1 is mask alignment mark schematic layout pattern of the present invention;
Fig. 2 is silicon chip alignment mark schematic layout pattern of the present invention;
Fig. 3 is the striped schematic diagram that in the present invention, two groups of round gratings produce, and wherein Fig. 3 a is mask and wafer misalignment schematic diagram, and Fig. 3 b is that mask and wafer aims at schematic diagram completely;
Fig. 4 is two groups of longitudinal spliced grating schematic layout patterns of line style in the present invention, and wherein Fig. 4 a is positioned at the longitudinal spliced grating schematic layout pattern of mask mark upper left corner line style, and Fig. 4 b is positioned at the longitudinal spliced grating schematic layout pattern of silicon chip mark upper left corner line style;
Fig. 5 is the striped schematic diagram that in the present invention, two groups of longitudinal line style jointing gratings produce, and wherein Fig. 5 a is mask grating and silicon chip grating misalignment schematic diagram, and Fig. 5 b is that mask grating aims at schematic diagram completely with silicon chip grating;
Fig. 6 is the horizontally-spliced grating schematic layout patterns of the present invention's two groups of line styles, and wherein Fig. 6 a is the horizontally-spliced grating schematic layout pattern of mask mark lower right corner line style, and Fig. 6 b is positioned at the horizontally-spliced grating schematic layout pattern of silicon chip mark lower right corner line style;
Embodiment
As shown in Figure 1, mask alignment mark of the present invention is by round grating 1(1), line style jointing grating 1(2), line style jointing grating 2(3), line style jointing grating 3(4), line style jointing grating 4(5) form.Circular grating 1(1) be positioned at mask alignment mark centre position; Line style jointing grating 1(2) be positioned at mask alignment mark upper left position; Line style jointing grating 2(3) be positioned at position, the mask alignment mark lower left corner; Line style jointing grating 3(4) be positioned at position, the mask alignment mark upper right corner; Line style jointing grating 4(5) be positioned at mask alignment mark lower right position;
As shown in Figure 2, silicon chip alignment mark of the present invention is by round grating 2(6), line style jointing grating 5(7), line style jointing grating 6(8), line style jointing grating 7(9) and line style jointing grating 8(10) form.Circular grating 2(6) be positioned at silicon chip alignment mark centre position; Line style jointing grating 5(7) be positioned at silicon chip alignment mark upper left position; Line style jointing grating 6(8) be positioned at position, the silicon chip alignment mark lower left corner; Line style jointing grating 7(9) be positioned at position, the silicon chip alignment mark upper right corner; Line style jointing grating 8(10) be positioned at silicon chip alignment mark lower right position;
As shown in Figure 3, when mask and wafer is overlapping with certain interval (gap length is that 100nm is to 200 μm), circular grating 1(1 in mask alignment mark) with circular grating 2(6 on silicon chip alignment mark) on interference by produce as Fig. 3 a, 3b striped.Wherein circular grating 1(1 in the embodiment of the present invention) cycle Q
1=2 μm, circular grating 2(6) cycle Q
2=2.2 μm.When silicon chip and mask are when existing certain relative displacement, its fringe distribution is as Fig. 3 a, and at this moment two groups of stripeds are easy to be distinguished; When the relative displacement of silicon chip and mask is eliminated as Fig. 3 b, at this moment, mask and wafer coarse alignment completes, and enters mask and silicon chip fine alignment scope;
As Fig. 4 a, shown in 4b, line style jointing grating 1(2 on mask) with line style jointing grating 5(7 on silicon chip) upper two groups of gratings adopt layout as shown in Figure 4, line style jointing grating 1(2) and silicon chip on line style jointing grating 5(7) be respectively P by the cycle respectively
1with P
2, P
2with P
1two gratings form up and down, wherein P in the embodiment of the present invention
1=4 μm, P
2=4.4 μm.When mask and wafer is overlapping with certain interval (gap length is that 100nm is to 200 μm), namely produce two groups of interference fringes.Fig. 5 is two groups of longitudinal spliced interference fringes of grating emulation according to Fig. 4, and when silicon chip and mask exist certain relative displacement in x direction, its fringe distribution is as Fig. 5
a, at this moment upper and lower two groups of fringe spatial frequency are inconsistent, and two groups of stripeds are easy to be distinguished; When the relative displacement of silicon chip and mask is eliminated, two groups of fringe frequency are completely equal, and as 5b, at this moment, mask and wafer has been aimed in the x direction, and reaches perfect condition.In like manner, line style jointing grating 3(4 on mask) with line style jointing grating 7(9 on silicon chip) adopt the layout identical with Fig. 4, difference is that the cycle is respectively T
1with T
2, wherein T in the embodiment of the present invention
1=1 μm, T
2=1.1 μm;
As Fig. 6 a, shown in 6b, line style jointing grating 4(5 on mask) with line style jointing grating 8(10 on silicon chip) upper two groups of gratings adopt layout as shown in Figure 6, line style jointing grating 4(5) and silicon chip on line style jointing grating 8(10) be respectively T by the cycle respectively
1with T
2, T
2with T
1two gratings about form, wherein T in the embodiment of the present invention
1=1 μm, T
2=1.1 μm.When mask and wafer is overlapping with certain interval (gap length is that 100nm is to 200 μm), namely produce about two groups interference fringes of splicing, to realize mask and wafer fine alignment in y-direction.In like manner, line style jointing grating 2(3 on mask) with line style jointing grating 6(8 on silicon chip) adopt the layout identical with Fig. 6, difference is that the cycle is respectively P
1with P
2,wherein P in the embodiment of the present invention
1=4 μm, P
2=4.4 μm;
Non-elaborated part of the present invention belongs to techniques well known.
Claims (6)
1. one kind marks for proximity nano-photoetching double grating auto-alignment, is made up of the two groups of alignment marks laid respectively on mask and wafer; It is characterized in that comprising: round grating 1(1), line style jointing grating 1(2), line style jointing grating 2(3), line style jointing grating 3(4), line style jointing grating 4(5), round grating 2(6), line style jointing grating 5(7), line style jointing grating 6(8), line style jointing grating 7(9) and line style jointing grating 8(10); Round grating 1(1) and round grating 2(6) lay respectively at two groups of alignment mark centers, for realizing coarse alignment; Line style jointing grating 1(2) and line style jointing grating 5(7) lay respectively at two groups of alignment mark upper left position, for realizing x direction fine alignment; Line style jointing grating 2(3) and line style jointing grating 6(8) lay respectively at position, two groups of alignment mark lower left corner, for realizing y direction fine alignment; Line style jointing grating 3(4) and line style jointing grating 7(9) lay respectively at position, two groups of alignment mark upper right corner, for realizing x direction fine alignment; Line style jointing grating 4(5) and line style jointing grating 8(10) lay respectively at two groups of alignment mark upper left position, for realizing y direction fine alignment.
2. according to claim 1 for proximity nano-photoetching double grating auto-alignment mark, it is characterized in that: described round grating 1(1) and round grating 2(6) cycle be respectively as Q
1with Q
2, and Q
1with Q
2meet certain proportionate relationship, ratio value is 0.8 ~ 1.2.
3. according to claim 1 for proximity nano-photoetching double grating auto-alignment mark, to it is characterized in that: described line style jointing grating 1(2), line style jointing grating 5(7), line style jointing grating 2(3) with line style jointing grating 6(8) be T by the cycle respectively
1with T
2, T
2with T
1two gratings up and down or left and right be spliced to form, and T
1with T
2meet certain proportionate relationship, ratio value is 0.8 ~ 1.2.
4. according to claim 1 for proximity nano-photoetching double grating auto-alignment mark, to it is characterized in that: described line style jointing grating 3(4), line style jointing grating 7(9), line style jointing grating 4(5) with line style jointing grating 8(10) be P by the cycle respectively
1with P
2, P
2with P
1two gratings up and down or left and right be spliced to form, and P
1with P
2meet certain proportionate relationship, ratio value is 0.8 ~ 1.2.
5. according to claim 1 for proximity nano-photoetching double grating auto-alignment mark, it is characterized in that: described all screen periods should be less than 10 μm.
6. according to claim 1 for proximity nano-photoetching double grating auto-alignment mark, it is characterized in that: described round screen periods Q
1with Q
2any one group of line style jointing grating cycle (T should be less than or equal to
1with T
2or P
1with P
2) 1/2.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410620137.7A CN105573049A (en) | 2014-11-07 | 2014-11-07 | Proximity nano-lithography double grating automatic alignment marks |
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|---|---|---|---|
| CN201410620137.7A CN105573049A (en) | 2014-11-07 | 2014-11-07 | Proximity nano-lithography double grating automatic alignment marks |
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| Publication Number | Publication Date |
|---|---|
| CN105573049A true CN105573049A (en) | 2016-05-11 |
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ID=55883340
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111383537A (en) * | 2020-04-02 | 2020-07-07 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN112947016A (en) * | 2021-01-26 | 2021-06-11 | 湖北光安伦芯片有限公司 | Method for improving alignment precision of different-machine photoetching mixed operation |
| CN113270392A (en) * | 2021-06-22 | 2021-08-17 | 福建省晋华集成电路有限公司 | Alignment mark structure and semiconductor device |
| CN113552767A (en) * | 2020-04-23 | 2021-10-26 | 无锡华润上华科技有限公司 | Photoetching plate and method for manufacturing integrated circuit |
| CN117492336A (en) * | 2024-01-02 | 2024-02-02 | 天府兴隆湖实验室 | Alignment mark and pattern alignment method |
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Patent Citations (1)
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| CN101369571A (en) * | 2007-08-17 | 2009-02-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, wafer coarse alignment mark and coarse alignment method |
Non-Patent Citations (1)
| Title |
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| 徐锋: "基于莫尔条纹相位解析的纳米对准方法研究", 《基于莫尔条纹相位解析的纳米对准方法研究》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111383537A (en) * | 2020-04-02 | 2020-07-07 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN113552767A (en) * | 2020-04-23 | 2021-10-26 | 无锡华润上华科技有限公司 | Photoetching plate and method for manufacturing integrated circuit |
| CN112947016A (en) * | 2021-01-26 | 2021-06-11 | 湖北光安伦芯片有限公司 | Method for improving alignment precision of different-machine photoetching mixed operation |
| CN112947016B (en) * | 2021-01-26 | 2023-01-03 | 湖北光安伦芯片有限公司 | Method for improving alignment precision of different-machine photoetching mixed operation |
| CN113270392A (en) * | 2021-06-22 | 2021-08-17 | 福建省晋华集成电路有限公司 | Alignment mark structure and semiconductor device |
| CN117492336A (en) * | 2024-01-02 | 2024-02-02 | 天府兴隆湖实验室 | Alignment mark and pattern alignment method |
| CN117492336B (en) * | 2024-01-02 | 2024-04-09 | 天府兴隆湖实验室 | Alignment mark and pattern alignment method |
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Application publication date: 20160511 |
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