CN101201544B

CN101201544B - Semiconductor photolithography method

Info

Publication number: CN101201544B
Application number: CN2006101194052A
Authority: CN
Inventors: 黄玮
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-12-11
Filing date: 2006-12-11
Publication date: 2011-11-02
Anticipated expiration: 2026-12-11
Also published as: CN101201544A

Abstract

The present invention discloses a semiconductor photoetching method and comprises the following steps: firstly, silicon nitride is generated on semiconductor silicon, secondly, silicon nitride is coated with photoresist and then photoetching is conducted to generate a groove, thirdly, photoresist is removed and the surface of the device is plated with silicon dioxide; multiple regularly spread point-shaped auxiliary marks are filled in the area of two sides of the groove of the silicon dioxide and then according to the position of the auxiliary mark, the silicon nitride layer, the silicon dioxide layer and the auxiliary mark can be removed with corrosion and chemical and mechanical polishing; at last, photoresist can be coated between grooves and later technique can be conducted. By adding the auxiliary mark, the invention greatly reduces influence of CMP technique on nesting measurement and ensures accuracy of nesting measurement; therefore, the rate of finished product of the chip is increased.

Description

Semiconductor photolithography method

Technical field

The present invention relates to a kind of semi-conductive process, especially a kind of semi-conductive photoetching method.

Background technology

STI (shallow trench isolation technology), Reverse mask (STI anti-carves technology), CMP (chemically mechanical polishing) are the technology that generally adopts during existing large scale integrated chip is made.Measurement has bigger influence to these technologies to the photoetching alignment.

The main method that the photoetching alignment is measured is: two photoetching levels measuring alignment precision at needs expose respectively to generating and are used for housing and the inside casing that alignment is measured test earlier, in measuring then housing between up and down apart from difference, to calculate the alignment side-play amount.

Anti-carving in the step of general STI technology, these alignment measurement markers do not have the photoresist protection as shown in Figure 1, and the silicon dioxide of deposit can be etched away a part on the mark, carries out next step CMP technology then.

Existing photoetching technological method can as shown in Figure 2, generate silicon nitride 2 earlier referring to Fig. 2 to shown in Figure 6 on semiconductor silicon 1, resist coating 3 and carry out photoetching and obtain raceway groove 4 on silicon nitride 2 is removed photoresist 3, as shown in Figure 3 then afterwards.Fig. 4 plates silicon dioxide 5 at device surface for another example, with the method for chemically mechanical polishing silicon dioxide 5 and silicon nitride 2 is removed then, obtains structure as shown in Figure 5, is coated with photoresist 6 and carries out follow-up technology as Fig. 6 at last.When carrying out chemically mechanical polishing, as shown in Figure 5, may cause the edge 41 of raceway groove 4 asymmetric, cause among Fig. 6 the position of photoresist inaccurate.

Because the singularity of CMP technology, behind the chemical-mechanical polishing step of the silicon dioxide of process deposit, the pattern of alignment measurement markers housing can be asymmetric, as shown in Figure 7, easily cause X1, X2, Y1, the measured deviation of Y2, final to the alignment side-play amount that makes mistake, influence the rate in blocks of chip.The inside casing zone also has step difference simultaneously, influences inside casing photoresist pattern, causes the measurement mistake.

Summary of the invention

Technical matters to be solved by this invention provides a kind of semiconductor photolithography method, can eliminate or reduce the influence that CMP technology is measured alignment, with the accuracy that guarantees that alignment is measured, to improve the yield rate of chip.

For solving the problems of the technologies described above, the technical scheme of semiconductor photolithography method of the present invention is, comprise and on semiconductor silicon, generate earlier silicon nitride, resist coating and carry out photoetching and obtain raceway groove on silicon nitride afterwards, remove photoresist then, plate silicon dioxide at device surface again, on silicon dioxide, fill many regularly arranged point-like aid marks then with photoresist in the zone of raceway groove both sides, according to the position of described aid mark silicon dioxide layer is carried out etching afterwards, silicon dioxide layer and top aid mark are removed in chemically mechanical polishing then, remove silicon nitride layer again, between raceway groove, be coated with photoresist at last and carry out subsequent technique.

The present invention greatly reduces the influence that CMP technology is measured alignment by adding the mode of aid mark, has guaranteed the accuracy that alignment is measured, thereby has improved the yield rate of chip.

Description of drawings

The present invention is further detailed explanation below in conjunction with drawings and Examples:

Fig. 1 is existing alignment measurement markers;

Fig. 2-Fig. 6 is the synoptic diagram of existing photoetching method;

The device architecture synoptic diagram that Fig. 7 obtains for existing photoetching method;

Fig. 8 is the alignment measurement markers that semiconductor photolithography method of the present invention adopted;

Fig. 9-Figure 16 is the synoptic diagram of semiconductor photolithography method of the present invention.

Reference numeral is among the figure, 1. silicon; 2. silicon nitride; 3. photoresist; 4. raceway groove; 41. trench edges; 5. silicon dioxide; 6. photoresist; 7. aid mark.

Embodiment

The alignment measurement markers that semiconductor photolithography method of the present invention adopted can be referring to shown in Figure 8, compare with existing overlay mark, overlay mark of the present invention includes many regularly arranged point-like aid marks 7, thereby limit out a scope, in that carry out can be so that photoetching be more accurate polytechnic the time.

The process of semiconductor photolithography method of the present invention can be referring to Fig. 9 to Figure 16.As shown in Figure 9, generate earlier silicon nitride 2 on semiconductor silicon 1, resist coating 3 and carry out photoetching and obtain raceway groove 4 on silicon nitride 2 is removed photoresist 3, as shown in figure 10 then afterwards.Figure 11 plates silicon dioxide 5 at device surface for another example, and described silicon dioxide layer upper surface has the corresponding depression of the raceway groove that obtains with photoetching.As shown in figure 12, on silicon dioxide 5, fill many regularly arranged point-like aid marks 7 in the specific zone, described aid mark 7 is formed on silicon dioxide layer 5 by the mask plate exposure imaging by photoresist, and the individuality of aid mark 7 is square, described aid mark 7 is distributed in the both sides of raceway groove, to mark the position of raceway groove.Afterwards as shown in figure 13, silicon dioxide layer is carried out etching, expose raceway groove according to the position of aid mark 7.Then as shown in figure 14, carry out chemically mechanical polishing and remove silicon dioxide layer 5 and top aid mark 7.Remove silicon nitride layer 2 afterwards again, as shown in figure 15.Between raceway groove, be coated with photoresist at last and carry out subsequent technique, as shown in figure 16.

The present invention adopts the method that adds auxiliary pattern in photoetching alignment measurement markers, make that the enforcement of CMP (Chemical Mechanical Polishing) process can be more accurate, and be unlikely to influence the precision that alignment is measured as prior art causes the destruction of trench edges, therefore reduced in the integrated circuit production process, CMP (Chemical Mechanical Polishing) process is to the influence of alignment measurement markers, guarantee lithography measurements target symmetry, thereby improve the accuracy that the photoetching alignment is measured, guarantee the yield rate of product.

Claims

1. semiconductor photolithography method, comprise and on semiconductor silicon, generate earlier silicon nitride, resist coating and carry out photoetching and obtain raceway groove on silicon nitride afterwards, remove photoresist then, plate silicon dioxide at device surface again, it is characterized in that, on silicon dioxide, fill many regularly arranged point-like aid marks then with photoresist in the zone of raceway groove both sides, according to the position of described aid mark silicon dioxide layer is carried out etching afterwards, silicon dioxide layer and top aid mark are removed in chemically mechanical polishing then, remove silicon nitride layer again, between raceway groove, be coated with photoresist at last and carry out subsequent technique.

2. semiconductor photolithography method according to claim 1 is characterized in that, the individuality of described aid mark is square.

3. semiconductor photolithography method according to claim 1 is characterized in that, described silicon dioxide layer upper surface has the corresponding depression of the raceway groove that obtains with photoetching.