CN117476457A - Semiconductor manufacturing method and semiconductor device - Google Patents
Semiconductor manufacturing method and semiconductor device Download PDFInfo
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- CN117476457A CN117476457A CN202311831195.XA CN202311831195A CN117476457A CN 117476457 A CN117476457 A CN 117476457A CN 202311831195 A CN202311831195 A CN 202311831195A CN 117476457 A CN117476457 A CN 117476457A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 37
- 230000008569 process Effects 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000000059 patterning Methods 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 6
- 238000005336 cracking Methods 0.000 abstract description 4
- 238000012858 packaging process Methods 0.000 abstract description 3
- VYQRBKCKQCRYEE-UHFFFAOYSA-N ctk1a7239 Chemical compound C12=CC=CC=C2N2CC=CC3=NC=CC1=C32 VYQRBKCKQCRYEE-UHFFFAOYSA-N 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 206
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000004806 packaging method and process Methods 0.000 description 7
- 230000008093 supporting effect Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004927 fusion Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Abstract
The application relates to a semiconductor manufacturing method and a semiconductor device, wherein the semiconductor manufacturing method at least comprises the following steps: providing a first wafer; forming a transistor in a first wafer; providing a second wafer, wherein the second wafer comprises a first surface and a second surface; forming a hard mask layer on a first surface of a second wafer; patterning the hard mask layer; etching at least one part of the second wafer by taking the patterned hard mask layer as shielding, and forming a first hole which is opened downwards from the first surface; bonding the patterned hard mask layer of the second wafer with the front surface of the first wafer, wherein the first hole is sealed by the first wafer after bonding; thinning the back surface of the first wafer; the second surface side of the second wafer is thinned and the first hole is opened. The semiconductor manufacturing method can thin the wafer to a thinner thickness in the packaging process, meanwhile, the defects such as cracking and the like can not occur, and the process precision is easier to control.
Description
Technical Field
The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor manufacturing method and a semiconductor device.
Background
Since the proposal of "moore's law," microelectronic device densities have evolved almost along the predictions of "moore's law. In order to increase circuit density, microelectronic fabrication has evolved from two dimensions to three dimensions. One of the methods is to stack the chips and then package them, thereby producing a three-dimensional circuit packaging technology (3D IC packaging).
The three-dimensional circuit packaging technology comprises packaging laminated three-dimensional packaging, chip laminated three-dimensional packaging, wafer laminated three-dimensional packaging and the like. The three-dimensional package can improve the density of the interconnection lines and reduce the overall height of the device profile. In some packaging processes, it is necessary to thin the wafer to reduce the volume of the wafer, so that the chips continue to be miniaturized and highly integrated under the law of moore.
However, in the process of thinning the wafer, when the wafer is thinned to a certain extent, the wafer becomes extremely fragile, warpage or even chipping is liable to occur, which results in failure to make the wafer smaller in thickness, and further reduction of the wafer volume is limited.
Disclosure of Invention
Aiming at least one defect in the related art, the application provides a semiconductor manufacturing method and a semiconductor device, wherein a wafer can be thinned to a thinner thickness in the packaging process without defects such as cracking, and the process precision is easier to control.
A first aspect of the present application provides a semiconductor manufacturing method, including at least the steps of:
providing a first wafer, wherein the first wafer comprises a front surface and a back surface;
forming a transistor in the first wafer, wherein the transistor is positioned on the front surface of the first wafer or is close to the front surface of the first wafer;
providing a second wafer, wherein the second wafer comprises a first surface and a second surface positioned on the back surface of the first surface;
forming a hard mask layer on a first surface of a second wafer;
patterning the hard mask layer;
etching at least a portion of the second wafer with the patterned hard mask layer as a shadow to form a first hole opened downward from the first surface;
bonding the patterned hard mask layer of the second wafer with the front surface of the first wafer, wherein the first hole is sealed by the first wafer after bonding;
thinning the back surface of the first wafer;
the second surface side of the second wafer is thinned and the first hole is opened.
In some embodiments of the first aspect, the depth of the second wafer is 50 μm to 700 μm with the patterned hard mask layer as a shadow etch.
In some embodiments of the first aspect, thinning the back side of the first wafer to a thickness of 10 μm to 500 μm; and thinning the second surface side of the second wafer to a thickness of 10-500 mu m.
In some embodiments of the first aspect, the transistor is a metal-oxide-semiconductor field effect transistor, and the semiconductor manufacturing method further includes a step of ion implanting a back surface of the thinned first wafer and a step of performing metallization on the back surface of the ion implanted first wafer.
In some embodiments of the first aspect, a second hole is formed in the front side of the first wafer that opens to the metal layer in the mosfet, the second hole being located at a position corresponding to the first hole such that after the first wafer is bonded to the second wafer, the first hole and the second hole interface to form a closed air chamber.
In some embodiments of the first aspect, the hard mask layer comprises a silicon dioxide layer and a silicon nitride layer sequentially formed over the first surface of the second wafer.
In some embodiments of the first aspect, the first hole is formed on the second wafer by a wet etching process, wherein the etching solution used in the wet etching process is KOH or NH 4 OH。
In some embodiments of the first aspect, after etching the second wafer to form the first hole and before bonding the second wafer to the first wafer, the method further comprises a step of chemical mechanical polishing a surface of the patterned hard mask layer.
A second aspect of the present application provides a semiconductor device manufactured according to the semiconductor manufacturing method of any one of the embodiments of the first aspect.
In some embodiments of the second aspect, the semiconductor device includes:
thinning the processed first wafer;
the thinned second wafer is connected with the first wafer in a bonding way;
a transistor formed in the first wafer and adjacent to the second wafer;
a hole penetrating the second wafer and penetrating the transistor of the first wafer;
wherein the thickness of the whole semiconductor device is 50-1200 mu m.
Compared with the prior art, the invention has the advantages and positive effects that:
(1) According to the semiconductor manufacturing method provided by at least one embodiment of the application, the second wafer provides support for the first wafer in the thinning process of the first wafer, so that the first wafer can be thinned to a thinner thickness, meanwhile, the occurrence of defects such as cracking and warping is reduced, and the stability of the process is improved;
(2) According to the semiconductor manufacturing method provided by at least one embodiment of the application, the second wafer used for supporting is directly packaged on the first wafer, a first hole is formed by etching before bonding the second wafer and the first hole, the bottom of the first hole is opened in a thinning mode after bonding the two wafers, so that the difficulty in opening holes is reduced, the risk of damage to transistors caused by opening holes from the back surface of the second wafer after bonding is avoided, and the quality of wafer packaging is improved;
(3) The semiconductor device provided by at least one embodiment of the application has the advantages that the overall thickness can be 50-1200 mu m, the size of the device is reduced, the quality of the device is improved, the production period is shorter, the manufacturing cost is lower, and the market competitiveness is better.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a flow chart of a semiconductor manufacturing method according to an embodiment of the present application;
fig. 2 is a cross-sectional view of a first wafer processed according to a semiconductor manufacturing method provided in an embodiment of the present application;
fig. 3a is a cross-sectional view of a second wafer processed at step S4 in a semiconductor manufacturing method according to an embodiment of the present application;
fig. 3b is a cross-sectional view of the semiconductor manufacturing method according to the embodiment of the present application after the second wafer is processed in step S52;
fig. 3c is a cross-sectional view of the semiconductor manufacturing method according to the embodiment of the present application after the second wafer is processed in step S53;
fig. 3d is a cross-sectional view of a second wafer processed at step S6 in the semiconductor manufacturing method according to the embodiment of the present application;
fig. 4a is a cross-sectional view of a first wafer and a second wafer processed at step S7 in a semiconductor manufacturing method according to an embodiment of the present application;
fig. 4b is a cross-sectional view of the semiconductor manufacturing method according to the embodiment of the present application after processing the first wafer and the second wafer assembly at step S8;
fig. 4c is a cross-sectional view of the semiconductor manufacturing method according to the embodiment of the present application after the first wafer and the second wafer are processed in step S9;
fig. 4d is a cross-sectional view of the first wafer and the second wafer assembly after the blue film is attached in step S9 in the semiconductor manufacturing method according to the embodiment of the present application;
fig. 4e is a cross-sectional view of the semiconductor manufacturing method according to the embodiment of the present application after the first wafer and the second wafer are processed in step S82.
In the figure:
100. a first wafer; 101. a front face; 102. a back surface; 110. a second hole; 120. a back metal layer; 200. a second wafer; 201. a first surface; 202. a second surface; 210. a hard mask layer; 211. a silicon dioxide layer; 212. a silicon nitride layer; 220. a first hole; 300. a photoresist layer; 400. blue film.
Detailed Description
The technical solutions in the embodiments will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the embodiments described herein can be combined with other embodiments without conflict.
It is to be understood that, although the figures may show a particular order of method steps, the order of the steps may differ from what is depicted. Furthermore, two or more steps may be performed simultaneously or partially simultaneously.
In one aspect, the present application provides a semiconductor manufacturing method, as shown in fig. 1, which at least includes the following steps:
s1: providing a first wafer, wherein the first wafer comprises a front surface and a back surface;
s2: forming a transistor in the first wafer, wherein the transistor is positioned on the front surface of the first wafer or is close to the front surface of the first wafer;
s3: providing a second wafer, wherein the second wafer comprises a first surface and a second surface positioned on the back surface of the first surface;
s4: forming a hard mask layer on a first surface of a second wafer;
s5: patterning the hard mask layer;
s6: etching at least a portion of the second wafer with the patterned hard mask layer as a shadow to form a first hole opened downward from the first surface;
s7: bonding the patterned hard mask layer of the second wafer with the front surface of the first wafer, wherein the first hole is sealed by the first wafer after bonding;
s8: thinning the back surface of the first wafer;
s9: the second surface side of the second wafer is thinned and the first hole is opened.
According to the semiconductor manufacturing method provided by the embodiment of the application, the second wafer provides support for the first wafer in the thinning process of the first wafer, so that the first wafer can be thinned to a thinner thickness, meanwhile, the occurrence of defects such as cracking and warping is reduced, and the process stability is improved; the second wafer for supporting is directly packaged on the first wafer, a first hole is formed by etching before bonding the second wafer and the first hole, the bottom of the first hole is opened in a thinning mode after bonding the two wafers, so that the difficulty of opening holes is reduced, the risk of damage to transistors caused by opening holes from the back surface of the second wafer after bonding is avoided, and the quality of wafer packaging is improved; in addition, because the wafer is not a slice, a thinning machine is not required to be customized in addition, and the cost of the machine can be saved.
Hereinafter, each step in the semiconductor manufacturing process will be described in detail with reference to cross-sectional views of each step.
In step S1, a first wafer 100 is provided, and the first wafer 100 may be any material suitable for manufacturing semiconductor devices. For example, silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or the like, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials, or a combination thereof, may be used. In some embodiments, the first wafer 100 may be a silicon wafer or a monocrystalline silicon wafer. As shown in fig. 2, the first wafer 100 includes a front surface 101 and a back surface 102, and in general, in a semiconductor device, one side for forming functional regions such as circuits and transistors is the front surface 101 of the wafer, and the other side facing away from the front surface 101 is the back surface 102 of the wafer. In the present embodiment, the specification and thickness of the first wafer 100 are not limited, and may be specifically selected by a designer according to the needs.
Through step S2, a transistor (not shown) is formed in the first wafer 100 provided in step S1, specifically, the transistor is formed on the front surface 101 of the first wafer 100 or near the front surface 101 of the first wafer 100 and located at a depth below the front surface 101. The transistor is used as a functional device of the semiconductor device and has the functions of detection, rectification, amplification, switching, voltage stabilization, signal adjustment and the like according to different types of the transistor. In some embodiments, the transistor may be a field effect transistor (Field Effect Transistor, FET) or a metal-oxide-semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) or other type of transistor, selected in particular according to the function to be implemented by the semiconductor. The specific forming method of the transistor can refer to related prior art in the field, and the description is omitted herein.
To provide support for the thinning process of the first wafer 100, a second wafer 200 is provided in step S3. In some embodiments, the cross-section of the second wafer 200 is consistent or approximately consistent with the first wafer 100, such that the second wafer 200 may provide good support for the first wafer 100. The material of the second wafer 200 may be the same as the first wafer 100 or may be different from the first wafer 100, which is not limited in this application. In some embodiments, the second wafer 200 may be a silicon wafer or a monocrystalline silicon wafer. For convenience of description, as shown in fig. 3a, upper and lower surfaces of the second wafer 200 are defined as a first surface 201 and a second surface 202 located at the back surface 102 of the first surface 201, respectively. In the present application, there is no limitation on the thickness of the second wafer 200, as long as the supporting effect required for the first wafer 100 during the thinning process can be achieved. From the viewpoints of reducing the volume of the semiconductor device and simplifying the thinning process, the thickness of the second wafer 200 is as small as possible while achieving the supporting effect on the first wafer 100. In some embodiments, the thickness of the second wafer 200 may be selected between 50 μm and 800 μm as desired.
By performing step S4, a hard mask layer 210 is formed on the first surface 201 of the second wafer 200, and a cross-sectional view of the second wafer 200 with the hard mask layer 210 formed thereon is shown in fig. 3a. It will be appreciated that there is no substantial difference between the first surface 201 and the second surface 202 of the second wafer 200 in this application, which is defined for convenience of description only, and thus, it may be described herein that the hard mask layer 210 is formed on the second surface 202 of the second wafer 200, and the first surface 201 and the second surface 202 may be replaced in a subsequent step. In the description of the present application, the hard mask layer 210 is formed on the first surface 201 as an example. In some embodiments, the hard mask layer 210 includes a silicon dioxide layer (SiO) formed sequentially over the first surface 201 of the second wafer 200 2 ) 211 and a silicon nitride layer (SiN) 212. In some embodiments, a furnace tube thermal oxidation process is used to grow SiO on the surface of the second wafer 200 2 A layer of SiO is uniformly grown on the exposed surface of the second wafer 200 by a furnace tube thermal oxidation process 2 That is, dioxygen is formed on both the first surface 201 and the second surface 202 of the second wafer 200Silicon layer 211. Subsequently, a silicon nitride layer 212 is formed by deposition or other process over the silicon dioxide layer 211.
Step S5 is performed to pattern the hard mask layer 210. Specifically, the step of patterning the hard mask layer 210 in step S5 includes: s51: forming a photoresist layer 300 on the hard mask layer 210; s52: a cross-sectional view of the second wafer 200 after patterning the photoresist layer 300 by photolithography and developing the patterned photoresist layer 300 is shown in fig. 3 b; s53: the patterned photoresist layer 300 is used as a mask to etch the hard mask layer 210 to form a patterned hard mask layer 210, and a cross-sectional view of the second wafer 200 after patterning the hard mask layer 210 is shown in fig. 3 c. Specifically, when the hard mask layer 210 is formed on both the first surface 201 and the second surface 202, the photoresist layer 300 is only coated on the first surface 201, the photoresist layer 300 is made of a photosensitive material, the property of the photosensitive material itself of the irradiated portion is changed after the exposure of the light beam in the step S52, the photoresist layer 300 is formed into a desired specific pattern by the action of the developing solution, and the hard mask layer 210 is etched based on the remaining patterned photoresist layer 300, so that the pattern of the photoresist layer 300 is transferred into the hard mask layer 210.
After patterning of the hard mask layer 210 is completed, as shown in fig. 3d, at least a portion of the second wafer 200 is etched downward with the patterned hard mask layer 210 as a mask in step S6, thereby forming a first hole 220 opened downward from the first surface 201. The open position of the first hole 220 corresponds to the transistor position on the first wafer 100 and is defined by the illumination position of the lithography machine. Since more than one transistor is typically formed on the first wafer 100, more than two first holes 220 may be formed. In some embodiments, the depth of the second wafer 200 is 50 μm to 70 μm, on one hand, the etching within this depth range can be easily achieved by the existing etching apparatus, and on the other hand, the etching depth is such that the remaining portion of the second wafer 200 can also easily open the bottom of the first hole 220 by thinning, and the deep etching directly to the transistor portion of the first wafer 100 is avoided, so that the control of the opening depth is easier and the transistor is prevented from being damaged. In one placeIn some embodiments, the first hole 220 is formed on the second wafer 200 by a wet etching process, wherein the etching solution used in the wet etching process is KOH or NH 4 OH; it is to be understood that in other embodiments, processes other than wet etching may be used, such as dry etching, etc., and the present application is not limited thereto.
After the above-described processing is completed on the second wafer 200, before bonding the patterned hard mask layer 210 of the second wafer 200 to the front surface 101 of the first wafer 100, in some embodiments, the method further includes step S61: a step of performing chemical mechanical polishing (Chemical Mechanical Polishing, CMP) on the surface of the patterned hard mask layer 210. The CMP may increase the planarity of the hard mask layer 210 over the first surface 201 of the second wafer 200, which may be more advantageous for subsequent formation of a stable bond connection with the first wafer 100.
Subsequently, step S7 is performed to bond the patterned hard mask layer 210 of the second wafer 200 to the front surface 101 of the first wafer 100, and the cross-sectional view of the wafer assembly formed by the bonded first wafer 100 and second wafer 200 is shown in fig. 4a, where the bonded first hole 220 is closed by the first wafer 100. In some embodiments, the first wafer 100 and the second wafer 200 may be bonded by Direct Bonding (Direct Bonding) or Fusion Bonding (Fusion Bonding); the bonding temperature is between 150 ℃ and 600 ℃, so that the atoms of the hard mask layer 210 on the surface of the second wafer 200 and the atoms on the surface of the first wafer 100 form stable bonding connection, and the stability of bonding connection is improved.
After the second wafer 200 is bonded to the first wafer 100, the second wafer 200 may provide a supporting function for the first wafer 100, and the step S8 is performed to thin the back surface 102 of the first wafer 100, and the cross-sectional view of the wafer assembly after the thinning of the first wafer 100 is shown in fig. 4b, where the first wafer 100 may be thinned to a thinner thickness under the supporting function of the second wafer 200 and no phenomena such as chipping may occur. In some embodiments, in step S8, the back surface 102 of the first wafer 100 is thinned to a thickness of 10 μm to 500 μm of the first wafer 100, and the thickness of the thinning may be selected within the above range as required. Under the supporting action of the second wafer 200, the thinnest of the first wafer 100 can be about 10 μm, so that the thickness of the semiconductor device is greatly reduced, the integration level of the semiconductor device is improved, and the heat dissipation problem of the high-power device can be effectively solved.
When the semiconductor manufacturing method in the present application is used to manufacture an IGBT device, the transistor formed in the first wafer 100 is a metal-oxide-semiconductor field effect transistor (MOSFET), which includes a metal layer for external conductive connection. In some embodiments, before performing step S7 to bond the two wafers, step S21 is further included: as shown in fig. 2, a second hole 110 opened to the metal layer in the MOSFET is formed in the front surface 101 of the first wafer 100, and the position of the second hole 110 corresponds to the position of the first hole 220, further referring to fig. 4a, after the front surface 101 of the first wafer 100 is bonded to the hard mask layer 210 of the second wafer 200 in step S7, the first hole 220 is abutted to the second hole 110 to form a closed air chamber, and the closed air chamber can be opened again for external conductive connection in the subsequent thinning process of the second wafer 200. Because the metal layer in the MOSFET is close to the front surface 101 of the first wafer 100, the etching depth is easy to control in the process of forming the second hole 110 by etching, and the difficulty of performing the deep etching after the first wafer 100 and the second wafer 200 are bonded is avoided. Further, it is understood that step S21 may be performed just after step S2 and before step S7, but in view of the continuity of the preceding and following steps, step S21 is typically performed immediately after step S2.
When the semiconductor manufacturing method in the present application is used for manufacturing an IGBT device, the semiconductor manufacturing method further includes a step of S81 performing ion implantation on the back surface 102 of the thinned first wafer 100 and a step of S82 performing metallization on the back surface 102 of the ion-implanted first wafer 100. P-type impurities and N-type impurities required for forming a collector region and a field stop region are implanted into the back surface 102 of the first wafer 100 through step S81, and ions are sufficiently diffused to a desired depth through a low temperature annealing process after the ion implantation. As shown in fig. 4e, a back metal layer 120 is formed on the back surface 102 of the first wafer 100 in step S82, wherein the metallization process may refer to the prior art, and the description is omitted herein.
In consideration of the connectivity of the process steps, step S81 may be performed after thinning the back surface 102 of the first wafer 100 at step S8 and before thinning the second surface 202 side of the second wafer 200 and opening the first hole 220 at step S9; the metallization of the back surface 102 of the first wafer 100 in step S82 needs to be performed after step S9 is completed, otherwise, the back metal layer 120 formed by the metallization of the back surface 102 of the first wafer 100 is easily damaged by external force during the execution of step S9, which affects the performance of the device.
In step S9, the second surface 202 side of the second wafer 200 is thinned and the first hole 220 is opened, the sealed air chamber formed after bonding is opened, and the cross-sectional view of the wafer assembly after performing this step is shown in fig. 4 c. In this step, the second wafer 200 may be thinned to a thickness of 10 μm to 500 μm as needed, and the first hole 220 opened again may be used for conductive connection of the transistor outward, with the final thickness satisfying the semiconductor device requirements and being able to expose the first hole 220.
In some embodiments, in step S9, when the second wafer 200 is thinned, since the first wafer 100 is thinned to a thinner thickness, in order to further avoid chipping of the first wafer 100 during the thinning process, as shown in fig. 4d, a blue film 400 may be attached to the back surface 102 of the first wafer 100 to support the first wafer 100, and when the second wafer 200 is thinned to a desired thickness, the blue film 400 is removed, and then subsequent metallization steps are performed on the back surface 102 of the first wafer 100.
Another aspect of the present application also provides a semiconductor device manufactured according to the semiconductor manufacturing method of any one of the above embodiments. As shown in fig. 4e, the semiconductor device includes a first wafer 100 and a second wafer 200, both of which have been subjected to thinning treatment, the first wafer 100 and the second wafer 200 being bonded to each other; transistors are formed in the first wafer 100, with the transistors being adjacent to the second wafer 200; holes are formed through the second wafer 200, which holes penetrate through to the transistors of the first wafer 100.
The thickness of the whole semiconductor device provided by the embodiment can be 50-1200 mu m, meanwhile, the defects such as fragments or warpage cannot occur at the lower limit of the thickness, the size of the device is reduced, and the quality of the device is improved; in addition, because each step in the manufacturing process of the device, particularly the opening and the conductive connection step are easier to accurately control, the production period is shorter, the manufacturing cost is lower, and the device has market competitiveness.
In some embodiments, the semiconductor device is an IGBT device, wherein the transistor is a metal-oxide-semiconductor field effect transistor (MOSFET), and a collector region (not shown), a field stop region (not shown), and a back metal layer 120 are formed on the back surface 102 of the first wafer 100.
Finally, it should be noted that: in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same; while the invention has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that: modifications may be made to the specific embodiments of the present invention or equivalents may be substituted for part of the technical features thereof; without departing from the spirit of the invention, it is intended to cover the scope of the invention as claimed.
Claims (10)
1. A method of manufacturing a semiconductor, comprising at least the steps of:
providing a first wafer, wherein the first wafer comprises a front surface and a back surface;
forming a transistor in the first wafer, wherein the transistor is positioned on the front surface of the first wafer or is close to the front surface of the first wafer;
providing a second wafer, wherein the second wafer comprises a first surface and a second surface positioned on the back surface of the first surface;
forming a hard mask layer on the first surface of the second wafer;
patterning the hard mask layer;
etching at least a portion of the second wafer with the patterned hard mask layer as a shadow to form a first hole opened downward from the first surface;
bonding the patterned hard mask layer of the second wafer to the front surface of the first wafer, wherein the first hole is sealed by the first wafer after bonding;
thinning the back surface of the first wafer;
thinning the second surface side of the second wafer and opening the first hole.
2. The method according to claim 1, wherein the depth of the second wafer is 50 μm to 700 μm by using the patterned hard mask layer as a mask.
3. The method according to claim 1, wherein the back surface of the first wafer is thinned to a thickness of 10 μm to 500 μm; and thinning the second surface side of the second wafer until the thickness of the second wafer is 10-500 microns.
4. The method of claim 1, wherein the transistor is a metal-oxide-semiconductor field effect transistor, the method further comprising the step of ion implanting the thinned back surface of the first wafer and the step of performing metallization on the back surface of the ion implanted first wafer.
5. The method of claim 4, wherein a second hole is formed in the front surface of the first wafer, the second hole being open to the metal layer in the mosfet, the second hole being located at a position corresponding to the first hole such that after bonding the first wafer to the second wafer, the first hole and the second hole interface and form a closed air chamber.
6. The semiconductor manufacturing method according to claim 1, wherein the hard mask layer includes a silicon oxide layer and a silicon nitride layer sequentially formed over the first surface of the second wafer.
7. The method of manufacturing a semiconductor device according to claim 1, wherein the first hole is formed in the second wafer by a wet etching process, and an etching solution used in the wet etching process is KOH or NH 4 OH。
8. The method of claim 1, further comprising the step of chemical mechanical polishing a surface of the patterned hard mask layer after etching the second wafer to form the first hole and before bonding the second wafer to the first wafer.
9. A semiconductor device manufactured according to the semiconductor manufacturing method of any one of claims 1 to 8.
10. The semiconductor device according to claim 9, comprising:
thinning the processed first wafer;
the thinned second wafer is connected with the first wafer in a bonding way;
a transistor formed in the first wafer and adjacent to the second wafer;
a hole penetrating through the second wafer and through to the transistor of the first wafer;
wherein the thickness of the whole semiconductor device is 50-1200 mu m.
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| CN114157258A (en) * | 2022-02-09 | 2022-03-08 | 深圳新声半导体有限公司 | Wafer-level packaging structure of temperature compensation type surface acoustic wave filter and manufacturing method |
| WO2023070860A1 (en) * | 2021-10-29 | 2023-05-04 | 长鑫存储技术有限公司 | Semiconductor structure and forming method therefor, and wafer bonding method |
| CN117253790A (en) * | 2023-11-17 | 2023-12-19 | 物元半导体技术(青岛)有限公司 | IGBT device manufacturing method and IGBT device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023070860A1 (en) * | 2021-10-29 | 2023-05-04 | 长鑫存储技术有限公司 | Semiconductor structure and forming method therefor, and wafer bonding method |
| CN114157258A (en) * | 2022-02-09 | 2022-03-08 | 深圳新声半导体有限公司 | Wafer-level packaging structure of temperature compensation type surface acoustic wave filter and manufacturing method |
| CN117253790A (en) * | 2023-11-17 | 2023-12-19 | 物元半导体技术(青岛)有限公司 | IGBT device manufacturing method and IGBT device |
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